2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
47 #include <sys/_iovec.h>
49 #include <machine/vmm.h>
53 #define KASSERT(exp,msg) assert((exp))
56 #include <machine/vmm_instruction_emul.h>
58 #include <x86/specialreg.h>
60 /* struct vie_op.op_type */
74 /* struct vie_op.op_flags */
75 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
76 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
77 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
78 #define VIE_OP_F_NO_MODRM (1 << 3)
80 static const struct vie_op two_byte_opcodes[256] = {
83 .op_type = VIE_OP_TYPE_MOVZX,
87 .op_type = VIE_OP_TYPE_MOVZX,
91 .op_type = VIE_OP_TYPE_MOVSX,
95 static const struct vie_op one_byte_opcodes[256] = {
98 .op_type = VIE_OP_TYPE_TWO_BYTE
102 .op_type = VIE_OP_TYPE_CMP,
106 .op_type = VIE_OP_TYPE_MOV,
110 .op_type = VIE_OP_TYPE_MOV,
114 .op_type = VIE_OP_TYPE_MOV,
118 .op_type = VIE_OP_TYPE_MOV,
122 .op_type = VIE_OP_TYPE_MOV,
123 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
127 .op_type = VIE_OP_TYPE_MOV,
128 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
131 /* XXX Group 11 extended opcode - not just MOV */
133 .op_type = VIE_OP_TYPE_MOV,
134 .op_flags = VIE_OP_F_IMM8,
138 .op_type = VIE_OP_TYPE_MOV,
139 .op_flags = VIE_OP_F_IMM,
143 .op_type = VIE_OP_TYPE_AND,
146 /* XXX Group 1 extended opcode - not just AND */
148 .op_type = VIE_OP_TYPE_AND,
149 .op_flags = VIE_OP_F_IMM,
152 /* XXX Group 1 extended opcode - not just OR */
154 .op_type = VIE_OP_TYPE_OR,
155 .op_flags = VIE_OP_F_IMM8,
158 /* XXX Group 5 extended opcode - not just PUSH */
160 .op_type = VIE_OP_TYPE_PUSH,
165 #define VIE_MOD_INDIRECT 0
166 #define VIE_MOD_INDIRECT_DISP8 1
167 #define VIE_MOD_INDIRECT_DISP32 2
168 #define VIE_MOD_DIRECT 3
172 #define VIE_RM_DISP32 5
174 #define GB (1024 * 1024 * 1024)
176 static enum vm_reg_name gpr_map[16] = {
195 static uint64_t size2mask[] = {
199 [8] = 0xffffffffffffffff,
203 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
207 error = vm_get_register(vm, vcpuid, reg, rval);
213 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
216 *reg = gpr_map[vie->reg];
219 * 64-bit mode imposes limitations on accessing legacy high byte
222 * The legacy high-byte registers cannot be addressed if the REX
223 * prefix is present. In this case the values 4, 5, 6 and 7 of the
224 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
226 * If the REX prefix is not present then the values 4, 5, 6 and 7
227 * of the 'ModRM:reg' field address the legacy high-byte registers,
228 * %ah, %ch, %dh and %bh respectively.
230 if (!vie->rex_present) {
231 if (vie->reg & 0x4) {
233 *reg = gpr_map[vie->reg & 0x3];
239 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
243 enum vm_reg_name reg;
245 vie_calc_bytereg(vie, ®, &lhbr);
246 error = vm_get_register(vm, vcpuid, reg, &val);
249 * To obtain the value of a legacy high byte register shift the
250 * base register right by 8 bits (%ah = %rax >> 8).
260 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
262 uint64_t origval, val, mask;
264 enum vm_reg_name reg;
266 vie_calc_bytereg(vie, ®, &lhbr);
267 error = vm_get_register(vm, vcpuid, reg, &origval);
273 * Shift left by 8 to store 'byte' in a legacy high
279 val |= origval & ~mask;
280 error = vm_set_register(vm, vcpuid, reg, val);
286 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
287 uint64_t val, int size)
295 error = vie_read_register(vm, vcpuid, reg, &origval);
298 val &= size2mask[size];
299 val |= origval & ~size2mask[size];
310 error = vm_set_register(vm, vcpuid, reg, val);
315 * Return the status flags that would result from doing (x - y).
318 getcc16(uint16_t x, uint16_t y)
322 __asm __volatile("sub %1,%2; pushfq; popq %0" :
323 "=r" (rflags) : "m" (y), "r" (x));
328 getcc32(uint32_t x, uint32_t y)
332 __asm __volatile("sub %1,%2; pushfq; popq %0" :
333 "=r" (rflags) : "m" (y), "r" (x));
338 getcc64(uint64_t x, uint64_t y)
342 __asm __volatile("sub %1,%2; pushfq; popq %0" :
343 "=r" (rflags) : "m" (y), "r" (x));
348 getcc(int opsize, uint64_t x, uint64_t y)
350 KASSERT(opsize == 2 || opsize == 4 || opsize == 8,
351 ("getcc: invalid operand size %d", opsize));
354 return (getcc16(x, y));
355 else if (opsize == 4)
356 return (getcc32(x, y));
358 return (getcc64(x, y));
362 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
363 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
366 enum vm_reg_name reg;
373 switch (vie->op.op_byte) {
376 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
378 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
380 size = 1; /* override for byte operation */
381 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
383 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
387 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
388 * 89/r: mov r/m16, r16
389 * 89/r: mov r/m32, r32
390 * REX.W + 89/r mov r/m64, r64
392 reg = gpr_map[vie->reg];
393 error = vie_read_register(vm, vcpuid, reg, &val);
395 val &= size2mask[size];
396 error = memwrite(vm, vcpuid, gpa, val, size, arg);
401 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
403 * REX + 8A/r: mov r8, r/m8
405 size = 1; /* override for byte operation */
406 error = memread(vm, vcpuid, gpa, &val, size, arg);
408 error = vie_write_bytereg(vm, vcpuid, vie, val);
412 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
413 * 8B/r: mov r16, r/m16
414 * 8B/r: mov r32, r/m32
415 * REX.W 8B/r: mov r64, r/m64
417 error = memread(vm, vcpuid, gpa, &val, size, arg);
419 reg = gpr_map[vie->reg];
420 error = vie_update_register(vm, vcpuid, reg, val, size);
425 * MOV from seg:moffset to AX/EAX/RAX
426 * A1: mov AX, moffs16
427 * A1: mov EAX, moffs32
428 * REX.W + A1: mov RAX, moffs64
430 error = memread(vm, vcpuid, gpa, &val, size, arg);
432 reg = VM_REG_GUEST_RAX;
433 error = vie_update_register(vm, vcpuid, reg, val, size);
438 * MOV from AX/EAX/RAX to seg:moffset
439 * A3: mov moffs16, AX
440 * A3: mov moffs32, EAX
441 * REX.W + A3: mov moffs64, RAX
443 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
445 val &= size2mask[size];
446 error = memwrite(vm, vcpuid, gpa, val, size, arg);
451 * MOV from imm8 to mem (ModRM:r/m)
452 * C6/0 mov r/m8, imm8
453 * REX + C6/0 mov r/m8, imm8
455 size = 1; /* override for byte operation */
456 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
460 * MOV from imm16/imm32 to mem (ModRM:r/m)
461 * C7/0 mov r/m16, imm16
462 * C7/0 mov r/m32, imm32
463 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
465 val = vie->immediate & size2mask[size];
466 error = memwrite(vm, vcpuid, gpa, val, size, arg);
476 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
477 mem_region_read_t memread, mem_region_write_t memwrite,
481 enum vm_reg_name reg;
487 switch (vie->op.op_byte) {
490 * MOV and zero extend byte from mem (ModRM:r/m) to
493 * 0F B6/r movzx r16, r/m8
494 * 0F B6/r movzx r32, r/m8
495 * REX.W + 0F B6/r movzx r64, r/m8
498 /* get the first operand */
499 error = memread(vm, vcpuid, gpa, &val, 1, arg);
503 /* get the second operand */
504 reg = gpr_map[vie->reg];
506 /* zero-extend byte */
509 /* write the result */
510 error = vie_update_register(vm, vcpuid, reg, val, size);
514 * MOV and zero extend word from mem (ModRM:r/m) to
517 * 0F B7/r movzx r32, r/m16
518 * REX.W + 0F B7/r movzx r64, r/m16
520 error = memread(vm, vcpuid, gpa, &val, 2, arg);
524 reg = gpr_map[vie->reg];
526 /* zero-extend word */
529 error = vie_update_register(vm, vcpuid, reg, val, size);
533 * MOV and sign extend byte from mem (ModRM:r/m) to
536 * 0F BE/r movsx r16, r/m8
537 * 0F BE/r movsx r32, r/m8
538 * REX.W + 0F BE/r movsx r64, r/m8
541 /* get the first operand */
542 error = memread(vm, vcpuid, gpa, &val, 1, arg);
546 /* get the second operand */
547 reg = gpr_map[vie->reg];
549 /* sign extend byte */
552 /* write the result */
553 error = vie_update_register(vm, vcpuid, reg, val, size);
562 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
563 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
566 enum vm_reg_name reg;
572 switch (vie->op.op_byte) {
575 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
578 * 23/r and r16, r/m16
579 * 23/r and r32, r/m32
580 * REX.W + 23/r and r64, r/m64
583 /* get the first operand */
584 reg = gpr_map[vie->reg];
585 error = vie_read_register(vm, vcpuid, reg, &val1);
589 /* get the second operand */
590 error = memread(vm, vcpuid, gpa, &val2, size, arg);
594 /* perform the operation and write the result */
596 error = vie_update_register(vm, vcpuid, reg, val1, size);
600 * AND mem (ModRM:r/m) with immediate and store the
603 * 81 /4 and r/m16, imm16
604 * 81 /4 and r/m32, imm32
605 * REX.W + 81 /4 and r/m64, imm32 sign-extended to 64
607 * Currently, only the AND operation of the 0x81 opcode
608 * is implemented (ModRM:reg = b100).
610 if ((vie->reg & 7) != 4)
613 /* get the first operand */
614 error = memread(vm, vcpuid, gpa, &val1, size, arg);
619 * perform the operation with the pre-fetched immediate
620 * operand and write the result
622 val1 &= vie->immediate;
623 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
632 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
633 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
641 switch (vie->op.op_byte) {
644 * OR mem (ModRM:r/m) with immediate and store the
647 * 83 /1 OR r/m16, imm8 sign-extended to 16
648 * 83 /1 OR r/m32, imm8 sign-extended to 32
649 * REX.W + 83/1 OR r/m64, imm8 sign-extended to 64
651 * Currently, only the OR operation of the 0x83 opcode
652 * is implemented (ModRM:reg = b001).
654 if ((vie->reg & 7) != 1)
657 /* get the first operand */
658 error = memread(vm, vcpuid, gpa, &val1, size, arg);
663 * perform the operation with the pre-fetched immediate
664 * operand and write the result
666 val1 |= vie->immediate;
667 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
675 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
678 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
679 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
682 uint64_t op1, op2, rflags, rflags2;
683 enum vm_reg_name reg;
686 switch (vie->op.op_byte) {
689 * 3B/r CMP r16, r/m16
690 * 3B/r CMP r32, r/m32
691 * REX.W + 3B/r CMP r64, r/m64
693 * Compare first operand (reg) with second operand (r/m) and
694 * set status flags in EFLAGS register. The comparison is
695 * performed by subtracting the second operand from the first
696 * operand and then setting the status flags.
699 /* Get the first operand */
700 reg = gpr_map[vie->reg];
701 error = vie_read_register(vm, vcpuid, reg, &op1);
705 /* Get the second operand */
706 error = memread(vm, vcpuid, gpa, &op2, size, arg);
714 rflags2 = getcc(size, op1, op2);
715 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
718 rflags &= ~RFLAGS_STATUS_BITS;
719 rflags |= rflags2 & RFLAGS_STATUS_BITS;
721 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
726 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
727 struct vm_guest_paging *paging, mem_region_read_t memread,
728 mem_region_write_t memwrite, void *arg)
731 struct vm_copyinfo copyinfo[2];
733 struct iovec copyinfo[2];
735 struct seg_desc ss_desc;
736 uint64_t cr0, rflags, rsp, stack_gla, val;
737 int error, size, stackaddrsize;
740 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
742 * PUSH is part of the group 5 extended opcodes and is identified
743 * by ModRM:reg = b110.
745 if ((vie->reg & 7) != 6)
750 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
752 if (paging->cpu_mode == CPU_MODE_REAL) {
754 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
756 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
757 * - Stack pointer size is always 64-bits.
758 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
759 * - 16-bit PUSH/POP is supported by using the operand size
760 * override prefix (66H).
763 size = vie->opsize_override ? 2 : 8;
766 * In protected or compability mode the 'B' flag in the
767 * stack-segment descriptor determines the size of the
770 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
771 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
773 if (SEG_DESC_DEF32(ss_desc.access))
779 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
780 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
782 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
783 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
785 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
786 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
789 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
790 rsp, size, stackaddrsize, PROT_WRITE, &stack_gla)) {
791 vm_inject_ss(vm, vcpuid, 0);
795 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
796 vm_inject_ss(vm, vcpuid, 0);
800 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
801 vm_inject_ac(vm, vcpuid, 0);
805 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size, PROT_WRITE,
806 copyinfo, nitems(copyinfo));
809 * XXX cannot return a negative error value here because it
810 * ends up being the return value of the VM_RUN() ioctl and
811 * is interpreted as a pseudo-error (for e.g. ERESTART).
814 } else if (error == 1) {
815 /* Resume guest execution to handle page fault */
819 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
821 vm_copyout(vm, vcpuid, &val, copyinfo, size);
822 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
824 KASSERT(error == 0, ("error %d updating rsp", error));
827 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
833 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
834 struct vm_guest_paging *paging, mem_region_read_t memread,
835 mem_region_write_t memwrite, void *memarg)
842 switch (vie->op.op_type) {
843 case VIE_OP_TYPE_PUSH:
844 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
847 case VIE_OP_TYPE_CMP:
848 error = emulate_cmp(vm, vcpuid, gpa, vie,
849 memread, memwrite, memarg);
851 case VIE_OP_TYPE_MOV:
852 error = emulate_mov(vm, vcpuid, gpa, vie,
853 memread, memwrite, memarg);
855 case VIE_OP_TYPE_MOVSX:
856 case VIE_OP_TYPE_MOVZX:
857 error = emulate_movx(vm, vcpuid, gpa, vie,
858 memread, memwrite, memarg);
860 case VIE_OP_TYPE_AND:
861 error = emulate_and(vm, vcpuid, gpa, vie,
862 memread, memwrite, memarg);
865 error = emulate_or(vm, vcpuid, gpa, vie,
866 memread, memwrite, memarg);
877 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
879 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
880 ("%s: invalid size %d", __func__, size));
881 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
883 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
886 return ((gla & (size - 1)) ? 1 : 0);
890 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
894 if (cpu_mode != CPU_MODE_64BIT)
898 * The value of the bit 47 in the 'gla' should be replicated in the
899 * most significant 16 bits.
901 mask = ~((1UL << 48) - 1);
902 if (gla & (1UL << 47))
903 return ((gla & mask) != mask);
905 return ((gla & mask) != 0);
909 vie_size2mask(int size)
911 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
912 ("vie_size2mask: invalid size %d", size));
913 return (size2mask[size]);
917 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
918 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
919 int prot, uint64_t *gla)
921 uint64_t firstoff, low_limit, high_limit, segbase;
924 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
925 ("%s: invalid segment %d", __func__, seg));
926 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
927 ("%s: invalid operand size %d", __func__, length));
928 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
929 ("%s: invalid prot %#x", __func__, prot));
932 if (cpu_mode == CPU_MODE_64BIT) {
933 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
934 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
937 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
938 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
941 * If the segment selector is loaded with a NULL selector
942 * then the descriptor is unusable and attempting to use
943 * it results in a #GP(0).
945 if (SEG_DESC_UNUSABLE(desc->access))
949 * The processor generates a #NP exception when a segment
950 * register is loaded with a selector that points to a
951 * descriptor that is not present. If this was the case then
952 * it would have been checked before the VM-exit.
954 KASSERT(SEG_DESC_PRESENT(desc->access),
955 ("segment %d not present: %#x", seg, desc->access));
958 * The descriptor type must indicate a code/data segment.
960 type = SEG_DESC_TYPE(desc->access);
961 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
962 "descriptor type %#x", seg, type));
964 if (prot & PROT_READ) {
965 /* #GP on a read access to a exec-only code segment */
966 if ((type & 0xA) == 0x8)
970 if (prot & PROT_WRITE) {
972 * #GP on a write access to a code segment or a
973 * read-only data segment.
975 if (type & 0x8) /* code segment */
978 if ((type & 0xA) == 0) /* read-only data seg */
983 * 'desc->limit' is fully expanded taking granularity into
986 if ((type & 0xC) == 0x4) {
987 /* expand-down data segment */
988 low_limit = desc->limit + 1;
989 high_limit = SEG_DESC_DEF32(desc->access) ?
992 /* code segment or expand-up data segment */
994 high_limit = desc->limit;
998 offset &= vie_size2mask(addrsize);
999 if (offset < low_limit || offset > high_limit)
1007 * In 64-bit mode all segments except %fs and %gs have a segment
1008 * base address of 0.
1010 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1011 seg != VM_REG_GUEST_GS) {
1014 segbase = desc->base;
1018 * Truncate 'firstoff' to the effective address size before adding
1019 * it to the segment base.
1021 firstoff &= vie_size2mask(addrsize);
1022 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1028 vie_init(struct vie *vie)
1031 bzero(vie, sizeof(struct vie));
1033 vie->base_register = VM_REG_LAST;
1034 vie->index_register = VM_REG_LAST;
1038 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1043 error_code |= PGEX_P;
1044 if (prot & VM_PROT_WRITE)
1045 error_code |= PGEX_W;
1047 error_code |= PGEX_U;
1049 error_code |= PGEX_RSV;
1050 if (prot & VM_PROT_EXECUTE)
1051 error_code |= PGEX_I;
1053 return (error_code);
1057 ptp_release(void **cookie)
1059 if (*cookie != NULL) {
1060 vm_gpa_release(*cookie);
1066 ptp_hold(struct vm *vm, vm_paddr_t ptpphys, size_t len, void **cookie)
1070 ptp_release(cookie);
1071 ptr = vm_gpa_hold(vm, ptpphys, len, VM_PROT_RW, cookie);
1076 vmm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1077 uint64_t gla, int prot, uint64_t *gpa)
1079 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1081 uint64_t *ptpbase, ptpphys, pte, pgsize;
1082 uint32_t *ptpbase32, pte32;
1085 usermode = (paging->cpl == 3 ? 1 : 0);
1086 writable = prot & VM_PROT_WRITE;
1091 ptpphys = paging->cr3; /* root of the page tables */
1092 ptp_release(&cookie);
1096 if (vie_canonical_check(paging->cpu_mode, gla)) {
1098 * XXX assuming a non-stack reference otherwise a stack fault
1099 * should be generated.
1101 vm_inject_gp(vm, vcpuid);
1105 if (paging->paging_mode == PAGING_MODE_FLAT) {
1110 if (paging->paging_mode == PAGING_MODE_32) {
1112 while (--nlevels >= 0) {
1113 /* Zero out the lower 12 bits. */
1116 ptpbase32 = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1118 if (ptpbase32 == NULL)
1121 ptpshift = PAGE_SHIFT + nlevels * 10;
1122 ptpindex = (gla >> ptpshift) & 0x3FF;
1123 pgsize = 1UL << ptpshift;
1125 pte32 = ptpbase32[ptpindex];
1127 if ((pte32 & PG_V) == 0 ||
1128 (usermode && (pte32 & PG_U) == 0) ||
1129 (writable && (pte32 & PG_RW) == 0)) {
1130 pfcode = pf_error_code(usermode, prot, 0,
1132 vm_inject_pf(vm, vcpuid, pfcode, gla);
1137 * Emulate the x86 MMU's management of the accessed
1138 * and dirty flags. While the accessed flag is set
1139 * at every level of the page table, the dirty flag
1140 * is only set at the last level providing the guest
1143 if ((pte32 & PG_A) == 0) {
1144 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1145 pte32, pte32 | PG_A) == 0) {
1150 /* XXX must be ignored if CR4.PSE=0 */
1151 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1157 /* Set the dirty bit in the page table entry if necessary */
1158 if (writable && (pte32 & PG_M) == 0) {
1159 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1160 pte32, pte32 | PG_M) == 0) {
1165 /* Zero out the lower 'ptpshift' bits */
1166 pte32 >>= ptpshift; pte32 <<= ptpshift;
1167 *gpa = pte32 | (gla & (pgsize - 1));
1171 if (paging->paging_mode == PAGING_MODE_PAE) {
1172 /* Zero out the lower 5 bits and the upper 32 bits */
1173 ptpphys &= 0xffffffe0UL;
1175 ptpbase = ptp_hold(vm, ptpphys, sizeof(*ptpbase) * 4, &cookie);
1176 if (ptpbase == NULL)
1179 ptpindex = (gla >> 30) & 0x3;
1181 pte = ptpbase[ptpindex];
1183 if ((pte & PG_V) == 0) {
1184 pfcode = pf_error_code(usermode, prot, 0, pte);
1185 vm_inject_pf(vm, vcpuid, pfcode, gla);
1194 while (--nlevels >= 0) {
1195 /* Zero out the lower 12 bits and the upper 12 bits */
1196 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1198 ptpbase = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1199 if (ptpbase == NULL)
1202 ptpshift = PAGE_SHIFT + nlevels * 9;
1203 ptpindex = (gla >> ptpshift) & 0x1FF;
1204 pgsize = 1UL << ptpshift;
1206 pte = ptpbase[ptpindex];
1208 if ((pte & PG_V) == 0 ||
1209 (usermode && (pte & PG_U) == 0) ||
1210 (writable && (pte & PG_RW) == 0)) {
1211 pfcode = pf_error_code(usermode, prot, 0, pte);
1212 vm_inject_pf(vm, vcpuid, pfcode, gla);
1216 /* Set the accessed bit in the page table entry */
1217 if ((pte & PG_A) == 0) {
1218 if (atomic_cmpset_64(&ptpbase[ptpindex],
1219 pte, pte | PG_A) == 0) {
1224 if (nlevels > 0 && (pte & PG_PS) != 0) {
1225 if (pgsize > 1 * GB) {
1226 pfcode = pf_error_code(usermode, prot, 1, pte);
1227 vm_inject_pf(vm, vcpuid, pfcode, gla);
1236 /* Set the dirty bit in the page table entry if necessary */
1237 if (writable && (pte & PG_M) == 0) {
1238 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1242 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1243 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1244 *gpa = pte | (gla & (pgsize - 1));
1246 ptp_release(&cookie);
1257 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1258 uint64_t rip, int inst_length, struct vie *vie)
1260 struct vm_copyinfo copyinfo[2];
1263 if (inst_length > VIE_INST_SIZE)
1264 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1266 prot = PROT_READ | PROT_EXEC;
1267 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1268 copyinfo, nitems(copyinfo));
1270 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1271 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1272 vie->num_valid = inst_length;
1278 vie_peek(struct vie *vie, uint8_t *x)
1281 if (vie->num_processed < vie->num_valid) {
1282 *x = vie->inst[vie->num_processed];
1289 vie_advance(struct vie *vie)
1292 vie->num_processed++;
1296 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
1301 if (vie_peek(vie, &x))
1305 vie->opsize_override = 1;
1307 vie->addrsize_override = 1;
1315 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
1316 * - Only one REX prefix is allowed per instruction.
1317 * - The REX prefix must immediately precede the opcode byte or the
1318 * escape opcode byte.
1319 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
1320 * the mandatory prefix must come before the REX prefix.
1322 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
1323 vie->rex_present = 1;
1324 vie->rex_w = x & 0x8 ? 1 : 0;
1325 vie->rex_r = x & 0x4 ? 1 : 0;
1326 vie->rex_x = x & 0x2 ? 1 : 0;
1327 vie->rex_b = x & 0x1 ? 1 : 0;
1332 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
1334 if (cpu_mode == CPU_MODE_64BIT) {
1336 * Default address size is 64-bits and default operand size
1339 vie->addrsize = vie->addrsize_override ? 4 : 8;
1342 else if (vie->opsize_override)
1347 /* Default address and operand sizes are 32-bits */
1348 vie->addrsize = vie->addrsize_override ? 2 : 4;
1349 vie->opsize = vie->opsize_override ? 2 : 4;
1351 /* Default address and operand sizes are 16-bits */
1352 vie->addrsize = vie->addrsize_override ? 4 : 2;
1353 vie->opsize = vie->opsize_override ? 4 : 2;
1359 decode_two_byte_opcode(struct vie *vie)
1363 if (vie_peek(vie, &x))
1366 vie->op = two_byte_opcodes[x];
1368 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1376 decode_opcode(struct vie *vie)
1380 if (vie_peek(vie, &x))
1383 vie->op = one_byte_opcodes[x];
1385 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1390 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
1391 return (decode_two_byte_opcode(vie));
1397 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
1401 if (cpu_mode == CPU_MODE_REAL)
1404 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
1407 if (vie_peek(vie, &x))
1410 vie->mod = (x >> 6) & 0x3;
1411 vie->rm = (x >> 0) & 0x7;
1412 vie->reg = (x >> 3) & 0x7;
1415 * A direct addressing mode makes no sense in the context of an EPT
1416 * fault. There has to be a memory access involved to cause the
1419 if (vie->mod == VIE_MOD_DIRECT)
1422 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
1423 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
1425 * Table 2-5: Special Cases of REX Encodings
1427 * mod=0, r/m=5 is used in the compatibility mode to
1428 * indicate a disp32 without a base register.
1430 * mod!=3, r/m=4 is used in the compatibility mode to
1431 * indicate that the SIB byte is present.
1433 * The 'b' bit in the REX prefix is don't care in
1437 vie->rm |= (vie->rex_b << 3);
1440 vie->reg |= (vie->rex_r << 3);
1443 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
1446 vie->base_register = gpr_map[vie->rm];
1449 case VIE_MOD_INDIRECT_DISP8:
1450 vie->disp_bytes = 1;
1452 case VIE_MOD_INDIRECT_DISP32:
1453 vie->disp_bytes = 4;
1455 case VIE_MOD_INDIRECT:
1456 if (vie->rm == VIE_RM_DISP32) {
1457 vie->disp_bytes = 4;
1459 * Table 2-7. RIP-Relative Addressing
1461 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
1462 * whereas in compatibility mode it just implies disp32.
1465 if (cpu_mode == CPU_MODE_64BIT)
1466 vie->base_register = VM_REG_GUEST_RIP;
1468 vie->base_register = VM_REG_LAST;
1480 decode_sib(struct vie *vie)
1484 /* Proceed only if SIB byte is present */
1485 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
1488 if (vie_peek(vie, &x))
1491 /* De-construct the SIB byte */
1492 vie->ss = (x >> 6) & 0x3;
1493 vie->index = (x >> 3) & 0x7;
1494 vie->base = (x >> 0) & 0x7;
1496 /* Apply the REX prefix modifiers */
1497 vie->index |= vie->rex_x << 3;
1498 vie->base |= vie->rex_b << 3;
1501 case VIE_MOD_INDIRECT_DISP8:
1502 vie->disp_bytes = 1;
1504 case VIE_MOD_INDIRECT_DISP32:
1505 vie->disp_bytes = 4;
1509 if (vie->mod == VIE_MOD_INDIRECT &&
1510 (vie->base == 5 || vie->base == 13)) {
1512 * Special case when base register is unused if mod = 0
1513 * and base = %rbp or %r13.
1516 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1517 * Table 2-5: Special Cases of REX Encodings
1519 vie->disp_bytes = 4;
1521 vie->base_register = gpr_map[vie->base];
1525 * All encodings of 'index' are valid except for %rsp (4).
1528 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1529 * Table 2-5: Special Cases of REX Encodings
1531 if (vie->index != 4)
1532 vie->index_register = gpr_map[vie->index];
1534 /* 'scale' makes sense only in the context of an index register */
1535 if (vie->index_register < VM_REG_LAST)
1536 vie->scale = 1 << vie->ss;
1544 decode_displacement(struct vie *vie)
1555 if ((n = vie->disp_bytes) == 0)
1558 if (n != 1 && n != 4)
1559 panic("decode_displacement: invalid disp_bytes %d", n);
1561 for (i = 0; i < n; i++) {
1562 if (vie_peek(vie, &x))
1570 vie->displacement = u.signed8; /* sign-extended */
1572 vie->displacement = u.signed32; /* sign-extended */
1578 decode_immediate(struct vie *vie)
1589 /* Figure out immediate operand size (if any) */
1590 if (vie->op.op_flags & VIE_OP_F_IMM) {
1592 * Section 2.2.1.5 "Immediates", Intel SDM:
1593 * In 64-bit mode the typical size of immediate operands
1594 * remains 32-bits. When the operand size if 64-bits, the
1595 * processor sign-extends all immediates to 64-bits prior
1598 if (vie->opsize == 4 || vie->opsize == 8)
1602 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
1606 if ((n = vie->imm_bytes) == 0)
1609 KASSERT(n == 1 || n == 2 || n == 4,
1610 ("%s: invalid number of immediate bytes: %d", __func__, n));
1612 for (i = 0; i < n; i++) {
1613 if (vie_peek(vie, &x))
1620 /* sign-extend the immediate value before use */
1622 vie->immediate = u.signed8;
1624 vie->immediate = u.signed16;
1626 vie->immediate = u.signed32;
1632 decode_moffset(struct vie *vie)
1641 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
1645 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
1646 * The memory offset size follows the address-size of the instruction.
1649 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
1652 for (i = 0; i < n; i++) {
1653 if (vie_peek(vie, &x))
1659 vie->displacement = u.u64;
1664 * Verify that all the bytes in the instruction buffer were consumed.
1667 verify_inst_length(struct vie *vie)
1670 if (vie->num_processed)
1677 * Verify that the 'guest linear address' provided as collateral of the nested
1678 * page table fault matches with our instruction decoding.
1681 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
1684 uint64_t base, idx, gla2;
1686 /* Skip 'gla' verification */
1687 if (gla == VIE_INVALID_GLA)
1691 if (vie->base_register != VM_REG_LAST) {
1692 error = vm_get_register(vm, cpuid, vie->base_register, &base);
1694 printf("verify_gla: error %d getting base reg %d\n",
1695 error, vie->base_register);
1700 * RIP-relative addressing starts from the following
1703 if (vie->base_register == VM_REG_GUEST_RIP)
1704 base += vie->num_valid;
1708 if (vie->index_register != VM_REG_LAST) {
1709 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
1711 printf("verify_gla: error %d getting index reg %d\n",
1712 error, vie->index_register);
1717 /* XXX assuming that the base address of the segment is 0 */
1718 gla2 = base + vie->scale * idx + vie->displacement;
1719 gla2 &= size2mask[vie->addrsize];
1721 printf("verify_gla mismatch: "
1722 "base(0x%0lx), scale(%d), index(0x%0lx), "
1723 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
1724 base, vie->scale, idx, vie->displacement, gla, gla2);
1732 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
1733 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
1736 if (decode_prefixes(vie, cpu_mode, cs_d))
1739 if (decode_opcode(vie))
1742 if (decode_modrm(vie, cpu_mode))
1745 if (decode_sib(vie))
1748 if (decode_displacement(vie))
1751 if (decode_immediate(vie))
1754 if (decode_moffset(vie))
1757 if (verify_inst_length(vie))
1760 if (verify_gla(vm, cpuid, gla, vie))
1763 vie->decoded = 1; /* success */
1767 #endif /* _KERNEL */