2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
47 #include <sys/_iovec.h>
49 #include <machine/vmm.h>
53 #define KASSERT(exp,msg) assert((exp))
56 #include <machine/vmm_instruction_emul.h>
58 #include <x86/specialreg.h>
60 /* struct vie_op.op_type */
75 /* struct vie_op.op_flags */
76 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
77 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
78 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
79 #define VIE_OP_F_NO_MODRM (1 << 3)
81 static const struct vie_op two_byte_opcodes[256] = {
84 .op_type = VIE_OP_TYPE_MOVZX,
88 .op_type = VIE_OP_TYPE_MOVZX,
92 .op_type = VIE_OP_TYPE_MOVSX,
96 static const struct vie_op one_byte_opcodes[256] = {
99 .op_type = VIE_OP_TYPE_TWO_BYTE
103 .op_type = VIE_OP_TYPE_SUB,
107 .op_type = VIE_OP_TYPE_CMP,
111 .op_type = VIE_OP_TYPE_MOV,
115 .op_type = VIE_OP_TYPE_MOV,
119 .op_type = VIE_OP_TYPE_MOV,
123 .op_type = VIE_OP_TYPE_MOV,
127 .op_type = VIE_OP_TYPE_MOV,
128 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
132 .op_type = VIE_OP_TYPE_MOV,
133 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
136 /* XXX Group 11 extended opcode - not just MOV */
138 .op_type = VIE_OP_TYPE_MOV,
139 .op_flags = VIE_OP_F_IMM8,
143 .op_type = VIE_OP_TYPE_MOV,
144 .op_flags = VIE_OP_F_IMM,
148 .op_type = VIE_OP_TYPE_AND,
151 /* XXX Group 1 extended opcode - not just AND */
153 .op_type = VIE_OP_TYPE_AND,
154 .op_flags = VIE_OP_F_IMM,
157 /* XXX Group 1 extended opcode - not just OR */
159 .op_type = VIE_OP_TYPE_OR,
160 .op_flags = VIE_OP_F_IMM8,
163 /* XXX Group 5 extended opcode - not just PUSH */
165 .op_type = VIE_OP_TYPE_PUSH,
170 #define VIE_MOD_INDIRECT 0
171 #define VIE_MOD_INDIRECT_DISP8 1
172 #define VIE_MOD_INDIRECT_DISP32 2
173 #define VIE_MOD_DIRECT 3
177 #define VIE_RM_DISP32 5
179 #define GB (1024 * 1024 * 1024)
181 static enum vm_reg_name gpr_map[16] = {
200 static uint64_t size2mask[] = {
204 [8] = 0xffffffffffffffff,
208 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
212 error = vm_get_register(vm, vcpuid, reg, rval);
218 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
221 *reg = gpr_map[vie->reg];
224 * 64-bit mode imposes limitations on accessing legacy high byte
227 * The legacy high-byte registers cannot be addressed if the REX
228 * prefix is present. In this case the values 4, 5, 6 and 7 of the
229 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
231 * If the REX prefix is not present then the values 4, 5, 6 and 7
232 * of the 'ModRM:reg' field address the legacy high-byte registers,
233 * %ah, %ch, %dh and %bh respectively.
235 if (!vie->rex_present) {
236 if (vie->reg & 0x4) {
238 *reg = gpr_map[vie->reg & 0x3];
244 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
248 enum vm_reg_name reg;
250 vie_calc_bytereg(vie, ®, &lhbr);
251 error = vm_get_register(vm, vcpuid, reg, &val);
254 * To obtain the value of a legacy high byte register shift the
255 * base register right by 8 bits (%ah = %rax >> 8).
265 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
267 uint64_t origval, val, mask;
269 enum vm_reg_name reg;
271 vie_calc_bytereg(vie, ®, &lhbr);
272 error = vm_get_register(vm, vcpuid, reg, &origval);
278 * Shift left by 8 to store 'byte' in a legacy high
284 val |= origval & ~mask;
285 error = vm_set_register(vm, vcpuid, reg, val);
291 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
292 uint64_t val, int size)
300 error = vie_read_register(vm, vcpuid, reg, &origval);
303 val &= size2mask[size];
304 val |= origval & ~size2mask[size];
315 error = vm_set_register(vm, vcpuid, reg, val);
319 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
322 * Return the status flags that would result from doing (x - y).
326 getcc##sz(uint##sz##_t x, uint##sz##_t y) \
330 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
331 "=r" (rflags), "+r" (x) : "m" (y)); \
341 getcc(int opsize, uint64_t x, uint64_t y)
343 KASSERT(opsize == 1 || opsize == 2 || opsize == 4 || opsize == 8,
344 ("getcc: invalid operand size %d", opsize));
347 return (getcc8(x, y));
348 else if (opsize == 2)
349 return (getcc16(x, y));
350 else if (opsize == 4)
351 return (getcc32(x, y));
353 return (getcc64(x, y));
357 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
358 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
361 enum vm_reg_name reg;
368 switch (vie->op.op_byte) {
371 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
373 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
375 size = 1; /* override for byte operation */
376 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
378 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
382 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
383 * 89/r: mov r/m16, r16
384 * 89/r: mov r/m32, r32
385 * REX.W + 89/r mov r/m64, r64
387 reg = gpr_map[vie->reg];
388 error = vie_read_register(vm, vcpuid, reg, &val);
390 val &= size2mask[size];
391 error = memwrite(vm, vcpuid, gpa, val, size, arg);
396 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
398 * REX + 8A/r: mov r8, r/m8
400 size = 1; /* override for byte operation */
401 error = memread(vm, vcpuid, gpa, &val, size, arg);
403 error = vie_write_bytereg(vm, vcpuid, vie, val);
407 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
408 * 8B/r: mov r16, r/m16
409 * 8B/r: mov r32, r/m32
410 * REX.W 8B/r: mov r64, r/m64
412 error = memread(vm, vcpuid, gpa, &val, size, arg);
414 reg = gpr_map[vie->reg];
415 error = vie_update_register(vm, vcpuid, reg, val, size);
420 * MOV from seg:moffset to AX/EAX/RAX
421 * A1: mov AX, moffs16
422 * A1: mov EAX, moffs32
423 * REX.W + A1: mov RAX, moffs64
425 error = memread(vm, vcpuid, gpa, &val, size, arg);
427 reg = VM_REG_GUEST_RAX;
428 error = vie_update_register(vm, vcpuid, reg, val, size);
433 * MOV from AX/EAX/RAX to seg:moffset
434 * A3: mov moffs16, AX
435 * A3: mov moffs32, EAX
436 * REX.W + A3: mov moffs64, RAX
438 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
440 val &= size2mask[size];
441 error = memwrite(vm, vcpuid, gpa, val, size, arg);
446 * MOV from imm8 to mem (ModRM:r/m)
447 * C6/0 mov r/m8, imm8
448 * REX + C6/0 mov r/m8, imm8
450 size = 1; /* override for byte operation */
451 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
455 * MOV from imm16/imm32 to mem (ModRM:r/m)
456 * C7/0 mov r/m16, imm16
457 * C7/0 mov r/m32, imm32
458 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
460 val = vie->immediate & size2mask[size];
461 error = memwrite(vm, vcpuid, gpa, val, size, arg);
471 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
472 mem_region_read_t memread, mem_region_write_t memwrite,
476 enum vm_reg_name reg;
482 switch (vie->op.op_byte) {
485 * MOV and zero extend byte from mem (ModRM:r/m) to
488 * 0F B6/r movzx r16, r/m8
489 * 0F B6/r movzx r32, r/m8
490 * REX.W + 0F B6/r movzx r64, r/m8
493 /* get the first operand */
494 error = memread(vm, vcpuid, gpa, &val, 1, arg);
498 /* get the second operand */
499 reg = gpr_map[vie->reg];
501 /* zero-extend byte */
504 /* write the result */
505 error = vie_update_register(vm, vcpuid, reg, val, size);
509 * MOV and zero extend word from mem (ModRM:r/m) to
512 * 0F B7/r movzx r32, r/m16
513 * REX.W + 0F B7/r movzx r64, r/m16
515 error = memread(vm, vcpuid, gpa, &val, 2, arg);
519 reg = gpr_map[vie->reg];
521 /* zero-extend word */
524 error = vie_update_register(vm, vcpuid, reg, val, size);
528 * MOV and sign extend byte from mem (ModRM:r/m) to
531 * 0F BE/r movsx r16, r/m8
532 * 0F BE/r movsx r32, r/m8
533 * REX.W + 0F BE/r movsx r64, r/m8
536 /* get the first operand */
537 error = memread(vm, vcpuid, gpa, &val, 1, arg);
541 /* get the second operand */
542 reg = gpr_map[vie->reg];
544 /* sign extend byte */
547 /* write the result */
548 error = vie_update_register(vm, vcpuid, reg, val, size);
557 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
558 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
561 enum vm_reg_name reg;
562 uint64_t result, rflags, rflags2, val1, val2;
567 switch (vie->op.op_byte) {
570 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
573 * 23/r and r16, r/m16
574 * 23/r and r32, r/m32
575 * REX.W + 23/r and r64, r/m64
578 /* get the first operand */
579 reg = gpr_map[vie->reg];
580 error = vie_read_register(vm, vcpuid, reg, &val1);
584 /* get the second operand */
585 error = memread(vm, vcpuid, gpa, &val2, size, arg);
589 /* perform the operation and write the result */
590 result = val1 & val2;
591 error = vie_update_register(vm, vcpuid, reg, result, size);
595 * AND/OR mem (ModRM:r/m) with immediate and store the
600 * 81 /i op r/m16, imm16
601 * 81 /i op r/m32, imm32
602 * REX.W + 81 /i op r/m64, imm32 sign-extended to 64
606 /* get the first operand */
607 error = memread(vm, vcpuid, gpa, &val1, size, arg);
612 * perform the operation with the pre-fetched immediate
613 * operand and write the result
615 switch (vie->reg & 7) {
617 /* modrm:reg == b100, AND */
618 result = val1 & vie->immediate;
621 /* modrm:reg == b001, OR */
622 result = val1 | vie->immediate;
631 error = memwrite(vm, vcpuid, gpa, result, size, arg);
639 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
644 * OF and CF are cleared; the SF, ZF and PF flags are set according
645 * to the result; AF is undefined.
647 * The updated status flags are obtained by subtracting 0 from 'result'.
649 rflags2 = getcc(size, result, 0);
650 rflags &= ~RFLAGS_STATUS_BITS;
651 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
653 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
658 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
659 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
662 uint64_t val1, result, rflags, rflags2;
667 switch (vie->op.op_byte) {
670 * OR mem (ModRM:r/m) with immediate and store the
673 * 83 /1 OR r/m16, imm8 sign-extended to 16
674 * 83 /1 OR r/m32, imm8 sign-extended to 32
675 * REX.W + 83/1 OR r/m64, imm8 sign-extended to 64
677 * Currently, only the OR operation of the 0x83 opcode
678 * is implemented (ModRM:reg = b001).
680 if ((vie->reg & 7) != 1)
683 /* get the first operand */
684 error = memread(vm, vcpuid, gpa, &val1, size, arg);
689 * perform the operation with the pre-fetched immediate
690 * operand and write the result
692 result = val1 | vie->immediate;
693 error = memwrite(vm, vcpuid, gpa, result, size, arg);
701 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
706 * OF and CF are cleared; the SF, ZF and PF flags are set according
707 * to the result; AF is undefined.
709 * The updated status flags are obtained by subtracting 0 from 'result'.
711 rflags2 = getcc(size, result, 0);
712 rflags &= ~RFLAGS_STATUS_BITS;
713 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
715 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
720 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
721 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
724 uint64_t op1, op2, rflags, rflags2;
725 enum vm_reg_name reg;
728 switch (vie->op.op_byte) {
731 * 3B/r CMP r16, r/m16
732 * 3B/r CMP r32, r/m32
733 * REX.W + 3B/r CMP r64, r/m64
735 * Compare first operand (reg) with second operand (r/m) and
736 * set status flags in EFLAGS register. The comparison is
737 * performed by subtracting the second operand from the first
738 * operand and then setting the status flags.
741 /* Get the first operand */
742 reg = gpr_map[vie->reg];
743 error = vie_read_register(vm, vcpuid, reg, &op1);
747 /* Get the second operand */
748 error = memread(vm, vcpuid, gpa, &op2, size, arg);
756 rflags2 = getcc(size, op1, op2);
757 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
760 rflags &= ~RFLAGS_STATUS_BITS;
761 rflags |= rflags2 & RFLAGS_STATUS_BITS;
763 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
768 emulate_sub(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
769 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
772 uint64_t nval, rflags, rflags2, val1, val2;
773 enum vm_reg_name reg;
778 switch (vie->op.op_byte) {
781 * SUB r/m from r and store the result in r
783 * 2B/r SUB r16, r/m16
784 * 2B/r SUB r32, r/m32
785 * REX.W + 2B/r SUB r64, r/m64
788 /* get the first operand */
789 reg = gpr_map[vie->reg];
790 error = vie_read_register(vm, vcpuid, reg, &val1);
794 /* get the second operand */
795 error = memread(vm, vcpuid, gpa, &val2, size, arg);
799 /* perform the operation and write the result */
801 error = vie_update_register(vm, vcpuid, reg, nval, size);
808 rflags2 = getcc(size, val1, val2);
809 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
814 rflags &= ~RFLAGS_STATUS_BITS;
815 rflags |= rflags2 & RFLAGS_STATUS_BITS;
816 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
824 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
825 struct vm_guest_paging *paging, mem_region_read_t memread,
826 mem_region_write_t memwrite, void *arg)
829 struct vm_copyinfo copyinfo[2];
831 struct iovec copyinfo[2];
833 struct seg_desc ss_desc;
834 uint64_t cr0, rflags, rsp, stack_gla, val;
835 int error, size, stackaddrsize;
838 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
840 * PUSH is part of the group 5 extended opcodes and is identified
841 * by ModRM:reg = b110.
843 if ((vie->reg & 7) != 6)
848 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
850 if (paging->cpu_mode == CPU_MODE_REAL) {
852 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
854 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
855 * - Stack pointer size is always 64-bits.
856 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
857 * - 16-bit PUSH/POP is supported by using the operand size
858 * override prefix (66H).
861 size = vie->opsize_override ? 2 : 8;
864 * In protected or compability mode the 'B' flag in the
865 * stack-segment descriptor determines the size of the
868 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
869 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
871 if (SEG_DESC_DEF32(ss_desc.access))
877 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
878 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
880 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
881 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
883 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
884 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
887 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
888 rsp, size, stackaddrsize, PROT_WRITE, &stack_gla)) {
889 vm_inject_ss(vm, vcpuid, 0);
893 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
894 vm_inject_ss(vm, vcpuid, 0);
898 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
899 vm_inject_ac(vm, vcpuid, 0);
903 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size, PROT_WRITE,
904 copyinfo, nitems(copyinfo));
907 * XXX cannot return a negative error value here because it
908 * ends up being the return value of the VM_RUN() ioctl and
909 * is interpreted as a pseudo-error (for e.g. ERESTART).
912 } else if (error == 1) {
913 /* Resume guest execution to handle page fault */
917 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
919 vm_copyout(vm, vcpuid, &val, copyinfo, size);
920 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
922 KASSERT(error == 0, ("error %d updating rsp", error));
925 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
931 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
932 struct vm_guest_paging *paging, mem_region_read_t memread,
933 mem_region_write_t memwrite, void *memarg)
940 switch (vie->op.op_type) {
941 case VIE_OP_TYPE_PUSH:
942 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
945 case VIE_OP_TYPE_CMP:
946 error = emulate_cmp(vm, vcpuid, gpa, vie,
947 memread, memwrite, memarg);
949 case VIE_OP_TYPE_MOV:
950 error = emulate_mov(vm, vcpuid, gpa, vie,
951 memread, memwrite, memarg);
953 case VIE_OP_TYPE_MOVSX:
954 case VIE_OP_TYPE_MOVZX:
955 error = emulate_movx(vm, vcpuid, gpa, vie,
956 memread, memwrite, memarg);
958 case VIE_OP_TYPE_AND:
959 error = emulate_and(vm, vcpuid, gpa, vie,
960 memread, memwrite, memarg);
963 error = emulate_or(vm, vcpuid, gpa, vie,
964 memread, memwrite, memarg);
966 case VIE_OP_TYPE_SUB:
967 error = emulate_sub(vm, vcpuid, gpa, vie,
968 memread, memwrite, memarg);
979 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
981 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
982 ("%s: invalid size %d", __func__, size));
983 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
985 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
988 return ((gla & (size - 1)) ? 1 : 0);
992 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
996 if (cpu_mode != CPU_MODE_64BIT)
1000 * The value of the bit 47 in the 'gla' should be replicated in the
1001 * most significant 16 bits.
1003 mask = ~((1UL << 48) - 1);
1004 if (gla & (1UL << 47))
1005 return ((gla & mask) != mask);
1007 return ((gla & mask) != 0);
1011 vie_size2mask(int size)
1013 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1014 ("vie_size2mask: invalid size %d", size));
1015 return (size2mask[size]);
1019 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
1020 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
1021 int prot, uint64_t *gla)
1023 uint64_t firstoff, low_limit, high_limit, segbase;
1026 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
1027 ("%s: invalid segment %d", __func__, seg));
1028 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
1029 ("%s: invalid operand size %d", __func__, length));
1030 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
1031 ("%s: invalid prot %#x", __func__, prot));
1034 if (cpu_mode == CPU_MODE_64BIT) {
1035 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
1036 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
1039 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
1040 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
1043 * If the segment selector is loaded with a NULL selector
1044 * then the descriptor is unusable and attempting to use
1045 * it results in a #GP(0).
1047 if (SEG_DESC_UNUSABLE(desc->access))
1051 * The processor generates a #NP exception when a segment
1052 * register is loaded with a selector that points to a
1053 * descriptor that is not present. If this was the case then
1054 * it would have been checked before the VM-exit.
1056 KASSERT(SEG_DESC_PRESENT(desc->access),
1057 ("segment %d not present: %#x", seg, desc->access));
1060 * The descriptor type must indicate a code/data segment.
1062 type = SEG_DESC_TYPE(desc->access);
1063 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
1064 "descriptor type %#x", seg, type));
1066 if (prot & PROT_READ) {
1067 /* #GP on a read access to a exec-only code segment */
1068 if ((type & 0xA) == 0x8)
1072 if (prot & PROT_WRITE) {
1074 * #GP on a write access to a code segment or a
1075 * read-only data segment.
1077 if (type & 0x8) /* code segment */
1080 if ((type & 0xA) == 0) /* read-only data seg */
1085 * 'desc->limit' is fully expanded taking granularity into
1088 if ((type & 0xC) == 0x4) {
1089 /* expand-down data segment */
1090 low_limit = desc->limit + 1;
1091 high_limit = SEG_DESC_DEF32(desc->access) ?
1092 0xffffffff : 0xffff;
1094 /* code segment or expand-up data segment */
1096 high_limit = desc->limit;
1099 while (length > 0) {
1100 offset &= vie_size2mask(addrsize);
1101 if (offset < low_limit || offset > high_limit)
1109 * In 64-bit mode all segments except %fs and %gs have a segment
1110 * base address of 0.
1112 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1113 seg != VM_REG_GUEST_GS) {
1116 segbase = desc->base;
1120 * Truncate 'firstoff' to the effective address size before adding
1121 * it to the segment base.
1123 firstoff &= vie_size2mask(addrsize);
1124 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1130 vie_init(struct vie *vie, const char *inst_bytes, int inst_length)
1132 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE,
1133 ("%s: invalid instruction length (%d)", __func__, inst_length));
1135 bzero(vie, sizeof(struct vie));
1137 vie->base_register = VM_REG_LAST;
1138 vie->index_register = VM_REG_LAST;
1141 bcopy(inst_bytes, vie->inst, inst_length);
1142 vie->num_valid = inst_length;
1147 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1152 error_code |= PGEX_P;
1153 if (prot & VM_PROT_WRITE)
1154 error_code |= PGEX_W;
1156 error_code |= PGEX_U;
1158 error_code |= PGEX_RSV;
1159 if (prot & VM_PROT_EXECUTE)
1160 error_code |= PGEX_I;
1162 return (error_code);
1166 ptp_release(void **cookie)
1168 if (*cookie != NULL) {
1169 vm_gpa_release(*cookie);
1175 ptp_hold(struct vm *vm, vm_paddr_t ptpphys, size_t len, void **cookie)
1179 ptp_release(cookie);
1180 ptr = vm_gpa_hold(vm, ptpphys, len, VM_PROT_RW, cookie);
1185 vmm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1186 uint64_t gla, int prot, uint64_t *gpa)
1188 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1190 uint64_t *ptpbase, ptpphys, pte, pgsize;
1191 uint32_t *ptpbase32, pte32;
1194 usermode = (paging->cpl == 3 ? 1 : 0);
1195 writable = prot & VM_PROT_WRITE;
1200 ptpphys = paging->cr3; /* root of the page tables */
1201 ptp_release(&cookie);
1205 if (vie_canonical_check(paging->cpu_mode, gla)) {
1207 * XXX assuming a non-stack reference otherwise a stack fault
1208 * should be generated.
1210 vm_inject_gp(vm, vcpuid);
1214 if (paging->paging_mode == PAGING_MODE_FLAT) {
1219 if (paging->paging_mode == PAGING_MODE_32) {
1221 while (--nlevels >= 0) {
1222 /* Zero out the lower 12 bits. */
1225 ptpbase32 = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1227 if (ptpbase32 == NULL)
1230 ptpshift = PAGE_SHIFT + nlevels * 10;
1231 ptpindex = (gla >> ptpshift) & 0x3FF;
1232 pgsize = 1UL << ptpshift;
1234 pte32 = ptpbase32[ptpindex];
1236 if ((pte32 & PG_V) == 0 ||
1237 (usermode && (pte32 & PG_U) == 0) ||
1238 (writable && (pte32 & PG_RW) == 0)) {
1239 pfcode = pf_error_code(usermode, prot, 0,
1241 vm_inject_pf(vm, vcpuid, pfcode, gla);
1246 * Emulate the x86 MMU's management of the accessed
1247 * and dirty flags. While the accessed flag is set
1248 * at every level of the page table, the dirty flag
1249 * is only set at the last level providing the guest
1252 if ((pte32 & PG_A) == 0) {
1253 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1254 pte32, pte32 | PG_A) == 0) {
1259 /* XXX must be ignored if CR4.PSE=0 */
1260 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1266 /* Set the dirty bit in the page table entry if necessary */
1267 if (writable && (pte32 & PG_M) == 0) {
1268 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1269 pte32, pte32 | PG_M) == 0) {
1274 /* Zero out the lower 'ptpshift' bits */
1275 pte32 >>= ptpshift; pte32 <<= ptpshift;
1276 *gpa = pte32 | (gla & (pgsize - 1));
1280 if (paging->paging_mode == PAGING_MODE_PAE) {
1281 /* Zero out the lower 5 bits and the upper 32 bits */
1282 ptpphys &= 0xffffffe0UL;
1284 ptpbase = ptp_hold(vm, ptpphys, sizeof(*ptpbase) * 4, &cookie);
1285 if (ptpbase == NULL)
1288 ptpindex = (gla >> 30) & 0x3;
1290 pte = ptpbase[ptpindex];
1292 if ((pte & PG_V) == 0) {
1293 pfcode = pf_error_code(usermode, prot, 0, pte);
1294 vm_inject_pf(vm, vcpuid, pfcode, gla);
1303 while (--nlevels >= 0) {
1304 /* Zero out the lower 12 bits and the upper 12 bits */
1305 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1307 ptpbase = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1308 if (ptpbase == NULL)
1311 ptpshift = PAGE_SHIFT + nlevels * 9;
1312 ptpindex = (gla >> ptpshift) & 0x1FF;
1313 pgsize = 1UL << ptpshift;
1315 pte = ptpbase[ptpindex];
1317 if ((pte & PG_V) == 0 ||
1318 (usermode && (pte & PG_U) == 0) ||
1319 (writable && (pte & PG_RW) == 0)) {
1320 pfcode = pf_error_code(usermode, prot, 0, pte);
1321 vm_inject_pf(vm, vcpuid, pfcode, gla);
1325 /* Set the accessed bit in the page table entry */
1326 if ((pte & PG_A) == 0) {
1327 if (atomic_cmpset_64(&ptpbase[ptpindex],
1328 pte, pte | PG_A) == 0) {
1333 if (nlevels > 0 && (pte & PG_PS) != 0) {
1334 if (pgsize > 1 * GB) {
1335 pfcode = pf_error_code(usermode, prot, 1, pte);
1336 vm_inject_pf(vm, vcpuid, pfcode, gla);
1345 /* Set the dirty bit in the page table entry if necessary */
1346 if (writable && (pte & PG_M) == 0) {
1347 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1351 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1352 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1353 *gpa = pte | (gla & (pgsize - 1));
1355 ptp_release(&cookie);
1366 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1367 uint64_t rip, int inst_length, struct vie *vie)
1369 struct vm_copyinfo copyinfo[2];
1372 if (inst_length > VIE_INST_SIZE)
1373 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1375 prot = PROT_READ | PROT_EXEC;
1376 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1377 copyinfo, nitems(copyinfo));
1379 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1380 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1381 vie->num_valid = inst_length;
1387 vie_peek(struct vie *vie, uint8_t *x)
1390 if (vie->num_processed < vie->num_valid) {
1391 *x = vie->inst[vie->num_processed];
1398 vie_advance(struct vie *vie)
1401 vie->num_processed++;
1405 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
1410 if (vie_peek(vie, &x))
1414 vie->opsize_override = 1;
1416 vie->addrsize_override = 1;
1424 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
1425 * - Only one REX prefix is allowed per instruction.
1426 * - The REX prefix must immediately precede the opcode byte or the
1427 * escape opcode byte.
1428 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
1429 * the mandatory prefix must come before the REX prefix.
1431 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
1432 vie->rex_present = 1;
1433 vie->rex_w = x & 0x8 ? 1 : 0;
1434 vie->rex_r = x & 0x4 ? 1 : 0;
1435 vie->rex_x = x & 0x2 ? 1 : 0;
1436 vie->rex_b = x & 0x1 ? 1 : 0;
1441 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
1443 if (cpu_mode == CPU_MODE_64BIT) {
1445 * Default address size is 64-bits and default operand size
1448 vie->addrsize = vie->addrsize_override ? 4 : 8;
1451 else if (vie->opsize_override)
1456 /* Default address and operand sizes are 32-bits */
1457 vie->addrsize = vie->addrsize_override ? 2 : 4;
1458 vie->opsize = vie->opsize_override ? 2 : 4;
1460 /* Default address and operand sizes are 16-bits */
1461 vie->addrsize = vie->addrsize_override ? 4 : 2;
1462 vie->opsize = vie->opsize_override ? 4 : 2;
1468 decode_two_byte_opcode(struct vie *vie)
1472 if (vie_peek(vie, &x))
1475 vie->op = two_byte_opcodes[x];
1477 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1485 decode_opcode(struct vie *vie)
1489 if (vie_peek(vie, &x))
1492 vie->op = one_byte_opcodes[x];
1494 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1499 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
1500 return (decode_two_byte_opcode(vie));
1506 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
1510 if (cpu_mode == CPU_MODE_REAL)
1513 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
1516 if (vie_peek(vie, &x))
1519 vie->mod = (x >> 6) & 0x3;
1520 vie->rm = (x >> 0) & 0x7;
1521 vie->reg = (x >> 3) & 0x7;
1524 * A direct addressing mode makes no sense in the context of an EPT
1525 * fault. There has to be a memory access involved to cause the
1528 if (vie->mod == VIE_MOD_DIRECT)
1531 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
1532 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
1534 * Table 2-5: Special Cases of REX Encodings
1536 * mod=0, r/m=5 is used in the compatibility mode to
1537 * indicate a disp32 without a base register.
1539 * mod!=3, r/m=4 is used in the compatibility mode to
1540 * indicate that the SIB byte is present.
1542 * The 'b' bit in the REX prefix is don't care in
1546 vie->rm |= (vie->rex_b << 3);
1549 vie->reg |= (vie->rex_r << 3);
1552 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
1555 vie->base_register = gpr_map[vie->rm];
1558 case VIE_MOD_INDIRECT_DISP8:
1559 vie->disp_bytes = 1;
1561 case VIE_MOD_INDIRECT_DISP32:
1562 vie->disp_bytes = 4;
1564 case VIE_MOD_INDIRECT:
1565 if (vie->rm == VIE_RM_DISP32) {
1566 vie->disp_bytes = 4;
1568 * Table 2-7. RIP-Relative Addressing
1570 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
1571 * whereas in compatibility mode it just implies disp32.
1574 if (cpu_mode == CPU_MODE_64BIT)
1575 vie->base_register = VM_REG_GUEST_RIP;
1577 vie->base_register = VM_REG_LAST;
1589 decode_sib(struct vie *vie)
1593 /* Proceed only if SIB byte is present */
1594 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
1597 if (vie_peek(vie, &x))
1600 /* De-construct the SIB byte */
1601 vie->ss = (x >> 6) & 0x3;
1602 vie->index = (x >> 3) & 0x7;
1603 vie->base = (x >> 0) & 0x7;
1605 /* Apply the REX prefix modifiers */
1606 vie->index |= vie->rex_x << 3;
1607 vie->base |= vie->rex_b << 3;
1610 case VIE_MOD_INDIRECT_DISP8:
1611 vie->disp_bytes = 1;
1613 case VIE_MOD_INDIRECT_DISP32:
1614 vie->disp_bytes = 4;
1618 if (vie->mod == VIE_MOD_INDIRECT &&
1619 (vie->base == 5 || vie->base == 13)) {
1621 * Special case when base register is unused if mod = 0
1622 * and base = %rbp or %r13.
1625 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1626 * Table 2-5: Special Cases of REX Encodings
1628 vie->disp_bytes = 4;
1630 vie->base_register = gpr_map[vie->base];
1634 * All encodings of 'index' are valid except for %rsp (4).
1637 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1638 * Table 2-5: Special Cases of REX Encodings
1640 if (vie->index != 4)
1641 vie->index_register = gpr_map[vie->index];
1643 /* 'scale' makes sense only in the context of an index register */
1644 if (vie->index_register < VM_REG_LAST)
1645 vie->scale = 1 << vie->ss;
1653 decode_displacement(struct vie *vie)
1664 if ((n = vie->disp_bytes) == 0)
1667 if (n != 1 && n != 4)
1668 panic("decode_displacement: invalid disp_bytes %d", n);
1670 for (i = 0; i < n; i++) {
1671 if (vie_peek(vie, &x))
1679 vie->displacement = u.signed8; /* sign-extended */
1681 vie->displacement = u.signed32; /* sign-extended */
1687 decode_immediate(struct vie *vie)
1698 /* Figure out immediate operand size (if any) */
1699 if (vie->op.op_flags & VIE_OP_F_IMM) {
1701 * Section 2.2.1.5 "Immediates", Intel SDM:
1702 * In 64-bit mode the typical size of immediate operands
1703 * remains 32-bits. When the operand size if 64-bits, the
1704 * processor sign-extends all immediates to 64-bits prior
1707 if (vie->opsize == 4 || vie->opsize == 8)
1711 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
1715 if ((n = vie->imm_bytes) == 0)
1718 KASSERT(n == 1 || n == 2 || n == 4,
1719 ("%s: invalid number of immediate bytes: %d", __func__, n));
1721 for (i = 0; i < n; i++) {
1722 if (vie_peek(vie, &x))
1729 /* sign-extend the immediate value before use */
1731 vie->immediate = u.signed8;
1733 vie->immediate = u.signed16;
1735 vie->immediate = u.signed32;
1741 decode_moffset(struct vie *vie)
1750 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
1754 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
1755 * The memory offset size follows the address-size of the instruction.
1758 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
1761 for (i = 0; i < n; i++) {
1762 if (vie_peek(vie, &x))
1768 vie->displacement = u.u64;
1773 * Verify that all the bytes in the instruction buffer were consumed.
1776 verify_inst_length(struct vie *vie)
1779 if (vie->num_processed)
1786 * Verify that the 'guest linear address' provided as collateral of the nested
1787 * page table fault matches with our instruction decoding.
1790 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
1793 uint64_t base, idx, gla2;
1795 /* Skip 'gla' verification */
1796 if (gla == VIE_INVALID_GLA)
1800 if (vie->base_register != VM_REG_LAST) {
1801 error = vm_get_register(vm, cpuid, vie->base_register, &base);
1803 printf("verify_gla: error %d getting base reg %d\n",
1804 error, vie->base_register);
1809 * RIP-relative addressing starts from the following
1812 if (vie->base_register == VM_REG_GUEST_RIP)
1813 base += vie->num_valid;
1817 if (vie->index_register != VM_REG_LAST) {
1818 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
1820 printf("verify_gla: error %d getting index reg %d\n",
1821 error, vie->index_register);
1826 /* XXX assuming that the base address of the segment is 0 */
1827 gla2 = base + vie->scale * idx + vie->displacement;
1828 gla2 &= size2mask[vie->addrsize];
1830 printf("verify_gla mismatch: "
1831 "base(0x%0lx), scale(%d), index(0x%0lx), "
1832 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
1833 base, vie->scale, idx, vie->displacement, gla, gla2);
1841 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
1842 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
1845 if (decode_prefixes(vie, cpu_mode, cs_d))
1848 if (decode_opcode(vie))
1851 if (decode_modrm(vie, cpu_mode))
1854 if (decode_sib(vie))
1857 if (decode_displacement(vie))
1860 if (decode_immediate(vie))
1863 if (decode_moffset(vie))
1866 if (verify_inst_length(vie))
1869 if (verify_gla(vm, cpuid, gla, vie))
1872 vie->decoded = 1; /* success */
1876 #endif /* _KERNEL */