2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Sandvine, Inc.
5 * Copyright (c) 2012 NetApp, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
38 #include <sys/systm.h>
44 #include <machine/vmparam.h>
45 #include <machine/vmm.h>
47 #include <sys/types.h>
48 #include <sys/errno.h>
49 #include <sys/_iovec.h>
51 #include <machine/vmm.h>
55 #define KASSERT(exp,msg) assert((exp))
58 #include <machine/vmm_instruction_emul.h>
60 #include <x86/specialreg.h>
62 /* struct vie_op.op_type */
82 /* struct vie_op.op_flags */
83 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
84 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
85 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
86 #define VIE_OP_F_NO_MODRM (1 << 3)
87 #define VIE_OP_F_NO_GLA_VERIFICATION (1 << 4)
89 static const struct vie_op two_byte_opcodes[256] = {
92 .op_type = VIE_OP_TYPE_MOVZX,
96 .op_type = VIE_OP_TYPE_MOVZX,
100 .op_type = VIE_OP_TYPE_BITTEST,
101 .op_flags = VIE_OP_F_IMM8,
105 .op_type = VIE_OP_TYPE_MOVSX,
109 static const struct vie_op one_byte_opcodes[256] = {
112 .op_type = VIE_OP_TYPE_TWO_BYTE
116 .op_type = VIE_OP_TYPE_OR,
120 .op_type = VIE_OP_TYPE_SUB,
124 .op_type = VIE_OP_TYPE_CMP,
128 .op_type = VIE_OP_TYPE_CMP,
132 .op_type = VIE_OP_TYPE_MOV,
136 .op_type = VIE_OP_TYPE_MOV,
140 .op_type = VIE_OP_TYPE_MOV,
144 .op_type = VIE_OP_TYPE_MOV,
148 .op_type = VIE_OP_TYPE_MOV,
149 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
153 .op_type = VIE_OP_TYPE_MOV,
154 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
158 .op_type = VIE_OP_TYPE_MOVS,
159 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
163 .op_type = VIE_OP_TYPE_MOVS,
164 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
168 .op_type = VIE_OP_TYPE_STOS,
169 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
173 .op_type = VIE_OP_TYPE_STOS,
174 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
177 /* XXX Group 11 extended opcode - not just MOV */
179 .op_type = VIE_OP_TYPE_MOV,
180 .op_flags = VIE_OP_F_IMM8,
184 .op_type = VIE_OP_TYPE_MOV,
185 .op_flags = VIE_OP_F_IMM,
189 .op_type = VIE_OP_TYPE_AND,
192 /* Group 1 extended opcode */
194 .op_type = VIE_OP_TYPE_GROUP1,
195 .op_flags = VIE_OP_F_IMM8,
198 /* Group 1 extended opcode */
200 .op_type = VIE_OP_TYPE_GROUP1,
201 .op_flags = VIE_OP_F_IMM,
204 /* Group 1 extended opcode */
206 .op_type = VIE_OP_TYPE_GROUP1,
207 .op_flags = VIE_OP_F_IMM8,
210 /* XXX Group 1A extended opcode - not just POP */
212 .op_type = VIE_OP_TYPE_POP,
215 /* XXX Group 5 extended opcode - not just PUSH */
217 .op_type = VIE_OP_TYPE_PUSH,
222 #define VIE_MOD_INDIRECT 0
223 #define VIE_MOD_INDIRECT_DISP8 1
224 #define VIE_MOD_INDIRECT_DISP32 2
225 #define VIE_MOD_DIRECT 3
229 #define VIE_RM_DISP32 5
231 #define GB (1024 * 1024 * 1024)
233 static enum vm_reg_name gpr_map[16] = {
252 static uint64_t size2mask[] = {
256 [8] = 0xffffffffffffffff,
260 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
264 error = vm_get_register(vm, vcpuid, reg, rval);
270 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
273 *reg = gpr_map[vie->reg];
276 * 64-bit mode imposes limitations on accessing legacy high byte
279 * The legacy high-byte registers cannot be addressed if the REX
280 * prefix is present. In this case the values 4, 5, 6 and 7 of the
281 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
283 * If the REX prefix is not present then the values 4, 5, 6 and 7
284 * of the 'ModRM:reg' field address the legacy high-byte registers,
285 * %ah, %ch, %dh and %bh respectively.
287 if (!vie->rex_present) {
288 if (vie->reg & 0x4) {
290 *reg = gpr_map[vie->reg & 0x3];
296 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
300 enum vm_reg_name reg;
302 vie_calc_bytereg(vie, ®, &lhbr);
303 error = vm_get_register(vm, vcpuid, reg, &val);
306 * To obtain the value of a legacy high byte register shift the
307 * base register right by 8 bits (%ah = %rax >> 8).
317 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
319 uint64_t origval, val, mask;
321 enum vm_reg_name reg;
323 vie_calc_bytereg(vie, ®, &lhbr);
324 error = vm_get_register(vm, vcpuid, reg, &origval);
330 * Shift left by 8 to store 'byte' in a legacy high
336 val |= origval & ~mask;
337 error = vm_set_register(vm, vcpuid, reg, val);
343 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
344 uint64_t val, int size)
352 error = vie_read_register(vm, vcpuid, reg, &origval);
355 val &= size2mask[size];
356 val |= origval & ~size2mask[size];
367 error = vm_set_register(vm, vcpuid, reg, val);
371 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
374 * Return the status flags that would result from doing (x - y).
378 getcc##sz(uint##sz##_t x, uint##sz##_t y) \
382 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
383 "=r" (rflags), "+r" (x) : "m" (y)); \
393 getcc(int opsize, uint64_t x, uint64_t y)
395 KASSERT(opsize == 1 || opsize == 2 || opsize == 4 || opsize == 8,
396 ("getcc: invalid operand size %d", opsize));
399 return (getcc8(x, y));
400 else if (opsize == 2)
401 return (getcc16(x, y));
402 else if (opsize == 4)
403 return (getcc32(x, y));
405 return (getcc64(x, y));
409 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
410 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
413 enum vm_reg_name reg;
420 switch (vie->op.op_byte) {
423 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
425 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
427 size = 1; /* override for byte operation */
428 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
430 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
434 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
435 * 89/r: mov r/m16, r16
436 * 89/r: mov r/m32, r32
437 * REX.W + 89/r mov r/m64, r64
439 reg = gpr_map[vie->reg];
440 error = vie_read_register(vm, vcpuid, reg, &val);
442 val &= size2mask[size];
443 error = memwrite(vm, vcpuid, gpa, val, size, arg);
448 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
450 * REX + 8A/r: mov r8, r/m8
452 size = 1; /* override for byte operation */
453 error = memread(vm, vcpuid, gpa, &val, size, arg);
455 error = vie_write_bytereg(vm, vcpuid, vie, val);
459 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
460 * 8B/r: mov r16, r/m16
461 * 8B/r: mov r32, r/m32
462 * REX.W 8B/r: mov r64, r/m64
464 error = memread(vm, vcpuid, gpa, &val, size, arg);
466 reg = gpr_map[vie->reg];
467 error = vie_update_register(vm, vcpuid, reg, val, size);
472 * MOV from seg:moffset to AX/EAX/RAX
473 * A1: mov AX, moffs16
474 * A1: mov EAX, moffs32
475 * REX.W + A1: mov RAX, moffs64
477 error = memread(vm, vcpuid, gpa, &val, size, arg);
479 reg = VM_REG_GUEST_RAX;
480 error = vie_update_register(vm, vcpuid, reg, val, size);
485 * MOV from AX/EAX/RAX to seg:moffset
486 * A3: mov moffs16, AX
487 * A3: mov moffs32, EAX
488 * REX.W + A3: mov moffs64, RAX
490 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
492 val &= size2mask[size];
493 error = memwrite(vm, vcpuid, gpa, val, size, arg);
498 * MOV from imm8 to mem (ModRM:r/m)
499 * C6/0 mov r/m8, imm8
500 * REX + C6/0 mov r/m8, imm8
502 size = 1; /* override for byte operation */
503 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
507 * MOV from imm16/imm32 to mem (ModRM:r/m)
508 * C7/0 mov r/m16, imm16
509 * C7/0 mov r/m32, imm32
510 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
512 val = vie->immediate & size2mask[size];
513 error = memwrite(vm, vcpuid, gpa, val, size, arg);
523 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
524 mem_region_read_t memread, mem_region_write_t memwrite,
528 enum vm_reg_name reg;
534 switch (vie->op.op_byte) {
537 * MOV and zero extend byte from mem (ModRM:r/m) to
540 * 0F B6/r movzx r16, r/m8
541 * 0F B6/r movzx r32, r/m8
542 * REX.W + 0F B6/r movzx r64, r/m8
545 /* get the first operand */
546 error = memread(vm, vcpuid, gpa, &val, 1, arg);
550 /* get the second operand */
551 reg = gpr_map[vie->reg];
553 /* zero-extend byte */
556 /* write the result */
557 error = vie_update_register(vm, vcpuid, reg, val, size);
561 * MOV and zero extend word from mem (ModRM:r/m) to
564 * 0F B7/r movzx r32, r/m16
565 * REX.W + 0F B7/r movzx r64, r/m16
567 error = memread(vm, vcpuid, gpa, &val, 2, arg);
571 reg = gpr_map[vie->reg];
573 /* zero-extend word */
576 error = vie_update_register(vm, vcpuid, reg, val, size);
580 * MOV and sign extend byte from mem (ModRM:r/m) to
583 * 0F BE/r movsx r16, r/m8
584 * 0F BE/r movsx r32, r/m8
585 * REX.W + 0F BE/r movsx r64, r/m8
588 /* get the first operand */
589 error = memread(vm, vcpuid, gpa, &val, 1, arg);
593 /* get the second operand */
594 reg = gpr_map[vie->reg];
596 /* sign extend byte */
599 /* write the result */
600 error = vie_update_register(vm, vcpuid, reg, val, size);
609 * Helper function to calculate and validate a linear address.
612 get_gla(void *vm, int vcpuid, struct vie *vie, struct vm_guest_paging *paging,
613 int opsize, int addrsize, int prot, enum vm_reg_name seg,
614 enum vm_reg_name gpr, uint64_t *gla, int *fault)
616 struct seg_desc desc;
617 uint64_t cr0, val, rflags;
620 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
621 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
623 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
624 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
626 error = vm_get_seg_desc(vm, vcpuid, seg, &desc);
627 KASSERT(error == 0, ("%s: error %d getting segment descriptor %d",
628 __func__, error, seg));
630 error = vie_read_register(vm, vcpuid, gpr, &val);
631 KASSERT(error == 0, ("%s: error %d getting register %d", __func__,
634 if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize,
635 addrsize, prot, gla)) {
636 if (seg == VM_REG_GUEST_SS)
637 vm_inject_ss(vm, vcpuid, 0);
639 vm_inject_gp(vm, vcpuid);
643 if (vie_canonical_check(paging->cpu_mode, *gla)) {
644 if (seg == VM_REG_GUEST_SS)
645 vm_inject_ss(vm, vcpuid, 0);
647 vm_inject_gp(vm, vcpuid);
651 if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) {
652 vm_inject_ac(vm, vcpuid, 0);
665 emulate_movs(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
666 struct vm_guest_paging *paging, mem_region_read_t memread,
667 mem_region_write_t memwrite, void *arg)
670 struct vm_copyinfo copyinfo[2];
672 struct iovec copyinfo[2];
674 uint64_t dstaddr, srcaddr, dstgpa, srcgpa, val;
675 uint64_t rcx, rdi, rsi, rflags;
676 int error, fault, opsize, seg, repeat;
678 opsize = (vie->op.op_byte == 0xA4) ? 1 : vie->opsize;
683 * XXX although the MOVS instruction is only supposed to be used with
684 * the "rep" prefix some guests like FreeBSD will use "repnz" instead.
686 * Empirically the "repnz" prefix has identical behavior to "rep"
687 * and the zero flag does not make a difference.
689 repeat = vie->repz_present | vie->repnz_present;
692 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
693 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
696 * The count register is %rcx, %ecx or %cx depending on the
697 * address size of the instruction.
699 if ((rcx & vie_size2mask(vie->addrsize)) == 0) {
706 * Source Destination Comments
707 * --------------------------------------------
708 * (1) memory memory n/a
709 * (2) memory mmio emulated
710 * (3) mmio memory emulated
711 * (4) mmio mmio emulated
713 * At this point we don't have sufficient information to distinguish
714 * between (2), (3) and (4). We use 'vm_copy_setup()' to tease this
715 * out because it will succeed only when operating on regular memory.
717 * XXX the emulation doesn't properly handle the case where 'gpa'
718 * is straddling the boundary between the normal memory and MMIO.
721 seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS;
722 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
723 PROT_READ, seg, VM_REG_GUEST_RSI, &srcaddr, &fault);
727 error = vm_copy_setup(vm, vcpuid, paging, srcaddr, opsize, PROT_READ,
728 copyinfo, nitems(copyinfo), &fault);
731 goto done; /* Resume guest to handle fault */
734 * case (2): read from system memory and write to mmio.
736 vm_copyin(vm, vcpuid, copyinfo, &val, opsize);
737 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
738 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
743 * 'vm_copy_setup()' is expected to fail for cases (3) and (4)
744 * if 'srcaddr' is in the mmio space.
747 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
748 PROT_WRITE, VM_REG_GUEST_ES, VM_REG_GUEST_RDI, &dstaddr,
753 error = vm_copy_setup(vm, vcpuid, paging, dstaddr, opsize,
754 PROT_WRITE, copyinfo, nitems(copyinfo), &fault);
757 goto done; /* Resume guest to handle fault */
760 * case (3): read from MMIO and write to system memory.
762 * A MMIO read can have side-effects so we
763 * commit to it only after vm_copy_setup() is
764 * successful. If a page-fault needs to be
765 * injected into the guest then it will happen
766 * before the MMIO read is attempted.
768 error = memread(vm, vcpuid, gpa, &val, opsize, arg);
772 vm_copyout(vm, vcpuid, &val, copyinfo, opsize);
773 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
776 * Case (4): read from and write to mmio.
778 * Commit to the MMIO read/write (with potential
779 * side-effects) only after we are sure that the
780 * instruction is not going to be restarted due
781 * to address translation faults.
783 error = vm_gla2gpa(vm, vcpuid, paging, srcaddr,
784 PROT_READ, &srcgpa, &fault);
788 error = vm_gla2gpa(vm, vcpuid, paging, dstaddr,
789 PROT_WRITE, &dstgpa, &fault);
793 error = memread(vm, vcpuid, srcgpa, &val, opsize, arg);
797 error = memwrite(vm, vcpuid, dstgpa, val, opsize, arg);
803 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSI, &rsi);
804 KASSERT(error == 0, ("%s: error %d getting rsi", __func__, error));
806 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
807 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
809 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
810 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
812 if (rflags & PSL_D) {
820 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSI, rsi,
822 KASSERT(error == 0, ("%s: error %d updating rsi", __func__, error));
824 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
826 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
830 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
832 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
835 * Repeat the instruction if the count register is not zero.
837 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
838 vm_restart_instruction(vm, vcpuid);
841 KASSERT(error == 0 || error == EFAULT, ("%s: unexpected error %d",
847 emulate_stos(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
848 struct vm_guest_paging *paging, mem_region_read_t memread,
849 mem_region_write_t memwrite, void *arg)
851 int error, opsize, repeat;
853 uint64_t rcx, rdi, rflags;
855 opsize = (vie->op.op_byte == 0xAA) ? 1 : vie->opsize;
856 repeat = vie->repz_present | vie->repnz_present;
859 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
860 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
863 * The count register is %rcx, %ecx or %cx depending on the
864 * address size of the instruction.
866 if ((rcx & vie_size2mask(vie->addrsize)) == 0)
870 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
871 KASSERT(!error, ("%s: error %d getting rax", __func__, error));
873 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
877 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
878 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
880 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
881 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
888 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
890 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
894 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
896 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
899 * Repeat the instruction if the count register is not zero.
901 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
902 vm_restart_instruction(vm, vcpuid);
909 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
910 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
913 enum vm_reg_name reg;
914 uint64_t result, rflags, rflags2, val1, val2;
919 switch (vie->op.op_byte) {
922 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
925 * 23/r and r16, r/m16
926 * 23/r and r32, r/m32
927 * REX.W + 23/r and r64, r/m64
930 /* get the first operand */
931 reg = gpr_map[vie->reg];
932 error = vie_read_register(vm, vcpuid, reg, &val1);
936 /* get the second operand */
937 error = memread(vm, vcpuid, gpa, &val2, size, arg);
941 /* perform the operation and write the result */
942 result = val1 & val2;
943 error = vie_update_register(vm, vcpuid, reg, result, size);
948 * AND mem (ModRM:r/m) with immediate and store the
951 * 81 /4 and r/m16, imm16
952 * 81 /4 and r/m32, imm32
953 * REX.W + 81 /4 and r/m64, imm32 sign-extended to 64
955 * 83 /4 and r/m16, imm8 sign-extended to 16
956 * 83 /4 and r/m32, imm8 sign-extended to 32
957 * REX.W + 83/4 and r/m64, imm8 sign-extended to 64
960 /* get the first operand */
961 error = memread(vm, vcpuid, gpa, &val1, size, arg);
966 * perform the operation with the pre-fetched immediate
967 * operand and write the result
969 result = val1 & vie->immediate;
970 error = memwrite(vm, vcpuid, gpa, result, size, arg);
978 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
983 * OF and CF are cleared; the SF, ZF and PF flags are set according
984 * to the result; AF is undefined.
986 * The updated status flags are obtained by subtracting 0 from 'result'.
988 rflags2 = getcc(size, result, 0);
989 rflags &= ~RFLAGS_STATUS_BITS;
990 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
992 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
997 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
998 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1001 enum vm_reg_name reg;
1002 uint64_t result, rflags, rflags2, val1, val2;
1007 switch (vie->op.op_byte) {
1010 * OR reg (ModRM:reg) and mem (ModRM:r/m) and store the
1013 * 0b/r or r16, r/m16
1014 * 0b/r or r32, r/m32
1015 * REX.W + 0b/r or r64, r/m64
1018 /* get the first operand */
1019 reg = gpr_map[vie->reg];
1020 error = vie_read_register(vm, vcpuid, reg, &val1);
1024 /* get the second operand */
1025 error = memread(vm, vcpuid, gpa, &val2, size, arg);
1029 /* perform the operation and write the result */
1030 result = val1 | val2;
1031 error = vie_update_register(vm, vcpuid, reg, result, size);
1036 * OR mem (ModRM:r/m) with immediate and store the
1039 * 81 /1 or r/m16, imm16
1040 * 81 /1 or r/m32, imm32
1041 * REX.W + 81 /1 or r/m64, imm32 sign-extended to 64
1043 * 83 /1 or r/m16, imm8 sign-extended to 16
1044 * 83 /1 or r/m32, imm8 sign-extended to 32
1045 * REX.W + 83/1 or r/m64, imm8 sign-extended to 64
1048 /* get the first operand */
1049 error = memread(vm, vcpuid, gpa, &val1, size, arg);
1054 * perform the operation with the pre-fetched immediate
1055 * operand and write the result
1057 result = val1 | vie->immediate;
1058 error = memwrite(vm, vcpuid, gpa, result, size, arg);
1066 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1071 * OF and CF are cleared; the SF, ZF and PF flags are set according
1072 * to the result; AF is undefined.
1074 * The updated status flags are obtained by subtracting 0 from 'result'.
1076 rflags2 = getcc(size, result, 0);
1077 rflags &= ~RFLAGS_STATUS_BITS;
1078 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
1080 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1085 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1086 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1089 uint64_t regop, memop, op1, op2, rflags, rflags2;
1090 enum vm_reg_name reg;
1093 switch (vie->op.op_byte) {
1097 * 39/r CMP r/m16, r16
1098 * 39/r CMP r/m32, r32
1099 * REX.W 39/r CMP r/m64, r64
1101 * 3B/r CMP r16, r/m16
1102 * 3B/r CMP r32, r/m32
1103 * REX.W + 3B/r CMP r64, r/m64
1105 * Compare the first operand with the second operand and
1106 * set status flags in EFLAGS register. The comparison is
1107 * performed by subtracting the second operand from the first
1108 * operand and then setting the status flags.
1111 /* Get the register operand */
1112 reg = gpr_map[vie->reg];
1113 error = vie_read_register(vm, vcpuid, reg, ®op);
1117 /* Get the memory operand */
1118 error = memread(vm, vcpuid, gpa, &memop, size, arg);
1122 if (vie->op.op_byte == 0x3B) {
1129 rflags2 = getcc(size, op1, op2);
1135 * 80 /7 cmp r/m8, imm8
1136 * REX + 80 /7 cmp r/m8, imm8
1138 * 81 /7 cmp r/m16, imm16
1139 * 81 /7 cmp r/m32, imm32
1140 * REX.W + 81 /7 cmp r/m64, imm32 sign-extended to 64
1142 * 83 /7 cmp r/m16, imm8 sign-extended to 16
1143 * 83 /7 cmp r/m32, imm8 sign-extended to 32
1144 * REX.W + 83 /7 cmp r/m64, imm8 sign-extended to 64
1146 * Compare mem (ModRM:r/m) with immediate and set
1147 * status flags according to the results. The
1148 * comparison is performed by subtracting the
1149 * immediate from the first operand and then setting
1153 if (vie->op.op_byte == 0x80)
1156 /* get the first operand */
1157 error = memread(vm, vcpuid, gpa, &op1, size, arg);
1161 rflags2 = getcc(size, op1, vie->immediate);
1166 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1169 rflags &= ~RFLAGS_STATUS_BITS;
1170 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1172 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1177 emulate_sub(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1178 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1181 uint64_t nval, rflags, rflags2, val1, val2;
1182 enum vm_reg_name reg;
1187 switch (vie->op.op_byte) {
1190 * SUB r/m from r and store the result in r
1192 * 2B/r SUB r16, r/m16
1193 * 2B/r SUB r32, r/m32
1194 * REX.W + 2B/r SUB r64, r/m64
1197 /* get the first operand */
1198 reg = gpr_map[vie->reg];
1199 error = vie_read_register(vm, vcpuid, reg, &val1);
1203 /* get the second operand */
1204 error = memread(vm, vcpuid, gpa, &val2, size, arg);
1208 /* perform the operation and write the result */
1210 error = vie_update_register(vm, vcpuid, reg, nval, size);
1217 rflags2 = getcc(size, val1, val2);
1218 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1223 rflags &= ~RFLAGS_STATUS_BITS;
1224 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1225 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1233 emulate_stack_op(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1234 struct vm_guest_paging *paging, mem_region_read_t memread,
1235 mem_region_write_t memwrite, void *arg)
1238 struct vm_copyinfo copyinfo[2];
1240 struct iovec copyinfo[2];
1242 struct seg_desc ss_desc;
1243 uint64_t cr0, rflags, rsp, stack_gla, val;
1244 int error, fault, size, stackaddrsize, pushop;
1248 pushop = (vie->op.op_type == VIE_OP_TYPE_PUSH) ? 1 : 0;
1251 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
1253 if (paging->cpu_mode == CPU_MODE_REAL) {
1255 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
1257 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
1258 * - Stack pointer size is always 64-bits.
1259 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
1260 * - 16-bit PUSH/POP is supported by using the operand size
1261 * override prefix (66H).
1264 size = vie->opsize_override ? 2 : 8;
1267 * In protected or compatibility mode the 'B' flag in the
1268 * stack-segment descriptor determines the size of the
1271 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
1272 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
1274 if (SEG_DESC_DEF32(ss_desc.access))
1280 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
1281 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
1283 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1284 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1286 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
1287 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
1292 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
1293 rsp, size, stackaddrsize, pushop ? PROT_WRITE : PROT_READ,
1295 vm_inject_ss(vm, vcpuid, 0);
1299 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
1300 vm_inject_ss(vm, vcpuid, 0);
1304 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
1305 vm_inject_ac(vm, vcpuid, 0);
1309 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size,
1310 pushop ? PROT_WRITE : PROT_READ, copyinfo, nitems(copyinfo),
1316 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
1318 vm_copyout(vm, vcpuid, &val, copyinfo, size);
1320 vm_copyin(vm, vcpuid, copyinfo, &val, size);
1321 error = memwrite(vm, vcpuid, mmio_gpa, val, size, arg);
1324 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1327 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
1329 KASSERT(error == 0, ("error %d updating rsp", error));
1335 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1336 struct vm_guest_paging *paging, mem_region_read_t memread,
1337 mem_region_write_t memwrite, void *arg)
1342 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1344 * PUSH is part of the group 5 extended opcodes and is identified
1345 * by ModRM:reg = b110.
1347 if ((vie->reg & 7) != 6)
1350 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1356 emulate_pop(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1357 struct vm_guest_paging *paging, mem_region_read_t memread,
1358 mem_region_write_t memwrite, void *arg)
1363 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1365 * POP is part of the group 1A extended opcodes and is identified
1366 * by ModRM:reg = b000.
1368 if ((vie->reg & 7) != 0)
1371 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1377 emulate_group1(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1378 struct vm_guest_paging *paging, mem_region_read_t memread,
1379 mem_region_write_t memwrite, void *memarg)
1383 switch (vie->reg & 7) {
1385 error = emulate_or(vm, vcpuid, gpa, vie,
1386 memread, memwrite, memarg);
1389 error = emulate_and(vm, vcpuid, gpa, vie,
1390 memread, memwrite, memarg);
1393 error = emulate_cmp(vm, vcpuid, gpa, vie,
1394 memread, memwrite, memarg);
1405 emulate_bittest(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1406 mem_region_read_t memread, mem_region_write_t memwrite, void *memarg)
1408 uint64_t val, rflags;
1409 int error, bitmask, bitoff;
1412 * 0F BA is a Group 8 extended opcode.
1414 * Currently we only emulate the 'Bit Test' instruction which is
1415 * identified by a ModR/M:reg encoding of 100b.
1417 if ((vie->reg & 7) != 4)
1420 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1421 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1423 error = memread(vm, vcpuid, gpa, &val, vie->opsize, memarg);
1428 * Intel SDM, Vol 2, Table 3-2:
1429 * "Range of Bit Positions Specified by Bit Offset Operands"
1431 bitmask = vie->opsize * 8 - 1;
1432 bitoff = vie->immediate & bitmask;
1434 /* Copy the bit into the Carry flag in %rflags */
1435 if (val & (1UL << bitoff))
1440 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1441 KASSERT(error == 0, ("%s: error %d updating rflags", __func__, error));
1447 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1448 struct vm_guest_paging *paging, mem_region_read_t memread,
1449 mem_region_write_t memwrite, void *memarg)
1456 switch (vie->op.op_type) {
1457 case VIE_OP_TYPE_GROUP1:
1458 error = emulate_group1(vm, vcpuid, gpa, vie, paging, memread,
1461 case VIE_OP_TYPE_POP:
1462 error = emulate_pop(vm, vcpuid, gpa, vie, paging, memread,
1465 case VIE_OP_TYPE_PUSH:
1466 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
1469 case VIE_OP_TYPE_CMP:
1470 error = emulate_cmp(vm, vcpuid, gpa, vie,
1471 memread, memwrite, memarg);
1473 case VIE_OP_TYPE_MOV:
1474 error = emulate_mov(vm, vcpuid, gpa, vie,
1475 memread, memwrite, memarg);
1477 case VIE_OP_TYPE_MOVSX:
1478 case VIE_OP_TYPE_MOVZX:
1479 error = emulate_movx(vm, vcpuid, gpa, vie,
1480 memread, memwrite, memarg);
1482 case VIE_OP_TYPE_MOVS:
1483 error = emulate_movs(vm, vcpuid, gpa, vie, paging, memread,
1486 case VIE_OP_TYPE_STOS:
1487 error = emulate_stos(vm, vcpuid, gpa, vie, paging, memread,
1490 case VIE_OP_TYPE_AND:
1491 error = emulate_and(vm, vcpuid, gpa, vie,
1492 memread, memwrite, memarg);
1494 case VIE_OP_TYPE_OR:
1495 error = emulate_or(vm, vcpuid, gpa, vie,
1496 memread, memwrite, memarg);
1498 case VIE_OP_TYPE_SUB:
1499 error = emulate_sub(vm, vcpuid, gpa, vie,
1500 memread, memwrite, memarg);
1502 case VIE_OP_TYPE_BITTEST:
1503 error = emulate_bittest(vm, vcpuid, gpa, vie,
1504 memread, memwrite, memarg);
1515 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
1517 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1518 ("%s: invalid size %d", __func__, size));
1519 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
1521 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
1524 return ((gla & (size - 1)) ? 1 : 0);
1528 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
1532 if (cpu_mode != CPU_MODE_64BIT)
1536 * The value of the bit 47 in the 'gla' should be replicated in the
1537 * most significant 16 bits.
1539 mask = ~((1UL << 48) - 1);
1540 if (gla & (1UL << 47))
1541 return ((gla & mask) != mask);
1543 return ((gla & mask) != 0);
1547 vie_size2mask(int size)
1549 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1550 ("vie_size2mask: invalid size %d", size));
1551 return (size2mask[size]);
1555 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
1556 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
1557 int prot, uint64_t *gla)
1559 uint64_t firstoff, low_limit, high_limit, segbase;
1562 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
1563 ("%s: invalid segment %d", __func__, seg));
1564 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
1565 ("%s: invalid operand size %d", __func__, length));
1566 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
1567 ("%s: invalid prot %#x", __func__, prot));
1570 if (cpu_mode == CPU_MODE_64BIT) {
1571 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
1572 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
1575 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
1576 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
1579 * If the segment selector is loaded with a NULL selector
1580 * then the descriptor is unusable and attempting to use
1581 * it results in a #GP(0).
1583 if (SEG_DESC_UNUSABLE(desc->access))
1587 * The processor generates a #NP exception when a segment
1588 * register is loaded with a selector that points to a
1589 * descriptor that is not present. If this was the case then
1590 * it would have been checked before the VM-exit.
1592 KASSERT(SEG_DESC_PRESENT(desc->access),
1593 ("segment %d not present: %#x", seg, desc->access));
1596 * The descriptor type must indicate a code/data segment.
1598 type = SEG_DESC_TYPE(desc->access);
1599 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
1600 "descriptor type %#x", seg, type));
1602 if (prot & PROT_READ) {
1603 /* #GP on a read access to a exec-only code segment */
1604 if ((type & 0xA) == 0x8)
1608 if (prot & PROT_WRITE) {
1610 * #GP on a write access to a code segment or a
1611 * read-only data segment.
1613 if (type & 0x8) /* code segment */
1616 if ((type & 0xA) == 0) /* read-only data seg */
1621 * 'desc->limit' is fully expanded taking granularity into
1624 if ((type & 0xC) == 0x4) {
1625 /* expand-down data segment */
1626 low_limit = desc->limit + 1;
1627 high_limit = SEG_DESC_DEF32(desc->access) ?
1628 0xffffffff : 0xffff;
1630 /* code segment or expand-up data segment */
1632 high_limit = desc->limit;
1635 while (length > 0) {
1636 offset &= vie_size2mask(addrsize);
1637 if (offset < low_limit || offset > high_limit)
1645 * In 64-bit mode all segments except %fs and %gs have a segment
1646 * base address of 0.
1648 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1649 seg != VM_REG_GUEST_GS) {
1652 segbase = desc->base;
1656 * Truncate 'firstoff' to the effective address size before adding
1657 * it to the segment base.
1659 firstoff &= vie_size2mask(addrsize);
1660 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1666 vie_init(struct vie *vie, const char *inst_bytes, int inst_length)
1668 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE,
1669 ("%s: invalid instruction length (%d)", __func__, inst_length));
1671 bzero(vie, sizeof(struct vie));
1673 vie->base_register = VM_REG_LAST;
1674 vie->index_register = VM_REG_LAST;
1675 vie->segment_register = VM_REG_LAST;
1678 bcopy(inst_bytes, vie->inst, inst_length);
1679 vie->num_valid = inst_length;
1684 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1689 error_code |= PGEX_P;
1690 if (prot & VM_PROT_WRITE)
1691 error_code |= PGEX_W;
1693 error_code |= PGEX_U;
1695 error_code |= PGEX_RSV;
1696 if (prot & VM_PROT_EXECUTE)
1697 error_code |= PGEX_I;
1699 return (error_code);
1703 ptp_release(void **cookie)
1705 if (*cookie != NULL) {
1706 vm_gpa_release(*cookie);
1712 ptp_hold(struct vm *vm, int vcpu, vm_paddr_t ptpphys, size_t len, void **cookie)
1716 ptp_release(cookie);
1717 ptr = vm_gpa_hold(vm, vcpu, ptpphys, len, VM_PROT_RW, cookie);
1722 _vm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1723 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault, bool check_only)
1725 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1727 uint64_t *ptpbase, ptpphys, pte, pgsize;
1728 uint32_t *ptpbase32, pte32;
1733 usermode = (paging->cpl == 3 ? 1 : 0);
1734 writable = prot & VM_PROT_WRITE;
1739 ptpphys = paging->cr3; /* root of the page tables */
1740 ptp_release(&cookie);
1744 if (vie_canonical_check(paging->cpu_mode, gla)) {
1746 * XXX assuming a non-stack reference otherwise a stack fault
1747 * should be generated.
1750 vm_inject_gp(vm, vcpuid);
1754 if (paging->paging_mode == PAGING_MODE_FLAT) {
1759 if (paging->paging_mode == PAGING_MODE_32) {
1761 while (--nlevels >= 0) {
1762 /* Zero out the lower 12 bits. */
1765 ptpbase32 = ptp_hold(vm, vcpuid, ptpphys, PAGE_SIZE,
1768 if (ptpbase32 == NULL)
1771 ptpshift = PAGE_SHIFT + nlevels * 10;
1772 ptpindex = (gla >> ptpshift) & 0x3FF;
1773 pgsize = 1UL << ptpshift;
1775 pte32 = ptpbase32[ptpindex];
1777 if ((pte32 & PG_V) == 0 ||
1778 (usermode && (pte32 & PG_U) == 0) ||
1779 (writable && (pte32 & PG_RW) == 0)) {
1781 pfcode = pf_error_code(usermode, prot, 0,
1783 vm_inject_pf(vm, vcpuid, pfcode, gla);
1789 * Emulate the x86 MMU's management of the accessed
1790 * and dirty flags. While the accessed flag is set
1791 * at every level of the page table, the dirty flag
1792 * is only set at the last level providing the guest
1795 if (!check_only && (pte32 & PG_A) == 0) {
1796 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1797 pte32, pte32 | PG_A) == 0) {
1802 /* XXX must be ignored if CR4.PSE=0 */
1803 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1809 /* Set the dirty bit in the page table entry if necessary */
1810 if (!check_only && writable && (pte32 & PG_M) == 0) {
1811 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1812 pte32, pte32 | PG_M) == 0) {
1817 /* Zero out the lower 'ptpshift' bits */
1818 pte32 >>= ptpshift; pte32 <<= ptpshift;
1819 *gpa = pte32 | (gla & (pgsize - 1));
1823 if (paging->paging_mode == PAGING_MODE_PAE) {
1824 /* Zero out the lower 5 bits and the upper 32 bits */
1825 ptpphys &= 0xffffffe0UL;
1827 ptpbase = ptp_hold(vm, vcpuid, ptpphys, sizeof(*ptpbase) * 4,
1829 if (ptpbase == NULL)
1832 ptpindex = (gla >> 30) & 0x3;
1834 pte = ptpbase[ptpindex];
1836 if ((pte & PG_V) == 0) {
1838 pfcode = pf_error_code(usermode, prot, 0, pte);
1839 vm_inject_pf(vm, vcpuid, pfcode, gla);
1849 while (--nlevels >= 0) {
1850 /* Zero out the lower 12 bits and the upper 12 bits */
1851 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1853 ptpbase = ptp_hold(vm, vcpuid, ptpphys, PAGE_SIZE, &cookie);
1854 if (ptpbase == NULL)
1857 ptpshift = PAGE_SHIFT + nlevels * 9;
1858 ptpindex = (gla >> ptpshift) & 0x1FF;
1859 pgsize = 1UL << ptpshift;
1861 pte = ptpbase[ptpindex];
1863 if ((pte & PG_V) == 0 ||
1864 (usermode && (pte & PG_U) == 0) ||
1865 (writable && (pte & PG_RW) == 0)) {
1867 pfcode = pf_error_code(usermode, prot, 0, pte);
1868 vm_inject_pf(vm, vcpuid, pfcode, gla);
1873 /* Set the accessed bit in the page table entry */
1874 if (!check_only && (pte & PG_A) == 0) {
1875 if (atomic_cmpset_64(&ptpbase[ptpindex],
1876 pte, pte | PG_A) == 0) {
1881 if (nlevels > 0 && (pte & PG_PS) != 0) {
1882 if (pgsize > 1 * GB) {
1884 pfcode = pf_error_code(usermode, prot, 1,
1886 vm_inject_pf(vm, vcpuid, pfcode, gla);
1896 /* Set the dirty bit in the page table entry if necessary */
1897 if (!check_only && writable && (pte & PG_M) == 0) {
1898 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1902 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1903 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1904 *gpa = pte | (gla & (pgsize - 1));
1906 ptp_release(&cookie);
1907 KASSERT(retval == 0 || retval == EFAULT, ("%s: unexpected retval %d",
1919 vm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1920 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault)
1923 return (_vm_gla2gpa(vm, vcpuid, paging, gla, prot, gpa, guest_fault,
1928 vm_gla2gpa_nofault(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1929 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault)
1932 return (_vm_gla2gpa(vm, vcpuid, paging, gla, prot, gpa, guest_fault,
1937 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1938 uint64_t rip, int inst_length, struct vie *vie, int *faultptr)
1940 struct vm_copyinfo copyinfo[2];
1943 if (inst_length > VIE_INST_SIZE)
1944 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1946 prot = PROT_READ | PROT_EXEC;
1947 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1948 copyinfo, nitems(copyinfo), faultptr);
1949 if (error || *faultptr)
1952 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1953 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1954 vie->num_valid = inst_length;
1959 vie_peek(struct vie *vie, uint8_t *x)
1962 if (vie->num_processed < vie->num_valid) {
1963 *x = vie->inst[vie->num_processed];
1970 vie_advance(struct vie *vie)
1973 vie->num_processed++;
1977 segment_override(uint8_t x, int *seg)
1982 *seg = VM_REG_GUEST_CS;
1985 *seg = VM_REG_GUEST_SS;
1988 *seg = VM_REG_GUEST_DS;
1991 *seg = VM_REG_GUEST_ES;
1994 *seg = VM_REG_GUEST_FS;
1997 *seg = VM_REG_GUEST_GS;
2006 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
2011 if (vie_peek(vie, &x))
2015 vie->opsize_override = 1;
2017 vie->addrsize_override = 1;
2019 vie->repz_present = 1;
2021 vie->repnz_present = 1;
2022 else if (segment_override(x, &vie->segment_register))
2023 vie->segment_override = 1;
2031 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
2032 * - Only one REX prefix is allowed per instruction.
2033 * - The REX prefix must immediately precede the opcode byte or the
2034 * escape opcode byte.
2035 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
2036 * the mandatory prefix must come before the REX prefix.
2038 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
2039 vie->rex_present = 1;
2040 vie->rex_w = x & 0x8 ? 1 : 0;
2041 vie->rex_r = x & 0x4 ? 1 : 0;
2042 vie->rex_x = x & 0x2 ? 1 : 0;
2043 vie->rex_b = x & 0x1 ? 1 : 0;
2048 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
2050 if (cpu_mode == CPU_MODE_64BIT) {
2052 * Default address size is 64-bits and default operand size
2055 vie->addrsize = vie->addrsize_override ? 4 : 8;
2058 else if (vie->opsize_override)
2063 /* Default address and operand sizes are 32-bits */
2064 vie->addrsize = vie->addrsize_override ? 2 : 4;
2065 vie->opsize = vie->opsize_override ? 2 : 4;
2067 /* Default address and operand sizes are 16-bits */
2068 vie->addrsize = vie->addrsize_override ? 4 : 2;
2069 vie->opsize = vie->opsize_override ? 4 : 2;
2075 decode_two_byte_opcode(struct vie *vie)
2079 if (vie_peek(vie, &x))
2082 vie->op = two_byte_opcodes[x];
2084 if (vie->op.op_type == VIE_OP_TYPE_NONE)
2092 decode_opcode(struct vie *vie)
2096 if (vie_peek(vie, &x))
2099 vie->op = one_byte_opcodes[x];
2101 if (vie->op.op_type == VIE_OP_TYPE_NONE)
2106 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
2107 return (decode_two_byte_opcode(vie));
2113 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
2117 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
2120 if (cpu_mode == CPU_MODE_REAL)
2123 if (vie_peek(vie, &x))
2126 vie->mod = (x >> 6) & 0x3;
2127 vie->rm = (x >> 0) & 0x7;
2128 vie->reg = (x >> 3) & 0x7;
2131 * A direct addressing mode makes no sense in the context of an EPT
2132 * fault. There has to be a memory access involved to cause the
2135 if (vie->mod == VIE_MOD_DIRECT)
2138 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
2139 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
2141 * Table 2-5: Special Cases of REX Encodings
2143 * mod=0, r/m=5 is used in the compatibility mode to
2144 * indicate a disp32 without a base register.
2146 * mod!=3, r/m=4 is used in the compatibility mode to
2147 * indicate that the SIB byte is present.
2149 * The 'b' bit in the REX prefix is don't care in
2153 vie->rm |= (vie->rex_b << 3);
2156 vie->reg |= (vie->rex_r << 3);
2159 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
2162 vie->base_register = gpr_map[vie->rm];
2165 case VIE_MOD_INDIRECT_DISP8:
2166 vie->disp_bytes = 1;
2168 case VIE_MOD_INDIRECT_DISP32:
2169 vie->disp_bytes = 4;
2171 case VIE_MOD_INDIRECT:
2172 if (vie->rm == VIE_RM_DISP32) {
2173 vie->disp_bytes = 4;
2175 * Table 2-7. RIP-Relative Addressing
2177 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
2178 * whereas in compatibility mode it just implies disp32.
2181 if (cpu_mode == CPU_MODE_64BIT)
2182 vie->base_register = VM_REG_GUEST_RIP;
2184 vie->base_register = VM_REG_LAST;
2196 decode_sib(struct vie *vie)
2200 /* Proceed only if SIB byte is present */
2201 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
2204 if (vie_peek(vie, &x))
2207 /* De-construct the SIB byte */
2208 vie->ss = (x >> 6) & 0x3;
2209 vie->index = (x >> 3) & 0x7;
2210 vie->base = (x >> 0) & 0x7;
2212 /* Apply the REX prefix modifiers */
2213 vie->index |= vie->rex_x << 3;
2214 vie->base |= vie->rex_b << 3;
2217 case VIE_MOD_INDIRECT_DISP8:
2218 vie->disp_bytes = 1;
2220 case VIE_MOD_INDIRECT_DISP32:
2221 vie->disp_bytes = 4;
2225 if (vie->mod == VIE_MOD_INDIRECT &&
2226 (vie->base == 5 || vie->base == 13)) {
2228 * Special case when base register is unused if mod = 0
2229 * and base = %rbp or %r13.
2232 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2233 * Table 2-5: Special Cases of REX Encodings
2235 vie->disp_bytes = 4;
2237 vie->base_register = gpr_map[vie->base];
2241 * All encodings of 'index' are valid except for %rsp (4).
2244 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2245 * Table 2-5: Special Cases of REX Encodings
2247 if (vie->index != 4)
2248 vie->index_register = gpr_map[vie->index];
2250 /* 'scale' makes sense only in the context of an index register */
2251 if (vie->index_register < VM_REG_LAST)
2252 vie->scale = 1 << vie->ss;
2260 decode_displacement(struct vie *vie)
2271 if ((n = vie->disp_bytes) == 0)
2274 if (n != 1 && n != 4)
2275 panic("decode_displacement: invalid disp_bytes %d", n);
2277 for (i = 0; i < n; i++) {
2278 if (vie_peek(vie, &x))
2286 vie->displacement = u.signed8; /* sign-extended */
2288 vie->displacement = u.signed32; /* sign-extended */
2294 decode_immediate(struct vie *vie)
2305 /* Figure out immediate operand size (if any) */
2306 if (vie->op.op_flags & VIE_OP_F_IMM) {
2308 * Section 2.2.1.5 "Immediates", Intel SDM:
2309 * In 64-bit mode the typical size of immediate operands
2310 * remains 32-bits. When the operand size if 64-bits, the
2311 * processor sign-extends all immediates to 64-bits prior
2314 if (vie->opsize == 4 || vie->opsize == 8)
2318 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
2322 if ((n = vie->imm_bytes) == 0)
2325 KASSERT(n == 1 || n == 2 || n == 4,
2326 ("%s: invalid number of immediate bytes: %d", __func__, n));
2328 for (i = 0; i < n; i++) {
2329 if (vie_peek(vie, &x))
2336 /* sign-extend the immediate value before use */
2338 vie->immediate = u.signed8;
2340 vie->immediate = u.signed16;
2342 vie->immediate = u.signed32;
2348 decode_moffset(struct vie *vie)
2357 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
2361 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
2362 * The memory offset size follows the address-size of the instruction.
2365 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
2368 for (i = 0; i < n; i++) {
2369 if (vie_peek(vie, &x))
2375 vie->displacement = u.u64;
2380 * Verify that the 'guest linear address' provided as collateral of the nested
2381 * page table fault matches with our instruction decoding.
2384 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie,
2385 enum vm_cpu_mode cpu_mode)
2388 uint64_t base, segbase, idx, gla2;
2389 enum vm_reg_name seg;
2390 struct seg_desc desc;
2392 /* Skip 'gla' verification */
2393 if (gla == VIE_INVALID_GLA)
2397 if (vie->base_register != VM_REG_LAST) {
2398 error = vm_get_register(vm, cpuid, vie->base_register, &base);
2400 printf("verify_gla: error %d getting base reg %d\n",
2401 error, vie->base_register);
2406 * RIP-relative addressing starts from the following
2409 if (vie->base_register == VM_REG_GUEST_RIP)
2410 base += vie->num_processed;
2414 if (vie->index_register != VM_REG_LAST) {
2415 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
2417 printf("verify_gla: error %d getting index reg %d\n",
2418 error, vie->index_register);
2424 * From "Specifying a Segment Selector", Intel SDM, Vol 1
2426 * In 64-bit mode, segmentation is generally (but not
2427 * completely) disabled. The exceptions are the FS and GS
2430 * In legacy IA-32 mode, when the ESP or EBP register is used
2431 * as the base, the SS segment is the default segment. For
2432 * other data references, except when relative to stack or
2433 * string destination the DS segment is the default. These
2434 * can be overridden to allow other segments to be accessed.
2436 if (vie->segment_override)
2437 seg = vie->segment_register;
2438 else if (vie->base_register == VM_REG_GUEST_RSP ||
2439 vie->base_register == VM_REG_GUEST_RBP)
2440 seg = VM_REG_GUEST_SS;
2442 seg = VM_REG_GUEST_DS;
2443 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
2444 seg != VM_REG_GUEST_GS) {
2447 error = vm_get_seg_desc(vm, cpuid, seg, &desc);
2449 printf("verify_gla: error %d getting segment"
2450 " descriptor %d", error,
2451 vie->segment_register);
2454 segbase = desc.base;
2457 gla2 = segbase + base + vie->scale * idx + vie->displacement;
2458 gla2 &= size2mask[vie->addrsize];
2460 printf("verify_gla mismatch: segbase(0x%0lx)"
2461 "base(0x%0lx), scale(%d), index(0x%0lx), "
2462 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
2463 segbase, base, vie->scale, idx, vie->displacement,
2472 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
2473 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
2476 if (decode_prefixes(vie, cpu_mode, cs_d))
2479 if (decode_opcode(vie))
2482 if (decode_modrm(vie, cpu_mode))
2485 if (decode_sib(vie))
2488 if (decode_displacement(vie))
2491 if (decode_immediate(vie))
2494 if (decode_moffset(vie))
2497 if ((vie->op.op_flags & VIE_OP_F_NO_GLA_VERIFICATION) == 0) {
2498 if (verify_gla(vm, cpuid, gla, vie, cpu_mode))
2502 vie->decoded = 1; /* success */
2506 #endif /* _KERNEL */