2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
47 #include <sys/_iovec.h>
49 #include <machine/vmm.h>
53 #define KASSERT(exp,msg) assert((exp))
56 #include <machine/vmm_instruction_emul.h>
58 #include <x86/specialreg.h>
60 /* struct vie_op.op_type */
80 /* struct vie_op.op_flags */
81 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
82 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
83 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
84 #define VIE_OP_F_NO_MODRM (1 << 3)
85 #define VIE_OP_F_NO_GLA_VERIFICATION (1 << 4)
87 static const struct vie_op two_byte_opcodes[256] = {
90 .op_type = VIE_OP_TYPE_MOVZX,
94 .op_type = VIE_OP_TYPE_MOVZX,
98 .op_type = VIE_OP_TYPE_BITTEST,
99 .op_flags = VIE_OP_F_IMM8,
103 .op_type = VIE_OP_TYPE_MOVSX,
107 static const struct vie_op one_byte_opcodes[256] = {
110 .op_type = VIE_OP_TYPE_TWO_BYTE
114 .op_type = VIE_OP_TYPE_SUB,
118 .op_type = VIE_OP_TYPE_CMP,
122 .op_type = VIE_OP_TYPE_MOV,
126 .op_type = VIE_OP_TYPE_MOV,
130 .op_type = VIE_OP_TYPE_MOV,
134 .op_type = VIE_OP_TYPE_MOV,
138 .op_type = VIE_OP_TYPE_MOV,
139 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
143 .op_type = VIE_OP_TYPE_MOV,
144 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
148 .op_type = VIE_OP_TYPE_MOVS,
149 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
153 .op_type = VIE_OP_TYPE_MOVS,
154 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
158 .op_type = VIE_OP_TYPE_STOS,
159 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
163 .op_type = VIE_OP_TYPE_STOS,
164 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
167 /* XXX Group 11 extended opcode - not just MOV */
169 .op_type = VIE_OP_TYPE_MOV,
170 .op_flags = VIE_OP_F_IMM8,
174 .op_type = VIE_OP_TYPE_MOV,
175 .op_flags = VIE_OP_F_IMM,
179 .op_type = VIE_OP_TYPE_AND,
182 /* Group 1 extended opcode */
184 .op_type = VIE_OP_TYPE_GROUP1,
185 .op_flags = VIE_OP_F_IMM8,
188 /* Group 1 extended opcode */
190 .op_type = VIE_OP_TYPE_GROUP1,
191 .op_flags = VIE_OP_F_IMM,
194 /* Group 1 extended opcode */
196 .op_type = VIE_OP_TYPE_GROUP1,
197 .op_flags = VIE_OP_F_IMM8,
200 /* XXX Group 1A extended opcode - not just POP */
202 .op_type = VIE_OP_TYPE_POP,
205 /* XXX Group 5 extended opcode - not just PUSH */
207 .op_type = VIE_OP_TYPE_PUSH,
212 #define VIE_MOD_INDIRECT 0
213 #define VIE_MOD_INDIRECT_DISP8 1
214 #define VIE_MOD_INDIRECT_DISP32 2
215 #define VIE_MOD_DIRECT 3
219 #define VIE_RM_DISP32 5
221 #define GB (1024 * 1024 * 1024)
223 static enum vm_reg_name gpr_map[16] = {
242 static uint64_t size2mask[] = {
246 [8] = 0xffffffffffffffff,
250 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
254 error = vm_get_register(vm, vcpuid, reg, rval);
260 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
263 *reg = gpr_map[vie->reg];
266 * 64-bit mode imposes limitations on accessing legacy high byte
269 * The legacy high-byte registers cannot be addressed if the REX
270 * prefix is present. In this case the values 4, 5, 6 and 7 of the
271 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
273 * If the REX prefix is not present then the values 4, 5, 6 and 7
274 * of the 'ModRM:reg' field address the legacy high-byte registers,
275 * %ah, %ch, %dh and %bh respectively.
277 if (!vie->rex_present) {
278 if (vie->reg & 0x4) {
280 *reg = gpr_map[vie->reg & 0x3];
286 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
290 enum vm_reg_name reg;
292 vie_calc_bytereg(vie, ®, &lhbr);
293 error = vm_get_register(vm, vcpuid, reg, &val);
296 * To obtain the value of a legacy high byte register shift the
297 * base register right by 8 bits (%ah = %rax >> 8).
307 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
309 uint64_t origval, val, mask;
311 enum vm_reg_name reg;
313 vie_calc_bytereg(vie, ®, &lhbr);
314 error = vm_get_register(vm, vcpuid, reg, &origval);
320 * Shift left by 8 to store 'byte' in a legacy high
326 val |= origval & ~mask;
327 error = vm_set_register(vm, vcpuid, reg, val);
333 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
334 uint64_t val, int size)
342 error = vie_read_register(vm, vcpuid, reg, &origval);
345 val &= size2mask[size];
346 val |= origval & ~size2mask[size];
357 error = vm_set_register(vm, vcpuid, reg, val);
361 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
364 * Return the status flags that would result from doing (x - y).
368 getcc##sz(uint##sz##_t x, uint##sz##_t y) \
372 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
373 "=r" (rflags), "+r" (x) : "m" (y)); \
383 getcc(int opsize, uint64_t x, uint64_t y)
385 KASSERT(opsize == 1 || opsize == 2 || opsize == 4 || opsize == 8,
386 ("getcc: invalid operand size %d", opsize));
389 return (getcc8(x, y));
390 else if (opsize == 2)
391 return (getcc16(x, y));
392 else if (opsize == 4)
393 return (getcc32(x, y));
395 return (getcc64(x, y));
399 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
400 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
403 enum vm_reg_name reg;
410 switch (vie->op.op_byte) {
413 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
415 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
417 size = 1; /* override for byte operation */
418 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
420 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
424 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
425 * 89/r: mov r/m16, r16
426 * 89/r: mov r/m32, r32
427 * REX.W + 89/r mov r/m64, r64
429 reg = gpr_map[vie->reg];
430 error = vie_read_register(vm, vcpuid, reg, &val);
432 val &= size2mask[size];
433 error = memwrite(vm, vcpuid, gpa, val, size, arg);
438 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
440 * REX + 8A/r: mov r8, r/m8
442 size = 1; /* override for byte operation */
443 error = memread(vm, vcpuid, gpa, &val, size, arg);
445 error = vie_write_bytereg(vm, vcpuid, vie, val);
449 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
450 * 8B/r: mov r16, r/m16
451 * 8B/r: mov r32, r/m32
452 * REX.W 8B/r: mov r64, r/m64
454 error = memread(vm, vcpuid, gpa, &val, size, arg);
456 reg = gpr_map[vie->reg];
457 error = vie_update_register(vm, vcpuid, reg, val, size);
462 * MOV from seg:moffset to AX/EAX/RAX
463 * A1: mov AX, moffs16
464 * A1: mov EAX, moffs32
465 * REX.W + A1: mov RAX, moffs64
467 error = memread(vm, vcpuid, gpa, &val, size, arg);
469 reg = VM_REG_GUEST_RAX;
470 error = vie_update_register(vm, vcpuid, reg, val, size);
475 * MOV from AX/EAX/RAX to seg:moffset
476 * A3: mov moffs16, AX
477 * A3: mov moffs32, EAX
478 * REX.W + A3: mov moffs64, RAX
480 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
482 val &= size2mask[size];
483 error = memwrite(vm, vcpuid, gpa, val, size, arg);
488 * MOV from imm8 to mem (ModRM:r/m)
489 * C6/0 mov r/m8, imm8
490 * REX + C6/0 mov r/m8, imm8
492 size = 1; /* override for byte operation */
493 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
497 * MOV from imm16/imm32 to mem (ModRM:r/m)
498 * C7/0 mov r/m16, imm16
499 * C7/0 mov r/m32, imm32
500 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
502 val = vie->immediate & size2mask[size];
503 error = memwrite(vm, vcpuid, gpa, val, size, arg);
513 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
514 mem_region_read_t memread, mem_region_write_t memwrite,
518 enum vm_reg_name reg;
524 switch (vie->op.op_byte) {
527 * MOV and zero extend byte from mem (ModRM:r/m) to
530 * 0F B6/r movzx r16, r/m8
531 * 0F B6/r movzx r32, r/m8
532 * REX.W + 0F B6/r movzx r64, r/m8
535 /* get the first operand */
536 error = memread(vm, vcpuid, gpa, &val, 1, arg);
540 /* get the second operand */
541 reg = gpr_map[vie->reg];
543 /* zero-extend byte */
546 /* write the result */
547 error = vie_update_register(vm, vcpuid, reg, val, size);
551 * MOV and zero extend word from mem (ModRM:r/m) to
554 * 0F B7/r movzx r32, r/m16
555 * REX.W + 0F B7/r movzx r64, r/m16
557 error = memread(vm, vcpuid, gpa, &val, 2, arg);
561 reg = gpr_map[vie->reg];
563 /* zero-extend word */
566 error = vie_update_register(vm, vcpuid, reg, val, size);
570 * MOV and sign extend byte from mem (ModRM:r/m) to
573 * 0F BE/r movsx r16, r/m8
574 * 0F BE/r movsx r32, r/m8
575 * REX.W + 0F BE/r movsx r64, r/m8
578 /* get the first operand */
579 error = memread(vm, vcpuid, gpa, &val, 1, arg);
583 /* get the second operand */
584 reg = gpr_map[vie->reg];
586 /* sign extend byte */
589 /* write the result */
590 error = vie_update_register(vm, vcpuid, reg, val, size);
599 * Helper function to calculate and validate a linear address.
601 * Returns 0 on success and 1 if an exception was injected into the guest.
604 get_gla(void *vm, int vcpuid, struct vie *vie, struct vm_guest_paging *paging,
605 int opsize, int addrsize, int prot, enum vm_reg_name seg,
606 enum vm_reg_name gpr, uint64_t *gla)
608 struct seg_desc desc;
609 uint64_t cr0, val, rflags;
612 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
613 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
615 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
616 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
618 error = vm_get_seg_desc(vm, vcpuid, seg, &desc);
619 KASSERT(error == 0, ("%s: error %d getting segment descriptor %d",
620 __func__, error, seg));
622 error = vie_read_register(vm, vcpuid, gpr, &val);
623 KASSERT(error == 0, ("%s: error %d getting register %d", __func__,
626 if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize,
627 addrsize, prot, gla)) {
628 if (seg == VM_REG_GUEST_SS)
629 vm_inject_ss(vm, vcpuid, 0);
631 vm_inject_gp(vm, vcpuid);
635 if (vie_canonical_check(paging->cpu_mode, *gla)) {
636 if (seg == VM_REG_GUEST_SS)
637 vm_inject_ss(vm, vcpuid, 0);
639 vm_inject_gp(vm, vcpuid);
643 if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) {
644 vm_inject_ac(vm, vcpuid, 0);
652 emulate_movs(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
653 struct vm_guest_paging *paging, mem_region_read_t memread,
654 mem_region_write_t memwrite, void *arg)
657 struct vm_copyinfo copyinfo[2];
659 struct iovec copyinfo[2];
661 uint64_t dstaddr, srcaddr, dstgpa, srcgpa, val;
662 uint64_t rcx, rdi, rsi, rflags;
663 int error, opsize, seg, repeat;
665 opsize = (vie->op.op_byte == 0xA4) ? 1 : vie->opsize;
670 * XXX although the MOVS instruction is only supposed to be used with
671 * the "rep" prefix some guests like FreeBSD will use "repnz" instead.
673 * Empirically the "repnz" prefix has identical behavior to "rep"
674 * and the zero flag does not make a difference.
676 repeat = vie->repz_present | vie->repnz_present;
679 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
680 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
683 * The count register is %rcx, %ecx or %cx depending on the
684 * address size of the instruction.
686 if ((rcx & vie_size2mask(vie->addrsize)) == 0)
691 * Source Destination Comments
692 * --------------------------------------------
693 * (1) memory memory n/a
694 * (2) memory mmio emulated
695 * (3) mmio memory emulated
696 * (4) mmio mmio emulated
698 * At this point we don't have sufficient information to distinguish
699 * between (2), (3) and (4). We use 'vm_copy_setup()' to tease this
700 * out because it will succeed only when operating on regular memory.
702 * XXX the emulation doesn't properly handle the case where 'gpa'
703 * is straddling the boundary between the normal memory and MMIO.
706 seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS;
707 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
708 PROT_READ, seg, VM_REG_GUEST_RSI, &srcaddr);
712 error = vm_copy_setup(vm, vcpuid, paging, srcaddr, opsize, PROT_READ,
713 copyinfo, nitems(copyinfo));
716 * case (2): read from system memory and write to mmio.
718 vm_copyin(vm, vcpuid, copyinfo, &val, opsize);
719 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
720 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
723 } else if (error > 0) {
725 * Resume guest execution to handle fault.
730 * 'vm_copy_setup()' is expected to fail for cases (3) and (4)
731 * if 'srcaddr' is in the mmio space.
734 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
735 PROT_WRITE, VM_REG_GUEST_ES, VM_REG_GUEST_RDI, &dstaddr);
739 error = vm_copy_setup(vm, vcpuid, paging, dstaddr, opsize,
740 PROT_WRITE, copyinfo, nitems(copyinfo));
743 * case (3): read from MMIO and write to system memory.
745 * A MMIO read can have side-effects so we
746 * commit to it only after vm_copy_setup() is
747 * successful. If a page-fault needs to be
748 * injected into the guest then it will happen
749 * before the MMIO read is attempted.
751 error = memread(vm, vcpuid, gpa, &val, opsize, arg);
755 vm_copyout(vm, vcpuid, &val, copyinfo, opsize);
756 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
757 } else if (error > 0) {
759 * Resume guest execution to handle fault.
764 * Case (4): read from and write to mmio.
766 error = vm_gla2gpa(vm, vcpuid, paging, srcaddr,
770 error = memread(vm, vcpuid, srcgpa, &val, opsize, arg);
774 error = vm_gla2gpa(vm, vcpuid, paging, dstaddr,
775 PROT_WRITE, &dstgpa);
778 error = memwrite(vm, vcpuid, dstgpa, val, opsize, arg);
784 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSI, &rsi);
785 KASSERT(error == 0, ("%s: error %d getting rsi", __func__, error));
787 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
788 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
790 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
791 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
793 if (rflags & PSL_D) {
801 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSI, rsi,
803 KASSERT(error == 0, ("%s: error %d updating rsi", __func__, error));
805 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
807 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
811 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
813 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
816 * Repeat the instruction if the count register is not zero.
818 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
819 vm_restart_instruction(vm, vcpuid);
829 emulate_stos(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
830 struct vm_guest_paging *paging, mem_region_read_t memread,
831 mem_region_write_t memwrite, void *arg)
833 int error, opsize, repeat;
835 uint64_t rcx, rdi, rflags;
837 opsize = (vie->op.op_byte == 0xAA) ? 1 : vie->opsize;
838 repeat = vie->repz_present | vie->repnz_present;
841 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
842 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
845 * The count register is %rcx, %ecx or %cx depending on the
846 * address size of the instruction.
848 if ((rcx & vie_size2mask(vie->addrsize)) == 0)
852 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
853 KASSERT(!error, ("%s: error %d getting rax", __func__, error));
855 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
859 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
860 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
862 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
863 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
870 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
872 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
876 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
878 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
881 * Repeat the instruction if the count register is not zero.
883 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
884 vm_restart_instruction(vm, vcpuid);
891 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
892 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
895 enum vm_reg_name reg;
896 uint64_t result, rflags, rflags2, val1, val2;
901 switch (vie->op.op_byte) {
904 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
907 * 23/r and r16, r/m16
908 * 23/r and r32, r/m32
909 * REX.W + 23/r and r64, r/m64
912 /* get the first operand */
913 reg = gpr_map[vie->reg];
914 error = vie_read_register(vm, vcpuid, reg, &val1);
918 /* get the second operand */
919 error = memread(vm, vcpuid, gpa, &val2, size, arg);
923 /* perform the operation and write the result */
924 result = val1 & val2;
925 error = vie_update_register(vm, vcpuid, reg, result, size);
930 * AND mem (ModRM:r/m) with immediate and store the
933 * 81 /4 and r/m16, imm16
934 * 81 /4 and r/m32, imm32
935 * REX.W + 81 /4 and r/m64, imm32 sign-extended to 64
937 * 83 /4 and r/m16, imm8 sign-extended to 16
938 * 83 /4 and r/m32, imm8 sign-extended to 32
939 * REX.W + 83/4 and r/m64, imm8 sign-extended to 64
942 /* get the first operand */
943 error = memread(vm, vcpuid, gpa, &val1, size, arg);
948 * perform the operation with the pre-fetched immediate
949 * operand and write the result
951 result = val1 & vie->immediate;
952 error = memwrite(vm, vcpuid, gpa, result, size, arg);
960 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
965 * OF and CF are cleared; the SF, ZF and PF flags are set according
966 * to the result; AF is undefined.
968 * The updated status flags are obtained by subtracting 0 from 'result'.
970 rflags2 = getcc(size, result, 0);
971 rflags &= ~RFLAGS_STATUS_BITS;
972 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
974 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
979 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
980 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
983 uint64_t val1, result, rflags, rflags2;
988 switch (vie->op.op_byte) {
992 * OR mem (ModRM:r/m) with immediate and store the
995 * 81 /1 or r/m16, imm16
996 * 81 /1 or r/m32, imm32
997 * REX.W + 81 /1 or r/m64, imm32 sign-extended to 64
999 * 83 /1 or r/m16, imm8 sign-extended to 16
1000 * 83 /1 or r/m32, imm8 sign-extended to 32
1001 * REX.W + 83/1 or r/m64, imm8 sign-extended to 64
1004 /* get the first operand */
1005 error = memread(vm, vcpuid, gpa, &val1, size, arg);
1010 * perform the operation with the pre-fetched immediate
1011 * operand and write the result
1013 result = val1 | vie->immediate;
1014 error = memwrite(vm, vcpuid, gpa, result, size, arg);
1022 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1027 * OF and CF are cleared; the SF, ZF and PF flags are set according
1028 * to the result; AF is undefined.
1030 * The updated status flags are obtained by subtracting 0 from 'result'.
1032 rflags2 = getcc(size, result, 0);
1033 rflags &= ~RFLAGS_STATUS_BITS;
1034 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
1036 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1041 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1042 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1045 uint64_t op1, op2, rflags, rflags2;
1046 enum vm_reg_name reg;
1049 switch (vie->op.op_byte) {
1052 * 3B/r CMP r16, r/m16
1053 * 3B/r CMP r32, r/m32
1054 * REX.W + 3B/r CMP r64, r/m64
1056 * Compare first operand (reg) with second operand (r/m) and
1057 * set status flags in EFLAGS register. The comparison is
1058 * performed by subtracting the second operand from the first
1059 * operand and then setting the status flags.
1062 /* Get the first operand */
1063 reg = gpr_map[vie->reg];
1064 error = vie_read_register(vm, vcpuid, reg, &op1);
1068 /* Get the second operand */
1069 error = memread(vm, vcpuid, gpa, &op2, size, arg);
1073 rflags2 = getcc(size, op1, op2);
1079 * 80 /7 cmp r/m8, imm8
1080 * REX + 80 /7 cmp r/m8, imm8
1082 * 81 /7 cmp r/m16, imm16
1083 * 81 /7 cmp r/m32, imm32
1084 * REX.W + 81 /7 cmp r/m64, imm32 sign-extended to 64
1086 * 83 /7 cmp r/m16, imm8 sign-extended to 16
1087 * 83 /7 cmp r/m32, imm8 sign-extended to 32
1088 * REX.W + 83 /7 cmp r/m64, imm8 sign-extended to 64
1090 * Compare mem (ModRM:r/m) with immediate and set
1091 * status flags according to the results. The
1092 * comparison is performed by subtracting the
1093 * immediate from the first operand and then setting
1097 if (vie->op.op_byte == 0x80)
1100 /* get the first operand */
1101 error = memread(vm, vcpuid, gpa, &op1, size, arg);
1105 rflags2 = getcc(size, op1, vie->immediate);
1110 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1113 rflags &= ~RFLAGS_STATUS_BITS;
1114 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1116 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1121 emulate_sub(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1122 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1125 uint64_t nval, rflags, rflags2, val1, val2;
1126 enum vm_reg_name reg;
1131 switch (vie->op.op_byte) {
1134 * SUB r/m from r and store the result in r
1136 * 2B/r SUB r16, r/m16
1137 * 2B/r SUB r32, r/m32
1138 * REX.W + 2B/r SUB r64, r/m64
1141 /* get the first operand */
1142 reg = gpr_map[vie->reg];
1143 error = vie_read_register(vm, vcpuid, reg, &val1);
1147 /* get the second operand */
1148 error = memread(vm, vcpuid, gpa, &val2, size, arg);
1152 /* perform the operation and write the result */
1154 error = vie_update_register(vm, vcpuid, reg, nval, size);
1161 rflags2 = getcc(size, val1, val2);
1162 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1167 rflags &= ~RFLAGS_STATUS_BITS;
1168 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1169 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1177 emulate_stack_op(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1178 struct vm_guest_paging *paging, mem_region_read_t memread,
1179 mem_region_write_t memwrite, void *arg)
1182 struct vm_copyinfo copyinfo[2];
1184 struct iovec copyinfo[2];
1186 struct seg_desc ss_desc;
1187 uint64_t cr0, rflags, rsp, stack_gla, val;
1188 int error, size, stackaddrsize, pushop;
1192 pushop = (vie->op.op_type == VIE_OP_TYPE_PUSH) ? 1 : 0;
1195 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
1197 if (paging->cpu_mode == CPU_MODE_REAL) {
1199 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
1201 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
1202 * - Stack pointer size is always 64-bits.
1203 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
1204 * - 16-bit PUSH/POP is supported by using the operand size
1205 * override prefix (66H).
1208 size = vie->opsize_override ? 2 : 8;
1211 * In protected or compability mode the 'B' flag in the
1212 * stack-segment descriptor determines the size of the
1215 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
1216 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
1218 if (SEG_DESC_DEF32(ss_desc.access))
1224 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
1225 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
1227 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1228 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1230 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
1231 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
1236 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
1237 rsp, size, stackaddrsize, pushop ? PROT_WRITE : PROT_READ,
1239 vm_inject_ss(vm, vcpuid, 0);
1243 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
1244 vm_inject_ss(vm, vcpuid, 0);
1248 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
1249 vm_inject_ac(vm, vcpuid, 0);
1253 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size,
1254 pushop ? PROT_WRITE : PROT_READ, copyinfo, nitems(copyinfo));
1257 * XXX cannot return a negative error value here because it
1258 * ends up being the return value of the VM_RUN() ioctl and
1259 * is interpreted as a pseudo-error (for e.g. ERESTART).
1262 } else if (error == 1) {
1263 /* Resume guest execution to handle page fault */
1268 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
1270 vm_copyout(vm, vcpuid, &val, copyinfo, size);
1272 vm_copyin(vm, vcpuid, copyinfo, &val, size);
1273 error = memwrite(vm, vcpuid, mmio_gpa, val, size, arg);
1276 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1279 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
1281 KASSERT(error == 0, ("error %d updating rsp", error));
1287 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1288 struct vm_guest_paging *paging, mem_region_read_t memread,
1289 mem_region_write_t memwrite, void *arg)
1294 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1296 * PUSH is part of the group 5 extended opcodes and is identified
1297 * by ModRM:reg = b110.
1299 if ((vie->reg & 7) != 6)
1302 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1308 emulate_pop(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1309 struct vm_guest_paging *paging, mem_region_read_t memread,
1310 mem_region_write_t memwrite, void *arg)
1315 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1317 * POP is part of the group 1A extended opcodes and is identified
1318 * by ModRM:reg = b000.
1320 if ((vie->reg & 7) != 0)
1323 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1329 emulate_group1(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1330 struct vm_guest_paging *paging, mem_region_read_t memread,
1331 mem_region_write_t memwrite, void *memarg)
1335 switch (vie->reg & 7) {
1337 error = emulate_or(vm, vcpuid, gpa, vie,
1338 memread, memwrite, memarg);
1341 error = emulate_and(vm, vcpuid, gpa, vie,
1342 memread, memwrite, memarg);
1345 error = emulate_cmp(vm, vcpuid, gpa, vie,
1346 memread, memwrite, memarg);
1357 emulate_bittest(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1358 mem_region_read_t memread, mem_region_write_t memwrite, void *memarg)
1360 uint64_t val, rflags;
1361 int error, bitmask, bitoff;
1364 * 0F BA is a Group 8 extended opcode.
1366 * Currently we only emulate the 'Bit Test' instruction which is
1367 * identified by a ModR/M:reg encoding of 100b.
1369 if ((vie->reg & 7) != 4)
1372 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1373 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1375 error = memread(vm, vcpuid, gpa, &val, vie->opsize, memarg);
1380 * Intel SDM, Vol 2, Table 3-2:
1381 * "Range of Bit Positions Specified by Bit Offset Operands"
1383 bitmask = vie->opsize * 8 - 1;
1384 bitoff = vie->immediate & bitmask;
1386 /* Copy the bit into the Carry flag in %rflags */
1387 if (val & (1UL << bitoff))
1392 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1393 KASSERT(error == 0, ("%s: error %d updating rflags", __func__, error));
1399 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1400 struct vm_guest_paging *paging, mem_region_read_t memread,
1401 mem_region_write_t memwrite, void *memarg)
1408 switch (vie->op.op_type) {
1409 case VIE_OP_TYPE_GROUP1:
1410 error = emulate_group1(vm, vcpuid, gpa, vie, paging, memread,
1413 case VIE_OP_TYPE_POP:
1414 error = emulate_pop(vm, vcpuid, gpa, vie, paging, memread,
1417 case VIE_OP_TYPE_PUSH:
1418 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
1421 case VIE_OP_TYPE_CMP:
1422 error = emulate_cmp(vm, vcpuid, gpa, vie,
1423 memread, memwrite, memarg);
1425 case VIE_OP_TYPE_MOV:
1426 error = emulate_mov(vm, vcpuid, gpa, vie,
1427 memread, memwrite, memarg);
1429 case VIE_OP_TYPE_MOVSX:
1430 case VIE_OP_TYPE_MOVZX:
1431 error = emulate_movx(vm, vcpuid, gpa, vie,
1432 memread, memwrite, memarg);
1434 case VIE_OP_TYPE_MOVS:
1435 error = emulate_movs(vm, vcpuid, gpa, vie, paging, memread,
1438 case VIE_OP_TYPE_STOS:
1439 error = emulate_stos(vm, vcpuid, gpa, vie, paging, memread,
1442 case VIE_OP_TYPE_AND:
1443 error = emulate_and(vm, vcpuid, gpa, vie,
1444 memread, memwrite, memarg);
1446 case VIE_OP_TYPE_OR:
1447 error = emulate_or(vm, vcpuid, gpa, vie,
1448 memread, memwrite, memarg);
1450 case VIE_OP_TYPE_SUB:
1451 error = emulate_sub(vm, vcpuid, gpa, vie,
1452 memread, memwrite, memarg);
1454 case VIE_OP_TYPE_BITTEST:
1455 error = emulate_bittest(vm, vcpuid, gpa, vie,
1456 memread, memwrite, memarg);
1467 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
1469 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1470 ("%s: invalid size %d", __func__, size));
1471 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
1473 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
1476 return ((gla & (size - 1)) ? 1 : 0);
1480 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
1484 if (cpu_mode != CPU_MODE_64BIT)
1488 * The value of the bit 47 in the 'gla' should be replicated in the
1489 * most significant 16 bits.
1491 mask = ~((1UL << 48) - 1);
1492 if (gla & (1UL << 47))
1493 return ((gla & mask) != mask);
1495 return ((gla & mask) != 0);
1499 vie_size2mask(int size)
1501 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1502 ("vie_size2mask: invalid size %d", size));
1503 return (size2mask[size]);
1507 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
1508 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
1509 int prot, uint64_t *gla)
1511 uint64_t firstoff, low_limit, high_limit, segbase;
1514 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
1515 ("%s: invalid segment %d", __func__, seg));
1516 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
1517 ("%s: invalid operand size %d", __func__, length));
1518 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
1519 ("%s: invalid prot %#x", __func__, prot));
1522 if (cpu_mode == CPU_MODE_64BIT) {
1523 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
1524 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
1527 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
1528 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
1531 * If the segment selector is loaded with a NULL selector
1532 * then the descriptor is unusable and attempting to use
1533 * it results in a #GP(0).
1535 if (SEG_DESC_UNUSABLE(desc->access))
1539 * The processor generates a #NP exception when a segment
1540 * register is loaded with a selector that points to a
1541 * descriptor that is not present. If this was the case then
1542 * it would have been checked before the VM-exit.
1544 KASSERT(SEG_DESC_PRESENT(desc->access),
1545 ("segment %d not present: %#x", seg, desc->access));
1548 * The descriptor type must indicate a code/data segment.
1550 type = SEG_DESC_TYPE(desc->access);
1551 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
1552 "descriptor type %#x", seg, type));
1554 if (prot & PROT_READ) {
1555 /* #GP on a read access to a exec-only code segment */
1556 if ((type & 0xA) == 0x8)
1560 if (prot & PROT_WRITE) {
1562 * #GP on a write access to a code segment or a
1563 * read-only data segment.
1565 if (type & 0x8) /* code segment */
1568 if ((type & 0xA) == 0) /* read-only data seg */
1573 * 'desc->limit' is fully expanded taking granularity into
1576 if ((type & 0xC) == 0x4) {
1577 /* expand-down data segment */
1578 low_limit = desc->limit + 1;
1579 high_limit = SEG_DESC_DEF32(desc->access) ?
1580 0xffffffff : 0xffff;
1582 /* code segment or expand-up data segment */
1584 high_limit = desc->limit;
1587 while (length > 0) {
1588 offset &= vie_size2mask(addrsize);
1589 if (offset < low_limit || offset > high_limit)
1597 * In 64-bit mode all segments except %fs and %gs have a segment
1598 * base address of 0.
1600 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1601 seg != VM_REG_GUEST_GS) {
1604 segbase = desc->base;
1608 * Truncate 'firstoff' to the effective address size before adding
1609 * it to the segment base.
1611 firstoff &= vie_size2mask(addrsize);
1612 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1618 vie_init(struct vie *vie, const char *inst_bytes, int inst_length)
1620 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE,
1621 ("%s: invalid instruction length (%d)", __func__, inst_length));
1623 bzero(vie, sizeof(struct vie));
1625 vie->base_register = VM_REG_LAST;
1626 vie->index_register = VM_REG_LAST;
1627 vie->segment_register = VM_REG_LAST;
1630 bcopy(inst_bytes, vie->inst, inst_length);
1631 vie->num_valid = inst_length;
1636 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1641 error_code |= PGEX_P;
1642 if (prot & VM_PROT_WRITE)
1643 error_code |= PGEX_W;
1645 error_code |= PGEX_U;
1647 error_code |= PGEX_RSV;
1648 if (prot & VM_PROT_EXECUTE)
1649 error_code |= PGEX_I;
1651 return (error_code);
1655 ptp_release(void **cookie)
1657 if (*cookie != NULL) {
1658 vm_gpa_release(*cookie);
1664 ptp_hold(struct vm *vm, vm_paddr_t ptpphys, size_t len, void **cookie)
1668 ptp_release(cookie);
1669 ptr = vm_gpa_hold(vm, ptpphys, len, VM_PROT_RW, cookie);
1674 vm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1675 uint64_t gla, int prot, uint64_t *gpa)
1677 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1679 uint64_t *ptpbase, ptpphys, pte, pgsize;
1680 uint32_t *ptpbase32, pte32;
1683 usermode = (paging->cpl == 3 ? 1 : 0);
1684 writable = prot & VM_PROT_WRITE;
1689 ptpphys = paging->cr3; /* root of the page tables */
1690 ptp_release(&cookie);
1694 if (vie_canonical_check(paging->cpu_mode, gla)) {
1696 * XXX assuming a non-stack reference otherwise a stack fault
1697 * should be generated.
1699 vm_inject_gp(vm, vcpuid);
1703 if (paging->paging_mode == PAGING_MODE_FLAT) {
1708 if (paging->paging_mode == PAGING_MODE_32) {
1710 while (--nlevels >= 0) {
1711 /* Zero out the lower 12 bits. */
1714 ptpbase32 = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1716 if (ptpbase32 == NULL)
1719 ptpshift = PAGE_SHIFT + nlevels * 10;
1720 ptpindex = (gla >> ptpshift) & 0x3FF;
1721 pgsize = 1UL << ptpshift;
1723 pte32 = ptpbase32[ptpindex];
1725 if ((pte32 & PG_V) == 0 ||
1726 (usermode && (pte32 & PG_U) == 0) ||
1727 (writable && (pte32 & PG_RW) == 0)) {
1728 pfcode = pf_error_code(usermode, prot, 0,
1730 vm_inject_pf(vm, vcpuid, pfcode, gla);
1735 * Emulate the x86 MMU's management of the accessed
1736 * and dirty flags. While the accessed flag is set
1737 * at every level of the page table, the dirty flag
1738 * is only set at the last level providing the guest
1741 if ((pte32 & PG_A) == 0) {
1742 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1743 pte32, pte32 | PG_A) == 0) {
1748 /* XXX must be ignored if CR4.PSE=0 */
1749 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1755 /* Set the dirty bit in the page table entry if necessary */
1756 if (writable && (pte32 & PG_M) == 0) {
1757 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1758 pte32, pte32 | PG_M) == 0) {
1763 /* Zero out the lower 'ptpshift' bits */
1764 pte32 >>= ptpshift; pte32 <<= ptpshift;
1765 *gpa = pte32 | (gla & (pgsize - 1));
1769 if (paging->paging_mode == PAGING_MODE_PAE) {
1770 /* Zero out the lower 5 bits and the upper 32 bits */
1771 ptpphys &= 0xffffffe0UL;
1773 ptpbase = ptp_hold(vm, ptpphys, sizeof(*ptpbase) * 4, &cookie);
1774 if (ptpbase == NULL)
1777 ptpindex = (gla >> 30) & 0x3;
1779 pte = ptpbase[ptpindex];
1781 if ((pte & PG_V) == 0) {
1782 pfcode = pf_error_code(usermode, prot, 0, pte);
1783 vm_inject_pf(vm, vcpuid, pfcode, gla);
1792 while (--nlevels >= 0) {
1793 /* Zero out the lower 12 bits and the upper 12 bits */
1794 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1796 ptpbase = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1797 if (ptpbase == NULL)
1800 ptpshift = PAGE_SHIFT + nlevels * 9;
1801 ptpindex = (gla >> ptpshift) & 0x1FF;
1802 pgsize = 1UL << ptpshift;
1804 pte = ptpbase[ptpindex];
1806 if ((pte & PG_V) == 0 ||
1807 (usermode && (pte & PG_U) == 0) ||
1808 (writable && (pte & PG_RW) == 0)) {
1809 pfcode = pf_error_code(usermode, prot, 0, pte);
1810 vm_inject_pf(vm, vcpuid, pfcode, gla);
1814 /* Set the accessed bit in the page table entry */
1815 if ((pte & PG_A) == 0) {
1816 if (atomic_cmpset_64(&ptpbase[ptpindex],
1817 pte, pte | PG_A) == 0) {
1822 if (nlevels > 0 && (pte & PG_PS) != 0) {
1823 if (pgsize > 1 * GB) {
1824 pfcode = pf_error_code(usermode, prot, 1, pte);
1825 vm_inject_pf(vm, vcpuid, pfcode, gla);
1834 /* Set the dirty bit in the page table entry if necessary */
1835 if (writable && (pte & PG_M) == 0) {
1836 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1840 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1841 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1842 *gpa = pte | (gla & (pgsize - 1));
1844 ptp_release(&cookie);
1855 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1856 uint64_t rip, int inst_length, struct vie *vie)
1858 struct vm_copyinfo copyinfo[2];
1861 if (inst_length > VIE_INST_SIZE)
1862 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1864 prot = PROT_READ | PROT_EXEC;
1865 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1866 copyinfo, nitems(copyinfo));
1868 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1869 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1870 vie->num_valid = inst_length;
1876 vie_peek(struct vie *vie, uint8_t *x)
1879 if (vie->num_processed < vie->num_valid) {
1880 *x = vie->inst[vie->num_processed];
1887 vie_advance(struct vie *vie)
1890 vie->num_processed++;
1894 segment_override(uint8_t x, int *seg)
1899 *seg = VM_REG_GUEST_CS;
1902 *seg = VM_REG_GUEST_SS;
1905 *seg = VM_REG_GUEST_DS;
1908 *seg = VM_REG_GUEST_ES;
1911 *seg = VM_REG_GUEST_FS;
1914 *seg = VM_REG_GUEST_GS;
1923 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
1928 if (vie_peek(vie, &x))
1932 vie->opsize_override = 1;
1934 vie->addrsize_override = 1;
1936 vie->repz_present = 1;
1938 vie->repnz_present = 1;
1939 else if (segment_override(x, &vie->segment_register))
1940 vie->segment_override = 1;
1948 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
1949 * - Only one REX prefix is allowed per instruction.
1950 * - The REX prefix must immediately precede the opcode byte or the
1951 * escape opcode byte.
1952 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
1953 * the mandatory prefix must come before the REX prefix.
1955 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
1956 vie->rex_present = 1;
1957 vie->rex_w = x & 0x8 ? 1 : 0;
1958 vie->rex_r = x & 0x4 ? 1 : 0;
1959 vie->rex_x = x & 0x2 ? 1 : 0;
1960 vie->rex_b = x & 0x1 ? 1 : 0;
1965 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
1967 if (cpu_mode == CPU_MODE_64BIT) {
1969 * Default address size is 64-bits and default operand size
1972 vie->addrsize = vie->addrsize_override ? 4 : 8;
1975 else if (vie->opsize_override)
1980 /* Default address and operand sizes are 32-bits */
1981 vie->addrsize = vie->addrsize_override ? 2 : 4;
1982 vie->opsize = vie->opsize_override ? 2 : 4;
1984 /* Default address and operand sizes are 16-bits */
1985 vie->addrsize = vie->addrsize_override ? 4 : 2;
1986 vie->opsize = vie->opsize_override ? 4 : 2;
1992 decode_two_byte_opcode(struct vie *vie)
1996 if (vie_peek(vie, &x))
1999 vie->op = two_byte_opcodes[x];
2001 if (vie->op.op_type == VIE_OP_TYPE_NONE)
2009 decode_opcode(struct vie *vie)
2013 if (vie_peek(vie, &x))
2016 vie->op = one_byte_opcodes[x];
2018 if (vie->op.op_type == VIE_OP_TYPE_NONE)
2023 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
2024 return (decode_two_byte_opcode(vie));
2030 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
2034 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
2037 if (cpu_mode == CPU_MODE_REAL)
2040 if (vie_peek(vie, &x))
2043 vie->mod = (x >> 6) & 0x3;
2044 vie->rm = (x >> 0) & 0x7;
2045 vie->reg = (x >> 3) & 0x7;
2048 * A direct addressing mode makes no sense in the context of an EPT
2049 * fault. There has to be a memory access involved to cause the
2052 if (vie->mod == VIE_MOD_DIRECT)
2055 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
2056 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
2058 * Table 2-5: Special Cases of REX Encodings
2060 * mod=0, r/m=5 is used in the compatibility mode to
2061 * indicate a disp32 without a base register.
2063 * mod!=3, r/m=4 is used in the compatibility mode to
2064 * indicate that the SIB byte is present.
2066 * The 'b' bit in the REX prefix is don't care in
2070 vie->rm |= (vie->rex_b << 3);
2073 vie->reg |= (vie->rex_r << 3);
2076 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
2079 vie->base_register = gpr_map[vie->rm];
2082 case VIE_MOD_INDIRECT_DISP8:
2083 vie->disp_bytes = 1;
2085 case VIE_MOD_INDIRECT_DISP32:
2086 vie->disp_bytes = 4;
2088 case VIE_MOD_INDIRECT:
2089 if (vie->rm == VIE_RM_DISP32) {
2090 vie->disp_bytes = 4;
2092 * Table 2-7. RIP-Relative Addressing
2094 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
2095 * whereas in compatibility mode it just implies disp32.
2098 if (cpu_mode == CPU_MODE_64BIT)
2099 vie->base_register = VM_REG_GUEST_RIP;
2101 vie->base_register = VM_REG_LAST;
2113 decode_sib(struct vie *vie)
2117 /* Proceed only if SIB byte is present */
2118 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
2121 if (vie_peek(vie, &x))
2124 /* De-construct the SIB byte */
2125 vie->ss = (x >> 6) & 0x3;
2126 vie->index = (x >> 3) & 0x7;
2127 vie->base = (x >> 0) & 0x7;
2129 /* Apply the REX prefix modifiers */
2130 vie->index |= vie->rex_x << 3;
2131 vie->base |= vie->rex_b << 3;
2134 case VIE_MOD_INDIRECT_DISP8:
2135 vie->disp_bytes = 1;
2137 case VIE_MOD_INDIRECT_DISP32:
2138 vie->disp_bytes = 4;
2142 if (vie->mod == VIE_MOD_INDIRECT &&
2143 (vie->base == 5 || vie->base == 13)) {
2145 * Special case when base register is unused if mod = 0
2146 * and base = %rbp or %r13.
2149 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2150 * Table 2-5: Special Cases of REX Encodings
2152 vie->disp_bytes = 4;
2154 vie->base_register = gpr_map[vie->base];
2158 * All encodings of 'index' are valid except for %rsp (4).
2161 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2162 * Table 2-5: Special Cases of REX Encodings
2164 if (vie->index != 4)
2165 vie->index_register = gpr_map[vie->index];
2167 /* 'scale' makes sense only in the context of an index register */
2168 if (vie->index_register < VM_REG_LAST)
2169 vie->scale = 1 << vie->ss;
2177 decode_displacement(struct vie *vie)
2188 if ((n = vie->disp_bytes) == 0)
2191 if (n != 1 && n != 4)
2192 panic("decode_displacement: invalid disp_bytes %d", n);
2194 for (i = 0; i < n; i++) {
2195 if (vie_peek(vie, &x))
2203 vie->displacement = u.signed8; /* sign-extended */
2205 vie->displacement = u.signed32; /* sign-extended */
2211 decode_immediate(struct vie *vie)
2222 /* Figure out immediate operand size (if any) */
2223 if (vie->op.op_flags & VIE_OP_F_IMM) {
2225 * Section 2.2.1.5 "Immediates", Intel SDM:
2226 * In 64-bit mode the typical size of immediate operands
2227 * remains 32-bits. When the operand size if 64-bits, the
2228 * processor sign-extends all immediates to 64-bits prior
2231 if (vie->opsize == 4 || vie->opsize == 8)
2235 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
2239 if ((n = vie->imm_bytes) == 0)
2242 KASSERT(n == 1 || n == 2 || n == 4,
2243 ("%s: invalid number of immediate bytes: %d", __func__, n));
2245 for (i = 0; i < n; i++) {
2246 if (vie_peek(vie, &x))
2253 /* sign-extend the immediate value before use */
2255 vie->immediate = u.signed8;
2257 vie->immediate = u.signed16;
2259 vie->immediate = u.signed32;
2265 decode_moffset(struct vie *vie)
2274 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
2278 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
2279 * The memory offset size follows the address-size of the instruction.
2282 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
2285 for (i = 0; i < n; i++) {
2286 if (vie_peek(vie, &x))
2292 vie->displacement = u.u64;
2297 * Verify that all the bytes in the instruction buffer were consumed.
2300 verify_inst_length(struct vie *vie)
2303 if (vie->num_processed)
2310 * Verify that the 'guest linear address' provided as collateral of the nested
2311 * page table fault matches with our instruction decoding.
2314 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
2317 uint64_t base, idx, gla2;
2319 /* Skip 'gla' verification */
2320 if (gla == VIE_INVALID_GLA)
2324 if (vie->base_register != VM_REG_LAST) {
2325 error = vm_get_register(vm, cpuid, vie->base_register, &base);
2327 printf("verify_gla: error %d getting base reg %d\n",
2328 error, vie->base_register);
2333 * RIP-relative addressing starts from the following
2336 if (vie->base_register == VM_REG_GUEST_RIP)
2337 base += vie->num_valid;
2341 if (vie->index_register != VM_REG_LAST) {
2342 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
2344 printf("verify_gla: error %d getting index reg %d\n",
2345 error, vie->index_register);
2350 /* XXX assuming that the base address of the segment is 0 */
2351 gla2 = base + vie->scale * idx + vie->displacement;
2352 gla2 &= size2mask[vie->addrsize];
2354 printf("verify_gla mismatch: "
2355 "base(0x%0lx), scale(%d), index(0x%0lx), "
2356 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
2357 base, vie->scale, idx, vie->displacement, gla, gla2);
2365 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
2366 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
2369 if (decode_prefixes(vie, cpu_mode, cs_d))
2372 if (decode_opcode(vie))
2375 if (decode_modrm(vie, cpu_mode))
2378 if (decode_sib(vie))
2381 if (decode_displacement(vie))
2384 if (decode_immediate(vie))
2387 if (decode_moffset(vie))
2390 if (verify_inst_length(vie))
2393 if ((vie->op.op_flags & VIE_OP_F_NO_GLA_VERIFICATION) == 0) {
2394 if (verify_gla(vm, cpuid, gla, vie))
2398 vie->decoded = 1; /* success */
2402 #endif /* _KERNEL */