2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
41 #include <machine/pmap.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
48 #include <machine/vmm.h>
54 CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
55 CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
58 /* struct vie_op.op_type */
67 /* struct vie_op.op_flags */
68 #define VIE_OP_F_IMM (1 << 0) /* immediate operand present */
69 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
71 static const struct vie_op one_byte_opcodes[256] = {
74 .op_type = VIE_OP_TYPE_MOV,
78 .op_type = VIE_OP_TYPE_MOV,
82 .op_type = VIE_OP_TYPE_MOV,
86 .op_type = VIE_OP_TYPE_MOV,
87 .op_flags = VIE_OP_F_IMM,
91 .op_type = VIE_OP_TYPE_AND,
94 /* XXX Group 1 extended opcode - not just AND */
96 .op_type = VIE_OP_TYPE_AND,
97 .op_flags = VIE_OP_F_IMM,
100 /* XXX Group 1 extended opcode - not just OR */
102 .op_type = VIE_OP_TYPE_OR,
103 .op_flags = VIE_OP_F_IMM8,
108 #define VIE_MOD_INDIRECT 0
109 #define VIE_MOD_INDIRECT_DISP8 1
110 #define VIE_MOD_INDIRECT_DISP32 2
111 #define VIE_MOD_DIRECT 3
115 #define VIE_RM_DISP32 5
117 #define GB (1024 * 1024 * 1024)
119 static enum vm_reg_name gpr_map[16] = {
138 static uint64_t size2mask[] = {
142 [8] = 0xffffffffffffffff,
146 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
150 error = vm_get_register(vm, vcpuid, reg, rval);
156 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
160 enum vm_reg_name reg;
163 reg = gpr_map[vie->reg];
166 * 64-bit mode imposes limitations on accessing legacy byte registers.
168 * The legacy high-byte registers cannot be addressed if the REX
169 * prefix is present. In this case the values 4, 5, 6 and 7 of the
170 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
172 * If the REX prefix is not present then the values 4, 5, 6 and 7
173 * of the 'ModRM:reg' field address the legacy high-byte registers,
174 * %ah, %ch, %dh and %bh respectively.
176 if (!vie->rex_present) {
177 if (vie->reg & 0x4) {
179 * Obtain the value of %ah by reading %rax and shifting
180 * right by 8 bits (same for %bh, %ch and %dh).
183 reg = gpr_map[vie->reg & 0x3];
187 error = vm_get_register(vm, vcpuid, reg, &val);
188 *rval = val >> rshift;
193 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
194 uint64_t val, int size)
202 error = vie_read_register(vm, vcpuid, reg, &origval);
205 val &= size2mask[size];
206 val |= origval & ~size2mask[size];
217 error = vm_set_register(vm, vcpuid, reg, val);
222 * The following simplifying assumptions are made during emulation:
224 * - guest is in 64-bit mode
225 * - default address size is 64-bits
226 * - default operand size is 32-bits
228 * - operand size override is not supported
230 * - address size override is not supported
233 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
234 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
237 enum vm_reg_name reg;
244 switch (vie->op.op_byte) {
247 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
249 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
252 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
254 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
258 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
259 * 89/r: mov r/m32, r32
260 * REX.W + 89/r mov r/m64, r64
264 reg = gpr_map[vie->reg];
265 error = vie_read_register(vm, vcpuid, reg, &val);
267 val &= size2mask[size];
268 error = memwrite(vm, vcpuid, gpa, val, size, arg);
273 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
274 * 8B/r: mov r32, r/m32
275 * REX.W 8B/r: mov r64, r/m64
279 error = memread(vm, vcpuid, gpa, &val, size, arg);
281 reg = gpr_map[vie->reg];
282 error = vie_update_register(vm, vcpuid, reg, val, size);
287 * MOV from imm32 to mem (ModRM:r/m)
288 * C7/0 mov r/m32, imm32
289 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
291 val = vie->immediate; /* already sign-extended */
297 val &= size2mask[size];
299 error = memwrite(vm, vcpuid, gpa, val, size, arg);
309 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
310 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
313 enum vm_reg_name reg;
319 switch (vie->op.op_byte) {
322 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
325 * 23/r and r32, r/m32
326 * REX.W + 23/r and r64, r/m64
331 /* get the first operand */
332 reg = gpr_map[vie->reg];
333 error = vie_read_register(vm, vcpuid, reg, &val1);
337 /* get the second operand */
338 error = memread(vm, vcpuid, gpa, &val2, size, arg);
342 /* perform the operation and write the result */
344 error = vie_update_register(vm, vcpuid, reg, val1, size);
348 * AND mem (ModRM:r/m) with immediate and store the
351 * 81/ and r/m32, imm32
352 * REX.W + 81/ and r/m64, imm32 sign-extended to 64
354 * Currently, only the AND operation of the 0x81 opcode
355 * is implemented (ModRM:reg = b100).
357 if ((vie->reg & 7) != 4)
363 /* get the first operand */
364 error = memread(vm, vcpuid, gpa, &val1, size, arg);
369 * perform the operation with the pre-fetched immediate
370 * operand and write the result
372 val1 &= vie->immediate;
373 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
382 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
383 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
391 switch (vie->op.op_byte) {
394 * OR mem (ModRM:r/m) with immediate and store the
397 * 83/ OR r/m32, imm8 sign-extended to 32
398 * REX.W + 83/ OR r/m64, imm8 sign-extended to 64
400 * Currently, only the OR operation of the 0x83 opcode
401 * is implemented (ModRM:reg = b001).
403 if ((vie->reg & 7) != 1)
409 /* get the first operand */
410 error = memread(vm, vcpuid, gpa, &val1, size, arg);
415 * perform the operation with the pre-fetched immediate
416 * operand and write the result
418 val1 |= vie->immediate;
419 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
428 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
429 mem_region_read_t memread, mem_region_write_t memwrite,
437 switch (vie->op.op_type) {
438 case VIE_OP_TYPE_MOV:
439 error = emulate_mov(vm, vcpuid, gpa, vie,
440 memread, memwrite, memarg);
442 case VIE_OP_TYPE_AND:
443 error = emulate_and(vm, vcpuid, gpa, vie,
444 memread, memwrite, memarg);
447 error = emulate_or(vm, vcpuid, gpa, vie,
448 memread, memwrite, memarg);
460 vie_init(struct vie *vie)
463 bzero(vie, sizeof(struct vie));
465 vie->base_register = VM_REG_LAST;
466 vie->index_register = VM_REG_LAST;
470 gla2gpa(struct vm *vm, uint64_t gla, uint64_t ptpphys,
471 uint64_t *gpa, uint64_t *gpaend)
474 int nlevels, ptpshift, ptpindex;
475 uint64_t *ptpbase, pte, pgsize;
478 * XXX assumes 64-bit guest with 4 page walk levels
481 while (--nlevels >= 0) {
482 /* Zero out the lower 12 bits and the upper 12 bits */
483 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
485 hpa = vm_gpa2hpa(vm, ptpphys, PAGE_SIZE);
489 ptpbase = (uint64_t *)PHYS_TO_DMAP(hpa);
491 ptpshift = PAGE_SHIFT + nlevels * 9;
492 ptpindex = (gla >> ptpshift) & 0x1FF;
493 pgsize = 1UL << ptpshift;
495 pte = ptpbase[ptpindex];
497 if ((pte & PG_V) == 0)
510 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
511 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
512 *gpa = pte | (gla & (pgsize - 1));
513 *gpaend = pte + pgsize;
521 vmm_fetch_instruction(struct vm *vm, int cpuid, uint64_t rip, int inst_length,
522 uint64_t cr3, struct vie *vie)
525 uint64_t hpa, gpa, gpaend, off;
528 * XXX cache previously fetched instructions using 'rip' as the tag
531 if (inst_length > VIE_INST_SIZE)
532 panic("vmm_fetch_instruction: invalid length %d", inst_length);
536 /* Copy the instruction into 'vie' */
537 while (vie->num_valid < inst_length) {
538 err = gla2gpa(vm, rip, cr3, &gpa, &gpaend);
542 off = gpa & PAGE_MASK;
543 n = min(inst_length - vie->num_valid, PAGE_SIZE - off);
545 hpa = vm_gpa2hpa(vm, gpa, n);
549 bcopy((void *)PHYS_TO_DMAP(hpa), &vie->inst[vie->num_valid], n);
555 if (vie->num_valid == inst_length)
562 vie_peek(struct vie *vie, uint8_t *x)
565 if (vie->num_processed < vie->num_valid) {
566 *x = vie->inst[vie->num_processed];
573 vie_advance(struct vie *vie)
576 vie->num_processed++;
580 decode_rex(struct vie *vie)
584 if (vie_peek(vie, &x))
587 if (x >= 0x40 && x <= 0x4F) {
588 vie->rex_present = 1;
590 vie->rex_w = x & 0x8 ? 1 : 0;
591 vie->rex_r = x & 0x4 ? 1 : 0;
592 vie->rex_x = x & 0x2 ? 1 : 0;
593 vie->rex_b = x & 0x1 ? 1 : 0;
602 decode_opcode(struct vie *vie)
606 if (vie_peek(vie, &x))
609 vie->op = one_byte_opcodes[x];
611 if (vie->op.op_type == VIE_OP_TYPE_NONE)
619 decode_modrm(struct vie *vie)
622 enum cpu_mode cpu_mode;
625 * XXX assuming that guest is in IA-32E 64-bit mode
627 cpu_mode = CPU_MODE_64BIT;
629 if (vie_peek(vie, &x))
632 vie->mod = (x >> 6) & 0x3;
633 vie->rm = (x >> 0) & 0x7;
634 vie->reg = (x >> 3) & 0x7;
637 * A direct addressing mode makes no sense in the context of an EPT
638 * fault. There has to be a memory access involved to cause the
641 if (vie->mod == VIE_MOD_DIRECT)
644 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
645 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
647 * Table 2-5: Special Cases of REX Encodings
649 * mod=0, r/m=5 is used in the compatibility mode to
650 * indicate a disp32 without a base register.
652 * mod!=3, r/m=4 is used in the compatibility mode to
653 * indicate that the SIB byte is present.
655 * The 'b' bit in the REX prefix is don't care in
659 vie->rm |= (vie->rex_b << 3);
662 vie->reg |= (vie->rex_r << 3);
665 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
668 vie->base_register = gpr_map[vie->rm];
671 case VIE_MOD_INDIRECT_DISP8:
674 case VIE_MOD_INDIRECT_DISP32:
677 case VIE_MOD_INDIRECT:
678 if (vie->rm == VIE_RM_DISP32) {
681 * Table 2-7. RIP-Relative Addressing
683 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
684 * whereas in compatibility mode it just implies disp32.
687 if (cpu_mode == CPU_MODE_64BIT)
688 vie->base_register = VM_REG_GUEST_RIP;
690 vie->base_register = VM_REG_LAST;
696 /* Figure out immediate operand size (if any) */
697 if (vie->op.op_flags & VIE_OP_F_IMM)
699 else if (vie->op.op_flags & VIE_OP_F_IMM8)
709 decode_sib(struct vie *vie)
713 /* Proceed only if SIB byte is present */
714 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
717 if (vie_peek(vie, &x))
720 /* De-construct the SIB byte */
721 vie->ss = (x >> 6) & 0x3;
722 vie->index = (x >> 3) & 0x7;
723 vie->base = (x >> 0) & 0x7;
725 /* Apply the REX prefix modifiers */
726 vie->index |= vie->rex_x << 3;
727 vie->base |= vie->rex_b << 3;
730 case VIE_MOD_INDIRECT_DISP8:
733 case VIE_MOD_INDIRECT_DISP32:
738 if (vie->mod == VIE_MOD_INDIRECT &&
739 (vie->base == 5 || vie->base == 13)) {
741 * Special case when base register is unused if mod = 0
742 * and base = %rbp or %r13.
745 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
746 * Table 2-5: Special Cases of REX Encodings
750 vie->base_register = gpr_map[vie->base];
754 * All encodings of 'index' are valid except for %rsp (4).
757 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
758 * Table 2-5: Special Cases of REX Encodings
761 vie->index_register = gpr_map[vie->index];
763 /* 'scale' makes sense only in the context of an index register */
764 if (vie->index_register < VM_REG_LAST)
765 vie->scale = 1 << vie->ss;
773 decode_displacement(struct vie *vie)
784 if ((n = vie->disp_bytes) == 0)
787 if (n != 1 && n != 4)
788 panic("decode_displacement: invalid disp_bytes %d", n);
790 for (i = 0; i < n; i++) {
791 if (vie_peek(vie, &x))
799 vie->displacement = u.signed8; /* sign-extended */
801 vie->displacement = u.signed32; /* sign-extended */
807 decode_immediate(struct vie *vie)
817 if ((n = vie->imm_bytes) == 0)
820 if (n != 1 && n != 4)
821 panic("decode_immediate: invalid imm_bytes %d", n);
823 for (i = 0; i < n; i++) {
824 if (vie_peek(vie, &x))
832 vie->immediate = u.signed8; /* sign-extended */
834 vie->immediate = u.signed32; /* sign-extended */
840 * Verify that all the bytes in the instruction buffer were consumed.
843 verify_inst_length(struct vie *vie)
846 if (vie->num_processed)
853 * Verify that the 'guest linear address' provided as collateral of the nested
854 * page table fault matches with our instruction decoding.
857 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
862 /* Skip 'gla' verification */
863 if (gla == VIE_INVALID_GLA)
867 if (vie->base_register != VM_REG_LAST) {
868 error = vm_get_register(vm, cpuid, vie->base_register, &base);
870 printf("verify_gla: error %d getting base reg %d\n",
871 error, vie->base_register);
876 * RIP-relative addressing starts from the following
879 if (vie->base_register == VM_REG_GUEST_RIP)
880 base += vie->num_valid;
884 if (vie->index_register != VM_REG_LAST) {
885 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
887 printf("verify_gla: error %d getting index reg %d\n",
888 error, vie->index_register);
893 if (base + vie->scale * idx + vie->displacement != gla) {
894 printf("verify_gla mismatch: "
895 "base(0x%0lx), scale(%d), index(0x%0lx), "
896 "disp(0x%0lx), gla(0x%0lx)\n",
897 base, vie->scale, idx, vie->displacement, gla);
905 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
911 if (decode_opcode(vie))
914 if (decode_modrm(vie))
920 if (decode_displacement(vie))
923 if (decode_immediate(vie))
926 if (verify_inst_length(vie))
929 if (verify_gla(vm, cpuid, gla, vie))
932 vie->decoded = 1; /* success */