2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
47 #include <sys/_iovec.h>
49 #include <machine/vmm.h>
53 #define KASSERT(exp,msg) assert((exp))
56 #include <machine/vmm_instruction_emul.h>
58 #include <x86/specialreg.h>
60 /* struct vie_op.op_type */
78 /* struct vie_op.op_flags */
79 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
80 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
81 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
82 #define VIE_OP_F_NO_MODRM (1 << 3)
83 #define VIE_OP_F_NO_GLA_VERIFICATION (1 << 4)
85 static const struct vie_op two_byte_opcodes[256] = {
88 .op_type = VIE_OP_TYPE_MOVZX,
92 .op_type = VIE_OP_TYPE_MOVZX,
96 .op_type = VIE_OP_TYPE_MOVSX,
100 static const struct vie_op one_byte_opcodes[256] = {
103 .op_type = VIE_OP_TYPE_TWO_BYTE
107 .op_type = VIE_OP_TYPE_SUB,
111 .op_type = VIE_OP_TYPE_CMP,
115 .op_type = VIE_OP_TYPE_MOV,
119 .op_type = VIE_OP_TYPE_MOV,
123 .op_type = VIE_OP_TYPE_MOV,
127 .op_type = VIE_OP_TYPE_MOV,
131 .op_type = VIE_OP_TYPE_MOV,
132 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
136 .op_type = VIE_OP_TYPE_MOV,
137 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
141 .op_type = VIE_OP_TYPE_MOVS,
142 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
146 .op_type = VIE_OP_TYPE_MOVS,
147 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
150 /* XXX Group 11 extended opcode - not just MOV */
152 .op_type = VIE_OP_TYPE_MOV,
153 .op_flags = VIE_OP_F_IMM8,
157 .op_type = VIE_OP_TYPE_MOV,
158 .op_flags = VIE_OP_F_IMM,
162 .op_type = VIE_OP_TYPE_AND,
165 /* XXX Group 1 extended opcode */
167 .op_type = VIE_OP_TYPE_GROUP1,
168 .op_flags = VIE_OP_F_IMM,
171 /* XXX Group 1 extended opcode */
173 .op_type = VIE_OP_TYPE_GROUP1,
174 .op_flags = VIE_OP_F_IMM8,
177 /* XXX Group 1A extended opcode - not just POP */
179 .op_type = VIE_OP_TYPE_POP,
182 /* XXX Group 5 extended opcode - not just PUSH */
184 .op_type = VIE_OP_TYPE_PUSH,
189 #define VIE_MOD_INDIRECT 0
190 #define VIE_MOD_INDIRECT_DISP8 1
191 #define VIE_MOD_INDIRECT_DISP32 2
192 #define VIE_MOD_DIRECT 3
196 #define VIE_RM_DISP32 5
198 #define GB (1024 * 1024 * 1024)
200 static enum vm_reg_name gpr_map[16] = {
219 static uint64_t size2mask[] = {
223 [8] = 0xffffffffffffffff,
227 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
231 error = vm_get_register(vm, vcpuid, reg, rval);
237 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
240 *reg = gpr_map[vie->reg];
243 * 64-bit mode imposes limitations on accessing legacy high byte
246 * The legacy high-byte registers cannot be addressed if the REX
247 * prefix is present. In this case the values 4, 5, 6 and 7 of the
248 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
250 * If the REX prefix is not present then the values 4, 5, 6 and 7
251 * of the 'ModRM:reg' field address the legacy high-byte registers,
252 * %ah, %ch, %dh and %bh respectively.
254 if (!vie->rex_present) {
255 if (vie->reg & 0x4) {
257 *reg = gpr_map[vie->reg & 0x3];
263 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
267 enum vm_reg_name reg;
269 vie_calc_bytereg(vie, ®, &lhbr);
270 error = vm_get_register(vm, vcpuid, reg, &val);
273 * To obtain the value of a legacy high byte register shift the
274 * base register right by 8 bits (%ah = %rax >> 8).
284 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
286 uint64_t origval, val, mask;
288 enum vm_reg_name reg;
290 vie_calc_bytereg(vie, ®, &lhbr);
291 error = vm_get_register(vm, vcpuid, reg, &origval);
297 * Shift left by 8 to store 'byte' in a legacy high
303 val |= origval & ~mask;
304 error = vm_set_register(vm, vcpuid, reg, val);
310 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
311 uint64_t val, int size)
319 error = vie_read_register(vm, vcpuid, reg, &origval);
322 val &= size2mask[size];
323 val |= origval & ~size2mask[size];
334 error = vm_set_register(vm, vcpuid, reg, val);
338 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
341 * Return the status flags that would result from doing (x - y).
345 getcc##sz(uint##sz##_t x, uint##sz##_t y) \
349 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
350 "=r" (rflags), "+r" (x) : "m" (y)); \
360 getcc(int opsize, uint64_t x, uint64_t y)
362 KASSERT(opsize == 1 || opsize == 2 || opsize == 4 || opsize == 8,
363 ("getcc: invalid operand size %d", opsize));
366 return (getcc8(x, y));
367 else if (opsize == 2)
368 return (getcc16(x, y));
369 else if (opsize == 4)
370 return (getcc32(x, y));
372 return (getcc64(x, y));
376 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
377 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
380 enum vm_reg_name reg;
387 switch (vie->op.op_byte) {
390 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
392 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
394 size = 1; /* override for byte operation */
395 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
397 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
401 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
402 * 89/r: mov r/m16, r16
403 * 89/r: mov r/m32, r32
404 * REX.W + 89/r mov r/m64, r64
406 reg = gpr_map[vie->reg];
407 error = vie_read_register(vm, vcpuid, reg, &val);
409 val &= size2mask[size];
410 error = memwrite(vm, vcpuid, gpa, val, size, arg);
415 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
417 * REX + 8A/r: mov r8, r/m8
419 size = 1; /* override for byte operation */
420 error = memread(vm, vcpuid, gpa, &val, size, arg);
422 error = vie_write_bytereg(vm, vcpuid, vie, val);
426 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
427 * 8B/r: mov r16, r/m16
428 * 8B/r: mov r32, r/m32
429 * REX.W 8B/r: mov r64, r/m64
431 error = memread(vm, vcpuid, gpa, &val, size, arg);
433 reg = gpr_map[vie->reg];
434 error = vie_update_register(vm, vcpuid, reg, val, size);
439 * MOV from seg:moffset to AX/EAX/RAX
440 * A1: mov AX, moffs16
441 * A1: mov EAX, moffs32
442 * REX.W + A1: mov RAX, moffs64
444 error = memread(vm, vcpuid, gpa, &val, size, arg);
446 reg = VM_REG_GUEST_RAX;
447 error = vie_update_register(vm, vcpuid, reg, val, size);
452 * MOV from AX/EAX/RAX to seg:moffset
453 * A3: mov moffs16, AX
454 * A3: mov moffs32, EAX
455 * REX.W + A3: mov moffs64, RAX
457 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
459 val &= size2mask[size];
460 error = memwrite(vm, vcpuid, gpa, val, size, arg);
465 * MOV from imm8 to mem (ModRM:r/m)
466 * C6/0 mov r/m8, imm8
467 * REX + C6/0 mov r/m8, imm8
469 size = 1; /* override for byte operation */
470 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
474 * MOV from imm16/imm32 to mem (ModRM:r/m)
475 * C7/0 mov r/m16, imm16
476 * C7/0 mov r/m32, imm32
477 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
479 val = vie->immediate & size2mask[size];
480 error = memwrite(vm, vcpuid, gpa, val, size, arg);
490 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
491 mem_region_read_t memread, mem_region_write_t memwrite,
495 enum vm_reg_name reg;
501 switch (vie->op.op_byte) {
504 * MOV and zero extend byte from mem (ModRM:r/m) to
507 * 0F B6/r movzx r16, r/m8
508 * 0F B6/r movzx r32, r/m8
509 * REX.W + 0F B6/r movzx r64, r/m8
512 /* get the first operand */
513 error = memread(vm, vcpuid, gpa, &val, 1, arg);
517 /* get the second operand */
518 reg = gpr_map[vie->reg];
520 /* zero-extend byte */
523 /* write the result */
524 error = vie_update_register(vm, vcpuid, reg, val, size);
528 * MOV and zero extend word from mem (ModRM:r/m) to
531 * 0F B7/r movzx r32, r/m16
532 * REX.W + 0F B7/r movzx r64, r/m16
534 error = memread(vm, vcpuid, gpa, &val, 2, arg);
538 reg = gpr_map[vie->reg];
540 /* zero-extend word */
543 error = vie_update_register(vm, vcpuid, reg, val, size);
547 * MOV and sign extend byte from mem (ModRM:r/m) to
550 * 0F BE/r movsx r16, r/m8
551 * 0F BE/r movsx r32, r/m8
552 * REX.W + 0F BE/r movsx r64, r/m8
555 /* get the first operand */
556 error = memread(vm, vcpuid, gpa, &val, 1, arg);
560 /* get the second operand */
561 reg = gpr_map[vie->reg];
563 /* sign extend byte */
566 /* write the result */
567 error = vie_update_register(vm, vcpuid, reg, val, size);
576 * Helper function to calculate and validate a linear address.
578 * Returns 0 on success and 1 if an exception was injected into the guest.
581 get_gla(void *vm, int vcpuid, struct vie *vie, struct vm_guest_paging *paging,
582 int opsize, int addrsize, int prot, enum vm_reg_name seg,
583 enum vm_reg_name gpr, uint64_t *gla)
585 struct seg_desc desc;
586 uint64_t cr0, val, rflags;
589 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
590 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
592 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
593 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
595 error = vm_get_seg_desc(vm, vcpuid, seg, &desc);
596 KASSERT(error == 0, ("%s: error %d getting segment descriptor %d",
597 __func__, error, seg));
599 error = vie_read_register(vm, vcpuid, gpr, &val);
600 KASSERT(error == 0, ("%s: error %d getting register %d", __func__,
603 if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize,
604 addrsize, prot, gla)) {
605 if (seg == VM_REG_GUEST_SS)
606 vm_inject_ss(vm, vcpuid, 0);
608 vm_inject_gp(vm, vcpuid);
612 if (vie_canonical_check(paging->cpu_mode, *gla)) {
613 if (seg == VM_REG_GUEST_SS)
614 vm_inject_ss(vm, vcpuid, 0);
616 vm_inject_gp(vm, vcpuid);
620 if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) {
621 vm_inject_ac(vm, vcpuid, 0);
629 emulate_movs(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
630 struct vm_guest_paging *paging, mem_region_read_t memread,
631 mem_region_write_t memwrite, void *arg)
634 struct vm_copyinfo copyinfo[2];
636 struct iovec copyinfo[2];
638 uint64_t dstaddr, srcaddr, dstgpa, srcgpa, val;
639 uint64_t rcx, rdi, rsi, rflags;
640 int error, opsize, seg, repeat;
642 opsize = (vie->op.op_byte == 0xA4) ? 1 : vie->opsize;
647 * XXX although the MOVS instruction is only supposed to be used with
648 * the "rep" prefix some guests like FreeBSD will use "repnz" instead.
650 * Empirically the "repnz" prefix has identical behavior to "rep"
651 * and the zero flag does not make a difference.
653 repeat = vie->repz_present | vie->repnz_present;
656 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
657 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
660 * The count register is %rcx, %ecx or %cx depending on the
661 * address size of the instruction.
663 if ((rcx & vie_size2mask(vie->addrsize)) == 0)
668 * Source Destination Comments
669 * --------------------------------------------
670 * (1) memory memory n/a
671 * (2) memory mmio emulated
672 * (3) mmio memory emulated
673 * (4) mmio mmio emulated
675 * At this point we don't have sufficient information to distinguish
676 * between (2), (3) and (4). We use 'vm_copy_setup()' to tease this
677 * out because it will succeed only when operating on regular memory.
679 * XXX the emulation doesn't properly handle the case where 'gpa'
680 * is straddling the boundary between the normal memory and MMIO.
683 seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS;
684 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
685 PROT_READ, seg, VM_REG_GUEST_RSI, &srcaddr);
689 error = vm_copy_setup(vm, vcpuid, paging, srcaddr, opsize, PROT_READ,
690 copyinfo, nitems(copyinfo));
693 * case (2): read from system memory and write to mmio.
695 vm_copyin(vm, vcpuid, copyinfo, &val, opsize);
696 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
697 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
700 } else if (error > 0) {
702 * Resume guest execution to handle fault.
707 * 'vm_copy_setup()' is expected to fail for cases (3) and (4)
708 * if 'srcaddr' is in the mmio space.
711 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
712 PROT_WRITE, VM_REG_GUEST_ES, VM_REG_GUEST_RDI, &dstaddr);
716 error = vm_copy_setup(vm, vcpuid, paging, dstaddr, opsize,
717 PROT_WRITE, copyinfo, nitems(copyinfo));
720 * case (3): read from MMIO and write to system memory.
722 * A MMIO read can have side-effects so we
723 * commit to it only after vm_copy_setup() is
724 * successful. If a page-fault needs to be
725 * injected into the guest then it will happen
726 * before the MMIO read is attempted.
728 error = memread(vm, vcpuid, gpa, &val, opsize, arg);
732 vm_copyout(vm, vcpuid, &val, copyinfo, opsize);
733 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
734 } else if (error > 0) {
736 * Resume guest execution to handle fault.
741 * Case (4): read from and write to mmio.
743 error = vm_gla2gpa(vm, vcpuid, paging, srcaddr,
747 error = memread(vm, vcpuid, srcgpa, &val, opsize, arg);
751 error = vm_gla2gpa(vm, vcpuid, paging, dstaddr,
752 PROT_WRITE, &dstgpa);
755 error = memwrite(vm, vcpuid, dstgpa, val, opsize, arg);
761 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSI, &rsi);
762 KASSERT(error == 0, ("%s: error %d getting rsi", __func__, error));
764 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
765 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
767 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
768 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
770 if (rflags & PSL_D) {
778 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSI, rsi,
780 KASSERT(error == 0, ("%s: error %d updating rsi", __func__, error));
782 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
784 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
788 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
790 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
793 * Repeat the instruction if the count register is not zero.
795 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
796 vm_restart_instruction(vm, vcpuid);
806 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
807 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
810 enum vm_reg_name reg;
811 uint64_t result, rflags, rflags2, val1, val2;
816 switch (vie->op.op_byte) {
819 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
822 * 23/r and r16, r/m16
823 * 23/r and r32, r/m32
824 * REX.W + 23/r and r64, r/m64
827 /* get the first operand */
828 reg = gpr_map[vie->reg];
829 error = vie_read_register(vm, vcpuid, reg, &val1);
833 /* get the second operand */
834 error = memread(vm, vcpuid, gpa, &val2, size, arg);
838 /* perform the operation and write the result */
839 result = val1 & val2;
840 error = vie_update_register(vm, vcpuid, reg, result, size);
845 * AND mem (ModRM:r/m) with immediate and store the
848 * 81 /4 and r/m16, imm16
849 * 81 /4 and r/m32, imm32
850 * REX.W + 81 /4 and r/m64, imm32 sign-extended to 64
852 * 83 /4 and r/m16, imm8 sign-extended to 16
853 * 83 /4 and r/m32, imm8 sign-extended to 32
854 * REX.W + 83/4 and r/m64, imm8 sign-extended to 64
857 /* get the first operand */
858 error = memread(vm, vcpuid, gpa, &val1, size, arg);
863 * perform the operation with the pre-fetched immediate
864 * operand and write the result
866 result = val1 & vie->immediate;
867 error = memwrite(vm, vcpuid, gpa, result, size, arg);
875 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
880 * OF and CF are cleared; the SF, ZF and PF flags are set according
881 * to the result; AF is undefined.
883 * The updated status flags are obtained by subtracting 0 from 'result'.
885 rflags2 = getcc(size, result, 0);
886 rflags &= ~RFLAGS_STATUS_BITS;
887 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
889 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
894 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
895 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
898 uint64_t val1, result, rflags, rflags2;
903 switch (vie->op.op_byte) {
907 * OR mem (ModRM:r/m) with immediate and store the
910 * 81 /1 or r/m16, imm16
911 * 81 /1 or r/m32, imm32
912 * REX.W + 81 /1 or r/m64, imm32 sign-extended to 64
914 * 83 /1 or r/m16, imm8 sign-extended to 16
915 * 83 /1 or r/m32, imm8 sign-extended to 32
916 * REX.W + 83/1 or r/m64, imm8 sign-extended to 64
919 /* get the first operand */
920 error = memread(vm, vcpuid, gpa, &val1, size, arg);
925 * perform the operation with the pre-fetched immediate
926 * operand and write the result
928 result = val1 | vie->immediate;
929 error = memwrite(vm, vcpuid, gpa, result, size, arg);
937 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
942 * OF and CF are cleared; the SF, ZF and PF flags are set according
943 * to the result; AF is undefined.
945 * The updated status flags are obtained by subtracting 0 from 'result'.
947 rflags2 = getcc(size, result, 0);
948 rflags &= ~RFLAGS_STATUS_BITS;
949 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
951 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
956 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
957 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
960 uint64_t op1, op2, rflags, rflags2;
961 enum vm_reg_name reg;
964 switch (vie->op.op_byte) {
967 * 3B/r CMP r16, r/m16
968 * 3B/r CMP r32, r/m32
969 * REX.W + 3B/r CMP r64, r/m64
971 * Compare first operand (reg) with second operand (r/m) and
972 * set status flags in EFLAGS register. The comparison is
973 * performed by subtracting the second operand from the first
974 * operand and then setting the status flags.
977 /* Get the first operand */
978 reg = gpr_map[vie->reg];
979 error = vie_read_register(vm, vcpuid, reg, &op1);
983 /* Get the second operand */
984 error = memread(vm, vcpuid, gpa, &op2, size, arg);
988 rflags2 = getcc(size, op1, op2);
993 * 81 /7 cmp r/m16, imm16
994 * 81 /7 cmp r/m32, imm32
995 * REX.W + 81 /7 cmp r/m64, imm32 sign-extended to 64
997 * 83 /7 cmp r/m16, imm8 sign-extended to 16
998 * 83 /7 cmp r/m32, imm8 sign-extended to 32
999 * REX.W + 83 /7 cmp r/m64, imm8 sign-extended to 64
1001 * Compare mem (ModRM:r/m) with immediate and set
1002 * status flags according to the results. The
1003 * comparison is performed by subtracting the
1004 * immediate from the first operand and then setting
1009 /* get the first operand */
1010 error = memread(vm, vcpuid, gpa, &op1, size, arg);
1014 rflags2 = getcc(size, op1, vie->immediate);
1019 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1022 rflags &= ~RFLAGS_STATUS_BITS;
1023 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1025 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1030 emulate_sub(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1031 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1034 uint64_t nval, rflags, rflags2, val1, val2;
1035 enum vm_reg_name reg;
1040 switch (vie->op.op_byte) {
1043 * SUB r/m from r and store the result in r
1045 * 2B/r SUB r16, r/m16
1046 * 2B/r SUB r32, r/m32
1047 * REX.W + 2B/r SUB r64, r/m64
1050 /* get the first operand */
1051 reg = gpr_map[vie->reg];
1052 error = vie_read_register(vm, vcpuid, reg, &val1);
1056 /* get the second operand */
1057 error = memread(vm, vcpuid, gpa, &val2, size, arg);
1061 /* perform the operation and write the result */
1063 error = vie_update_register(vm, vcpuid, reg, nval, size);
1070 rflags2 = getcc(size, val1, val2);
1071 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1076 rflags &= ~RFLAGS_STATUS_BITS;
1077 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1078 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1086 emulate_stack_op(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1087 struct vm_guest_paging *paging, mem_region_read_t memread,
1088 mem_region_write_t memwrite, void *arg)
1091 struct vm_copyinfo copyinfo[2];
1093 struct iovec copyinfo[2];
1095 struct seg_desc ss_desc;
1096 uint64_t cr0, rflags, rsp, stack_gla, val;
1097 int error, size, stackaddrsize, pushop;
1101 pushop = (vie->op.op_type == VIE_OP_TYPE_PUSH) ? 1 : 0;
1104 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
1106 if (paging->cpu_mode == CPU_MODE_REAL) {
1108 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
1110 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
1111 * - Stack pointer size is always 64-bits.
1112 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
1113 * - 16-bit PUSH/POP is supported by using the operand size
1114 * override prefix (66H).
1117 size = vie->opsize_override ? 2 : 8;
1120 * In protected or compability mode the 'B' flag in the
1121 * stack-segment descriptor determines the size of the
1124 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
1125 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
1127 if (SEG_DESC_DEF32(ss_desc.access))
1133 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
1134 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
1136 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1137 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1139 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
1140 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
1145 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
1146 rsp, size, stackaddrsize, pushop ? PROT_WRITE : PROT_READ,
1148 vm_inject_ss(vm, vcpuid, 0);
1152 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
1153 vm_inject_ss(vm, vcpuid, 0);
1157 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
1158 vm_inject_ac(vm, vcpuid, 0);
1162 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size,
1163 pushop ? PROT_WRITE : PROT_READ, copyinfo, nitems(copyinfo));
1166 * XXX cannot return a negative error value here because it
1167 * ends up being the return value of the VM_RUN() ioctl and
1168 * is interpreted as a pseudo-error (for e.g. ERESTART).
1171 } else if (error == 1) {
1172 /* Resume guest execution to handle page fault */
1177 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
1179 vm_copyout(vm, vcpuid, &val, copyinfo, size);
1181 vm_copyin(vm, vcpuid, copyinfo, &val, size);
1182 error = memwrite(vm, vcpuid, mmio_gpa, val, size, arg);
1185 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1188 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
1190 KASSERT(error == 0, ("error %d updating rsp", error));
1196 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1197 struct vm_guest_paging *paging, mem_region_read_t memread,
1198 mem_region_write_t memwrite, void *arg)
1203 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1205 * PUSH is part of the group 5 extended opcodes and is identified
1206 * by ModRM:reg = b110.
1208 if ((vie->reg & 7) != 6)
1211 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1217 emulate_pop(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1218 struct vm_guest_paging *paging, mem_region_read_t memread,
1219 mem_region_write_t memwrite, void *arg)
1224 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1226 * POP is part of the group 1A extended opcodes and is identified
1227 * by ModRM:reg = b000.
1229 if ((vie->reg & 7) != 0)
1232 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1238 emulate_group1(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1239 struct vm_guest_paging *paging, mem_region_read_t memread,
1240 mem_region_write_t memwrite, void *memarg)
1244 switch (vie->reg & 7) {
1246 error = emulate_or(vm, vcpuid, gpa, vie,
1247 memread, memwrite, memarg);
1250 error = emulate_and(vm, vcpuid, gpa, vie,
1251 memread, memwrite, memarg);
1254 error = emulate_cmp(vm, vcpuid, gpa, vie,
1255 memread, memwrite, memarg);
1266 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1267 struct vm_guest_paging *paging, mem_region_read_t memread,
1268 mem_region_write_t memwrite, void *memarg)
1275 switch (vie->op.op_type) {
1276 case VIE_OP_TYPE_GROUP1:
1277 error = emulate_group1(vm, vcpuid, gpa, vie, paging, memread,
1280 case VIE_OP_TYPE_POP:
1281 error = emulate_pop(vm, vcpuid, gpa, vie, paging, memread,
1284 case VIE_OP_TYPE_PUSH:
1285 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
1288 case VIE_OP_TYPE_CMP:
1289 error = emulate_cmp(vm, vcpuid, gpa, vie,
1290 memread, memwrite, memarg);
1292 case VIE_OP_TYPE_MOV:
1293 error = emulate_mov(vm, vcpuid, gpa, vie,
1294 memread, memwrite, memarg);
1296 case VIE_OP_TYPE_MOVSX:
1297 case VIE_OP_TYPE_MOVZX:
1298 error = emulate_movx(vm, vcpuid, gpa, vie,
1299 memread, memwrite, memarg);
1301 case VIE_OP_TYPE_MOVS:
1302 error = emulate_movs(vm, vcpuid, gpa, vie, paging, memread,
1305 case VIE_OP_TYPE_AND:
1306 error = emulate_and(vm, vcpuid, gpa, vie,
1307 memread, memwrite, memarg);
1309 case VIE_OP_TYPE_OR:
1310 error = emulate_or(vm, vcpuid, gpa, vie,
1311 memread, memwrite, memarg);
1313 case VIE_OP_TYPE_SUB:
1314 error = emulate_sub(vm, vcpuid, gpa, vie,
1315 memread, memwrite, memarg);
1326 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
1328 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1329 ("%s: invalid size %d", __func__, size));
1330 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
1332 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
1335 return ((gla & (size - 1)) ? 1 : 0);
1339 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
1343 if (cpu_mode != CPU_MODE_64BIT)
1347 * The value of the bit 47 in the 'gla' should be replicated in the
1348 * most significant 16 bits.
1350 mask = ~((1UL << 48) - 1);
1351 if (gla & (1UL << 47))
1352 return ((gla & mask) != mask);
1354 return ((gla & mask) != 0);
1358 vie_size2mask(int size)
1360 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1361 ("vie_size2mask: invalid size %d", size));
1362 return (size2mask[size]);
1366 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
1367 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
1368 int prot, uint64_t *gla)
1370 uint64_t firstoff, low_limit, high_limit, segbase;
1373 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
1374 ("%s: invalid segment %d", __func__, seg));
1375 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
1376 ("%s: invalid operand size %d", __func__, length));
1377 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
1378 ("%s: invalid prot %#x", __func__, prot));
1381 if (cpu_mode == CPU_MODE_64BIT) {
1382 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
1383 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
1386 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
1387 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
1390 * If the segment selector is loaded with a NULL selector
1391 * then the descriptor is unusable and attempting to use
1392 * it results in a #GP(0).
1394 if (SEG_DESC_UNUSABLE(desc->access))
1398 * The processor generates a #NP exception when a segment
1399 * register is loaded with a selector that points to a
1400 * descriptor that is not present. If this was the case then
1401 * it would have been checked before the VM-exit.
1403 KASSERT(SEG_DESC_PRESENT(desc->access),
1404 ("segment %d not present: %#x", seg, desc->access));
1407 * The descriptor type must indicate a code/data segment.
1409 type = SEG_DESC_TYPE(desc->access);
1410 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
1411 "descriptor type %#x", seg, type));
1413 if (prot & PROT_READ) {
1414 /* #GP on a read access to a exec-only code segment */
1415 if ((type & 0xA) == 0x8)
1419 if (prot & PROT_WRITE) {
1421 * #GP on a write access to a code segment or a
1422 * read-only data segment.
1424 if (type & 0x8) /* code segment */
1427 if ((type & 0xA) == 0) /* read-only data seg */
1432 * 'desc->limit' is fully expanded taking granularity into
1435 if ((type & 0xC) == 0x4) {
1436 /* expand-down data segment */
1437 low_limit = desc->limit + 1;
1438 high_limit = SEG_DESC_DEF32(desc->access) ?
1439 0xffffffff : 0xffff;
1441 /* code segment or expand-up data segment */
1443 high_limit = desc->limit;
1446 while (length > 0) {
1447 offset &= vie_size2mask(addrsize);
1448 if (offset < low_limit || offset > high_limit)
1456 * In 64-bit mode all segments except %fs and %gs have a segment
1457 * base address of 0.
1459 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1460 seg != VM_REG_GUEST_GS) {
1463 segbase = desc->base;
1467 * Truncate 'firstoff' to the effective address size before adding
1468 * it to the segment base.
1470 firstoff &= vie_size2mask(addrsize);
1471 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1477 vie_init(struct vie *vie, const char *inst_bytes, int inst_length)
1479 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE,
1480 ("%s: invalid instruction length (%d)", __func__, inst_length));
1482 bzero(vie, sizeof(struct vie));
1484 vie->base_register = VM_REG_LAST;
1485 vie->index_register = VM_REG_LAST;
1486 vie->segment_register = VM_REG_LAST;
1489 bcopy(inst_bytes, vie->inst, inst_length);
1490 vie->num_valid = inst_length;
1495 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1500 error_code |= PGEX_P;
1501 if (prot & VM_PROT_WRITE)
1502 error_code |= PGEX_W;
1504 error_code |= PGEX_U;
1506 error_code |= PGEX_RSV;
1507 if (prot & VM_PROT_EXECUTE)
1508 error_code |= PGEX_I;
1510 return (error_code);
1514 ptp_release(void **cookie)
1516 if (*cookie != NULL) {
1517 vm_gpa_release(*cookie);
1523 ptp_hold(struct vm *vm, vm_paddr_t ptpphys, size_t len, void **cookie)
1527 ptp_release(cookie);
1528 ptr = vm_gpa_hold(vm, ptpphys, len, VM_PROT_RW, cookie);
1533 vm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1534 uint64_t gla, int prot, uint64_t *gpa)
1536 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1538 uint64_t *ptpbase, ptpphys, pte, pgsize;
1539 uint32_t *ptpbase32, pte32;
1542 usermode = (paging->cpl == 3 ? 1 : 0);
1543 writable = prot & VM_PROT_WRITE;
1548 ptpphys = paging->cr3; /* root of the page tables */
1549 ptp_release(&cookie);
1553 if (vie_canonical_check(paging->cpu_mode, gla)) {
1555 * XXX assuming a non-stack reference otherwise a stack fault
1556 * should be generated.
1558 vm_inject_gp(vm, vcpuid);
1562 if (paging->paging_mode == PAGING_MODE_FLAT) {
1567 if (paging->paging_mode == PAGING_MODE_32) {
1569 while (--nlevels >= 0) {
1570 /* Zero out the lower 12 bits. */
1573 ptpbase32 = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1575 if (ptpbase32 == NULL)
1578 ptpshift = PAGE_SHIFT + nlevels * 10;
1579 ptpindex = (gla >> ptpshift) & 0x3FF;
1580 pgsize = 1UL << ptpshift;
1582 pte32 = ptpbase32[ptpindex];
1584 if ((pte32 & PG_V) == 0 ||
1585 (usermode && (pte32 & PG_U) == 0) ||
1586 (writable && (pte32 & PG_RW) == 0)) {
1587 pfcode = pf_error_code(usermode, prot, 0,
1589 vm_inject_pf(vm, vcpuid, pfcode, gla);
1594 * Emulate the x86 MMU's management of the accessed
1595 * and dirty flags. While the accessed flag is set
1596 * at every level of the page table, the dirty flag
1597 * is only set at the last level providing the guest
1600 if ((pte32 & PG_A) == 0) {
1601 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1602 pte32, pte32 | PG_A) == 0) {
1607 /* XXX must be ignored if CR4.PSE=0 */
1608 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1614 /* Set the dirty bit in the page table entry if necessary */
1615 if (writable && (pte32 & PG_M) == 0) {
1616 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1617 pte32, pte32 | PG_M) == 0) {
1622 /* Zero out the lower 'ptpshift' bits */
1623 pte32 >>= ptpshift; pte32 <<= ptpshift;
1624 *gpa = pte32 | (gla & (pgsize - 1));
1628 if (paging->paging_mode == PAGING_MODE_PAE) {
1629 /* Zero out the lower 5 bits and the upper 32 bits */
1630 ptpphys &= 0xffffffe0UL;
1632 ptpbase = ptp_hold(vm, ptpphys, sizeof(*ptpbase) * 4, &cookie);
1633 if (ptpbase == NULL)
1636 ptpindex = (gla >> 30) & 0x3;
1638 pte = ptpbase[ptpindex];
1640 if ((pte & PG_V) == 0) {
1641 pfcode = pf_error_code(usermode, prot, 0, pte);
1642 vm_inject_pf(vm, vcpuid, pfcode, gla);
1651 while (--nlevels >= 0) {
1652 /* Zero out the lower 12 bits and the upper 12 bits */
1653 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1655 ptpbase = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1656 if (ptpbase == NULL)
1659 ptpshift = PAGE_SHIFT + nlevels * 9;
1660 ptpindex = (gla >> ptpshift) & 0x1FF;
1661 pgsize = 1UL << ptpshift;
1663 pte = ptpbase[ptpindex];
1665 if ((pte & PG_V) == 0 ||
1666 (usermode && (pte & PG_U) == 0) ||
1667 (writable && (pte & PG_RW) == 0)) {
1668 pfcode = pf_error_code(usermode, prot, 0, pte);
1669 vm_inject_pf(vm, vcpuid, pfcode, gla);
1673 /* Set the accessed bit in the page table entry */
1674 if ((pte & PG_A) == 0) {
1675 if (atomic_cmpset_64(&ptpbase[ptpindex],
1676 pte, pte | PG_A) == 0) {
1681 if (nlevels > 0 && (pte & PG_PS) != 0) {
1682 if (pgsize > 1 * GB) {
1683 pfcode = pf_error_code(usermode, prot, 1, pte);
1684 vm_inject_pf(vm, vcpuid, pfcode, gla);
1693 /* Set the dirty bit in the page table entry if necessary */
1694 if (writable && (pte & PG_M) == 0) {
1695 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1699 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1700 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1701 *gpa = pte | (gla & (pgsize - 1));
1703 ptp_release(&cookie);
1714 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1715 uint64_t rip, int inst_length, struct vie *vie)
1717 struct vm_copyinfo copyinfo[2];
1720 if (inst_length > VIE_INST_SIZE)
1721 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1723 prot = PROT_READ | PROT_EXEC;
1724 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1725 copyinfo, nitems(copyinfo));
1727 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1728 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1729 vie->num_valid = inst_length;
1735 vie_peek(struct vie *vie, uint8_t *x)
1738 if (vie->num_processed < vie->num_valid) {
1739 *x = vie->inst[vie->num_processed];
1746 vie_advance(struct vie *vie)
1749 vie->num_processed++;
1753 segment_override(uint8_t x, int *seg)
1758 *seg = VM_REG_GUEST_CS;
1761 *seg = VM_REG_GUEST_SS;
1764 *seg = VM_REG_GUEST_DS;
1767 *seg = VM_REG_GUEST_ES;
1770 *seg = VM_REG_GUEST_FS;
1773 *seg = VM_REG_GUEST_GS;
1782 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
1787 if (vie_peek(vie, &x))
1791 vie->opsize_override = 1;
1793 vie->addrsize_override = 1;
1795 vie->repz_present = 1;
1797 vie->repnz_present = 1;
1798 else if (segment_override(x, &vie->segment_register))
1799 vie->segment_override = 1;
1807 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
1808 * - Only one REX prefix is allowed per instruction.
1809 * - The REX prefix must immediately precede the opcode byte or the
1810 * escape opcode byte.
1811 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
1812 * the mandatory prefix must come before the REX prefix.
1814 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
1815 vie->rex_present = 1;
1816 vie->rex_w = x & 0x8 ? 1 : 0;
1817 vie->rex_r = x & 0x4 ? 1 : 0;
1818 vie->rex_x = x & 0x2 ? 1 : 0;
1819 vie->rex_b = x & 0x1 ? 1 : 0;
1824 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
1826 if (cpu_mode == CPU_MODE_64BIT) {
1828 * Default address size is 64-bits and default operand size
1831 vie->addrsize = vie->addrsize_override ? 4 : 8;
1834 else if (vie->opsize_override)
1839 /* Default address and operand sizes are 32-bits */
1840 vie->addrsize = vie->addrsize_override ? 2 : 4;
1841 vie->opsize = vie->opsize_override ? 2 : 4;
1843 /* Default address and operand sizes are 16-bits */
1844 vie->addrsize = vie->addrsize_override ? 4 : 2;
1845 vie->opsize = vie->opsize_override ? 4 : 2;
1851 decode_two_byte_opcode(struct vie *vie)
1855 if (vie_peek(vie, &x))
1858 vie->op = two_byte_opcodes[x];
1860 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1868 decode_opcode(struct vie *vie)
1872 if (vie_peek(vie, &x))
1875 vie->op = one_byte_opcodes[x];
1877 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1882 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
1883 return (decode_two_byte_opcode(vie));
1889 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
1893 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
1896 if (cpu_mode == CPU_MODE_REAL)
1899 if (vie_peek(vie, &x))
1902 vie->mod = (x >> 6) & 0x3;
1903 vie->rm = (x >> 0) & 0x7;
1904 vie->reg = (x >> 3) & 0x7;
1907 * A direct addressing mode makes no sense in the context of an EPT
1908 * fault. There has to be a memory access involved to cause the
1911 if (vie->mod == VIE_MOD_DIRECT)
1914 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
1915 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
1917 * Table 2-5: Special Cases of REX Encodings
1919 * mod=0, r/m=5 is used in the compatibility mode to
1920 * indicate a disp32 without a base register.
1922 * mod!=3, r/m=4 is used in the compatibility mode to
1923 * indicate that the SIB byte is present.
1925 * The 'b' bit in the REX prefix is don't care in
1929 vie->rm |= (vie->rex_b << 3);
1932 vie->reg |= (vie->rex_r << 3);
1935 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
1938 vie->base_register = gpr_map[vie->rm];
1941 case VIE_MOD_INDIRECT_DISP8:
1942 vie->disp_bytes = 1;
1944 case VIE_MOD_INDIRECT_DISP32:
1945 vie->disp_bytes = 4;
1947 case VIE_MOD_INDIRECT:
1948 if (vie->rm == VIE_RM_DISP32) {
1949 vie->disp_bytes = 4;
1951 * Table 2-7. RIP-Relative Addressing
1953 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
1954 * whereas in compatibility mode it just implies disp32.
1957 if (cpu_mode == CPU_MODE_64BIT)
1958 vie->base_register = VM_REG_GUEST_RIP;
1960 vie->base_register = VM_REG_LAST;
1972 decode_sib(struct vie *vie)
1976 /* Proceed only if SIB byte is present */
1977 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
1980 if (vie_peek(vie, &x))
1983 /* De-construct the SIB byte */
1984 vie->ss = (x >> 6) & 0x3;
1985 vie->index = (x >> 3) & 0x7;
1986 vie->base = (x >> 0) & 0x7;
1988 /* Apply the REX prefix modifiers */
1989 vie->index |= vie->rex_x << 3;
1990 vie->base |= vie->rex_b << 3;
1993 case VIE_MOD_INDIRECT_DISP8:
1994 vie->disp_bytes = 1;
1996 case VIE_MOD_INDIRECT_DISP32:
1997 vie->disp_bytes = 4;
2001 if (vie->mod == VIE_MOD_INDIRECT &&
2002 (vie->base == 5 || vie->base == 13)) {
2004 * Special case when base register is unused if mod = 0
2005 * and base = %rbp or %r13.
2008 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2009 * Table 2-5: Special Cases of REX Encodings
2011 vie->disp_bytes = 4;
2013 vie->base_register = gpr_map[vie->base];
2017 * All encodings of 'index' are valid except for %rsp (4).
2020 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2021 * Table 2-5: Special Cases of REX Encodings
2023 if (vie->index != 4)
2024 vie->index_register = gpr_map[vie->index];
2026 /* 'scale' makes sense only in the context of an index register */
2027 if (vie->index_register < VM_REG_LAST)
2028 vie->scale = 1 << vie->ss;
2036 decode_displacement(struct vie *vie)
2047 if ((n = vie->disp_bytes) == 0)
2050 if (n != 1 && n != 4)
2051 panic("decode_displacement: invalid disp_bytes %d", n);
2053 for (i = 0; i < n; i++) {
2054 if (vie_peek(vie, &x))
2062 vie->displacement = u.signed8; /* sign-extended */
2064 vie->displacement = u.signed32; /* sign-extended */
2070 decode_immediate(struct vie *vie)
2081 /* Figure out immediate operand size (if any) */
2082 if (vie->op.op_flags & VIE_OP_F_IMM) {
2084 * Section 2.2.1.5 "Immediates", Intel SDM:
2085 * In 64-bit mode the typical size of immediate operands
2086 * remains 32-bits. When the operand size if 64-bits, the
2087 * processor sign-extends all immediates to 64-bits prior
2090 if (vie->opsize == 4 || vie->opsize == 8)
2094 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
2098 if ((n = vie->imm_bytes) == 0)
2101 KASSERT(n == 1 || n == 2 || n == 4,
2102 ("%s: invalid number of immediate bytes: %d", __func__, n));
2104 for (i = 0; i < n; i++) {
2105 if (vie_peek(vie, &x))
2112 /* sign-extend the immediate value before use */
2114 vie->immediate = u.signed8;
2116 vie->immediate = u.signed16;
2118 vie->immediate = u.signed32;
2124 decode_moffset(struct vie *vie)
2133 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
2137 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
2138 * The memory offset size follows the address-size of the instruction.
2141 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
2144 for (i = 0; i < n; i++) {
2145 if (vie_peek(vie, &x))
2151 vie->displacement = u.u64;
2156 * Verify that all the bytes in the instruction buffer were consumed.
2159 verify_inst_length(struct vie *vie)
2162 if (vie->num_processed)
2169 * Verify that the 'guest linear address' provided as collateral of the nested
2170 * page table fault matches with our instruction decoding.
2173 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
2176 uint64_t base, idx, gla2;
2178 /* Skip 'gla' verification */
2179 if (gla == VIE_INVALID_GLA)
2183 if (vie->base_register != VM_REG_LAST) {
2184 error = vm_get_register(vm, cpuid, vie->base_register, &base);
2186 printf("verify_gla: error %d getting base reg %d\n",
2187 error, vie->base_register);
2192 * RIP-relative addressing starts from the following
2195 if (vie->base_register == VM_REG_GUEST_RIP)
2196 base += vie->num_valid;
2200 if (vie->index_register != VM_REG_LAST) {
2201 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
2203 printf("verify_gla: error %d getting index reg %d\n",
2204 error, vie->index_register);
2209 /* XXX assuming that the base address of the segment is 0 */
2210 gla2 = base + vie->scale * idx + vie->displacement;
2211 gla2 &= size2mask[vie->addrsize];
2213 printf("verify_gla mismatch: "
2214 "base(0x%0lx), scale(%d), index(0x%0lx), "
2215 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
2216 base, vie->scale, idx, vie->displacement, gla, gla2);
2224 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
2225 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
2228 if (decode_prefixes(vie, cpu_mode, cs_d))
2231 if (decode_opcode(vie))
2234 if (decode_modrm(vie, cpu_mode))
2237 if (decode_sib(vie))
2240 if (decode_displacement(vie))
2243 if (decode_immediate(vie))
2246 if (decode_moffset(vie))
2249 if (verify_inst_length(vie))
2252 if ((vie->op.op_flags & VIE_OP_F_NO_GLA_VERIFICATION) == 0) {
2253 if (verify_gla(vm, cpuid, gla, vie))
2257 vie->decoded = 1; /* success */
2261 #endif /* _KERNEL */