2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
47 #include <sys/_iovec.h>
49 #include <machine/vmm.h>
53 #define KASSERT(exp,msg) assert((exp))
56 #include <machine/vmm_instruction_emul.h>
58 #include <x86/specialreg.h>
60 /* struct vie_op.op_type */
80 /* struct vie_op.op_flags */
81 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
82 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
83 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
84 #define VIE_OP_F_NO_MODRM (1 << 3)
85 #define VIE_OP_F_NO_GLA_VERIFICATION (1 << 4)
87 static const struct vie_op two_byte_opcodes[256] = {
90 .op_type = VIE_OP_TYPE_MOVZX,
94 .op_type = VIE_OP_TYPE_MOVZX,
98 .op_type = VIE_OP_TYPE_BITTEST,
99 .op_flags = VIE_OP_F_IMM8,
103 .op_type = VIE_OP_TYPE_MOVSX,
107 static const struct vie_op one_byte_opcodes[256] = {
110 .op_type = VIE_OP_TYPE_TWO_BYTE
114 .op_type = VIE_OP_TYPE_SUB,
118 .op_type = VIE_OP_TYPE_CMP,
122 .op_type = VIE_OP_TYPE_CMP,
126 .op_type = VIE_OP_TYPE_MOV,
130 .op_type = VIE_OP_TYPE_MOV,
134 .op_type = VIE_OP_TYPE_MOV,
138 .op_type = VIE_OP_TYPE_MOV,
142 .op_type = VIE_OP_TYPE_MOV,
143 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
147 .op_type = VIE_OP_TYPE_MOV,
148 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
152 .op_type = VIE_OP_TYPE_MOVS,
153 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
157 .op_type = VIE_OP_TYPE_MOVS,
158 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
162 .op_type = VIE_OP_TYPE_STOS,
163 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
167 .op_type = VIE_OP_TYPE_STOS,
168 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
171 /* XXX Group 11 extended opcode - not just MOV */
173 .op_type = VIE_OP_TYPE_MOV,
174 .op_flags = VIE_OP_F_IMM8,
178 .op_type = VIE_OP_TYPE_MOV,
179 .op_flags = VIE_OP_F_IMM,
183 .op_type = VIE_OP_TYPE_AND,
186 /* Group 1 extended opcode */
188 .op_type = VIE_OP_TYPE_GROUP1,
189 .op_flags = VIE_OP_F_IMM8,
192 /* Group 1 extended opcode */
194 .op_type = VIE_OP_TYPE_GROUP1,
195 .op_flags = VIE_OP_F_IMM,
198 /* Group 1 extended opcode */
200 .op_type = VIE_OP_TYPE_GROUP1,
201 .op_flags = VIE_OP_F_IMM8,
204 /* XXX Group 1A extended opcode - not just POP */
206 .op_type = VIE_OP_TYPE_POP,
209 /* XXX Group 5 extended opcode - not just PUSH */
211 .op_type = VIE_OP_TYPE_PUSH,
216 #define VIE_MOD_INDIRECT 0
217 #define VIE_MOD_INDIRECT_DISP8 1
218 #define VIE_MOD_INDIRECT_DISP32 2
219 #define VIE_MOD_DIRECT 3
223 #define VIE_RM_DISP32 5
225 #define GB (1024 * 1024 * 1024)
227 static enum vm_reg_name gpr_map[16] = {
246 static uint64_t size2mask[] = {
250 [8] = 0xffffffffffffffff,
254 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
258 error = vm_get_register(vm, vcpuid, reg, rval);
264 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
267 *reg = gpr_map[vie->reg];
270 * 64-bit mode imposes limitations on accessing legacy high byte
273 * The legacy high-byte registers cannot be addressed if the REX
274 * prefix is present. In this case the values 4, 5, 6 and 7 of the
275 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
277 * If the REX prefix is not present then the values 4, 5, 6 and 7
278 * of the 'ModRM:reg' field address the legacy high-byte registers,
279 * %ah, %ch, %dh and %bh respectively.
281 if (!vie->rex_present) {
282 if (vie->reg & 0x4) {
284 *reg = gpr_map[vie->reg & 0x3];
290 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
294 enum vm_reg_name reg;
296 vie_calc_bytereg(vie, ®, &lhbr);
297 error = vm_get_register(vm, vcpuid, reg, &val);
300 * To obtain the value of a legacy high byte register shift the
301 * base register right by 8 bits (%ah = %rax >> 8).
311 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
313 uint64_t origval, val, mask;
315 enum vm_reg_name reg;
317 vie_calc_bytereg(vie, ®, &lhbr);
318 error = vm_get_register(vm, vcpuid, reg, &origval);
324 * Shift left by 8 to store 'byte' in a legacy high
330 val |= origval & ~mask;
331 error = vm_set_register(vm, vcpuid, reg, val);
337 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
338 uint64_t val, int size)
346 error = vie_read_register(vm, vcpuid, reg, &origval);
349 val &= size2mask[size];
350 val |= origval & ~size2mask[size];
361 error = vm_set_register(vm, vcpuid, reg, val);
365 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
368 * Return the status flags that would result from doing (x - y).
372 getcc##sz(uint##sz##_t x, uint##sz##_t y) \
376 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
377 "=r" (rflags), "+r" (x) : "m" (y)); \
387 getcc(int opsize, uint64_t x, uint64_t y)
389 KASSERT(opsize == 1 || opsize == 2 || opsize == 4 || opsize == 8,
390 ("getcc: invalid operand size %d", opsize));
393 return (getcc8(x, y));
394 else if (opsize == 2)
395 return (getcc16(x, y));
396 else if (opsize == 4)
397 return (getcc32(x, y));
399 return (getcc64(x, y));
403 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
404 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
407 enum vm_reg_name reg;
414 switch (vie->op.op_byte) {
417 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
419 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
421 size = 1; /* override for byte operation */
422 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
424 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
428 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
429 * 89/r: mov r/m16, r16
430 * 89/r: mov r/m32, r32
431 * REX.W + 89/r mov r/m64, r64
433 reg = gpr_map[vie->reg];
434 error = vie_read_register(vm, vcpuid, reg, &val);
436 val &= size2mask[size];
437 error = memwrite(vm, vcpuid, gpa, val, size, arg);
442 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
444 * REX + 8A/r: mov r8, r/m8
446 size = 1; /* override for byte operation */
447 error = memread(vm, vcpuid, gpa, &val, size, arg);
449 error = vie_write_bytereg(vm, vcpuid, vie, val);
453 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
454 * 8B/r: mov r16, r/m16
455 * 8B/r: mov r32, r/m32
456 * REX.W 8B/r: mov r64, r/m64
458 error = memread(vm, vcpuid, gpa, &val, size, arg);
460 reg = gpr_map[vie->reg];
461 error = vie_update_register(vm, vcpuid, reg, val, size);
466 * MOV from seg:moffset to AX/EAX/RAX
467 * A1: mov AX, moffs16
468 * A1: mov EAX, moffs32
469 * REX.W + A1: mov RAX, moffs64
471 error = memread(vm, vcpuid, gpa, &val, size, arg);
473 reg = VM_REG_GUEST_RAX;
474 error = vie_update_register(vm, vcpuid, reg, val, size);
479 * MOV from AX/EAX/RAX to seg:moffset
480 * A3: mov moffs16, AX
481 * A3: mov moffs32, EAX
482 * REX.W + A3: mov moffs64, RAX
484 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
486 val &= size2mask[size];
487 error = memwrite(vm, vcpuid, gpa, val, size, arg);
492 * MOV from imm8 to mem (ModRM:r/m)
493 * C6/0 mov r/m8, imm8
494 * REX + C6/0 mov r/m8, imm8
496 size = 1; /* override for byte operation */
497 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
501 * MOV from imm16/imm32 to mem (ModRM:r/m)
502 * C7/0 mov r/m16, imm16
503 * C7/0 mov r/m32, imm32
504 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
506 val = vie->immediate & size2mask[size];
507 error = memwrite(vm, vcpuid, gpa, val, size, arg);
517 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
518 mem_region_read_t memread, mem_region_write_t memwrite,
522 enum vm_reg_name reg;
528 switch (vie->op.op_byte) {
531 * MOV and zero extend byte from mem (ModRM:r/m) to
534 * 0F B6/r movzx r16, r/m8
535 * 0F B6/r movzx r32, r/m8
536 * REX.W + 0F B6/r movzx r64, r/m8
539 /* get the first operand */
540 error = memread(vm, vcpuid, gpa, &val, 1, arg);
544 /* get the second operand */
545 reg = gpr_map[vie->reg];
547 /* zero-extend byte */
550 /* write the result */
551 error = vie_update_register(vm, vcpuid, reg, val, size);
555 * MOV and zero extend word from mem (ModRM:r/m) to
558 * 0F B7/r movzx r32, r/m16
559 * REX.W + 0F B7/r movzx r64, r/m16
561 error = memread(vm, vcpuid, gpa, &val, 2, arg);
565 reg = gpr_map[vie->reg];
567 /* zero-extend word */
570 error = vie_update_register(vm, vcpuid, reg, val, size);
574 * MOV and sign extend byte from mem (ModRM:r/m) to
577 * 0F BE/r movsx r16, r/m8
578 * 0F BE/r movsx r32, r/m8
579 * REX.W + 0F BE/r movsx r64, r/m8
582 /* get the first operand */
583 error = memread(vm, vcpuid, gpa, &val, 1, arg);
587 /* get the second operand */
588 reg = gpr_map[vie->reg];
590 /* sign extend byte */
593 /* write the result */
594 error = vie_update_register(vm, vcpuid, reg, val, size);
603 * Helper function to calculate and validate a linear address.
606 get_gla(void *vm, int vcpuid, struct vie *vie, struct vm_guest_paging *paging,
607 int opsize, int addrsize, int prot, enum vm_reg_name seg,
608 enum vm_reg_name gpr, uint64_t *gla, int *fault)
610 struct seg_desc desc;
611 uint64_t cr0, val, rflags;
614 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
615 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
617 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
618 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
620 error = vm_get_seg_desc(vm, vcpuid, seg, &desc);
621 KASSERT(error == 0, ("%s: error %d getting segment descriptor %d",
622 __func__, error, seg));
624 error = vie_read_register(vm, vcpuid, gpr, &val);
625 KASSERT(error == 0, ("%s: error %d getting register %d", __func__,
628 if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize,
629 addrsize, prot, gla)) {
630 if (seg == VM_REG_GUEST_SS)
631 vm_inject_ss(vm, vcpuid, 0);
633 vm_inject_gp(vm, vcpuid);
637 if (vie_canonical_check(paging->cpu_mode, *gla)) {
638 if (seg == VM_REG_GUEST_SS)
639 vm_inject_ss(vm, vcpuid, 0);
641 vm_inject_gp(vm, vcpuid);
645 if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) {
646 vm_inject_ac(vm, vcpuid, 0);
659 emulate_movs(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
660 struct vm_guest_paging *paging, mem_region_read_t memread,
661 mem_region_write_t memwrite, void *arg)
664 struct vm_copyinfo copyinfo[2];
666 struct iovec copyinfo[2];
668 uint64_t dstaddr, srcaddr, dstgpa, srcgpa, val;
669 uint64_t rcx, rdi, rsi, rflags;
670 int error, fault, opsize, seg, repeat;
672 opsize = (vie->op.op_byte == 0xA4) ? 1 : vie->opsize;
677 * XXX although the MOVS instruction is only supposed to be used with
678 * the "rep" prefix some guests like FreeBSD will use "repnz" instead.
680 * Empirically the "repnz" prefix has identical behavior to "rep"
681 * and the zero flag does not make a difference.
683 repeat = vie->repz_present | vie->repnz_present;
686 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
687 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
690 * The count register is %rcx, %ecx or %cx depending on the
691 * address size of the instruction.
693 if ((rcx & vie_size2mask(vie->addrsize)) == 0) {
700 * Source Destination Comments
701 * --------------------------------------------
702 * (1) memory memory n/a
703 * (2) memory mmio emulated
704 * (3) mmio memory emulated
705 * (4) mmio mmio emulated
707 * At this point we don't have sufficient information to distinguish
708 * between (2), (3) and (4). We use 'vm_copy_setup()' to tease this
709 * out because it will succeed only when operating on regular memory.
711 * XXX the emulation doesn't properly handle the case where 'gpa'
712 * is straddling the boundary between the normal memory and MMIO.
715 seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS;
716 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
717 PROT_READ, seg, VM_REG_GUEST_RSI, &srcaddr, &fault);
721 error = vm_copy_setup(vm, vcpuid, paging, srcaddr, opsize, PROT_READ,
722 copyinfo, nitems(copyinfo), &fault);
725 goto done; /* Resume guest to handle fault */
728 * case (2): read from system memory and write to mmio.
730 vm_copyin(vm, vcpuid, copyinfo, &val, opsize);
731 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
732 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
737 * 'vm_copy_setup()' is expected to fail for cases (3) and (4)
738 * if 'srcaddr' is in the mmio space.
741 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
742 PROT_WRITE, VM_REG_GUEST_ES, VM_REG_GUEST_RDI, &dstaddr,
747 error = vm_copy_setup(vm, vcpuid, paging, dstaddr, opsize,
748 PROT_WRITE, copyinfo, nitems(copyinfo), &fault);
751 goto done; /* Resume guest to handle fault */
754 * case (3): read from MMIO and write to system memory.
756 * A MMIO read can have side-effects so we
757 * commit to it only after vm_copy_setup() is
758 * successful. If a page-fault needs to be
759 * injected into the guest then it will happen
760 * before the MMIO read is attempted.
762 error = memread(vm, vcpuid, gpa, &val, opsize, arg);
766 vm_copyout(vm, vcpuid, &val, copyinfo, opsize);
767 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
770 * Case (4): read from and write to mmio.
772 * Commit to the MMIO read/write (with potential
773 * side-effects) only after we are sure that the
774 * instruction is not going to be restarted due
775 * to address translation faults.
777 error = vm_gla2gpa(vm, vcpuid, paging, srcaddr,
778 PROT_READ, &srcgpa, &fault);
782 error = vm_gla2gpa(vm, vcpuid, paging, dstaddr,
783 PROT_WRITE, &dstgpa, &fault);
787 error = memread(vm, vcpuid, srcgpa, &val, opsize, arg);
791 error = memwrite(vm, vcpuid, dstgpa, val, opsize, arg);
797 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSI, &rsi);
798 KASSERT(error == 0, ("%s: error %d getting rsi", __func__, error));
800 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
801 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
803 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
804 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
806 if (rflags & PSL_D) {
814 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSI, rsi,
816 KASSERT(error == 0, ("%s: error %d updating rsi", __func__, error));
818 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
820 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
824 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
826 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
829 * Repeat the instruction if the count register is not zero.
831 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
832 vm_restart_instruction(vm, vcpuid);
835 KASSERT(error == 0 || error == EFAULT, ("%s: unexpected error %d",
841 emulate_stos(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
842 struct vm_guest_paging *paging, mem_region_read_t memread,
843 mem_region_write_t memwrite, void *arg)
845 int error, opsize, repeat;
847 uint64_t rcx, rdi, rflags;
849 opsize = (vie->op.op_byte == 0xAA) ? 1 : vie->opsize;
850 repeat = vie->repz_present | vie->repnz_present;
853 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
854 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
857 * The count register is %rcx, %ecx or %cx depending on the
858 * address size of the instruction.
860 if ((rcx & vie_size2mask(vie->addrsize)) == 0)
864 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
865 KASSERT(!error, ("%s: error %d getting rax", __func__, error));
867 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
871 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
872 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
874 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
875 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
882 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
884 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
888 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
890 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
893 * Repeat the instruction if the count register is not zero.
895 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
896 vm_restart_instruction(vm, vcpuid);
903 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
904 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
907 enum vm_reg_name reg;
908 uint64_t result, rflags, rflags2, val1, val2;
913 switch (vie->op.op_byte) {
916 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
919 * 23/r and r16, r/m16
920 * 23/r and r32, r/m32
921 * REX.W + 23/r and r64, r/m64
924 /* get the first operand */
925 reg = gpr_map[vie->reg];
926 error = vie_read_register(vm, vcpuid, reg, &val1);
930 /* get the second operand */
931 error = memread(vm, vcpuid, gpa, &val2, size, arg);
935 /* perform the operation and write the result */
936 result = val1 & val2;
937 error = vie_update_register(vm, vcpuid, reg, result, size);
942 * AND mem (ModRM:r/m) with immediate and store the
945 * 81 /4 and r/m16, imm16
946 * 81 /4 and r/m32, imm32
947 * REX.W + 81 /4 and r/m64, imm32 sign-extended to 64
949 * 83 /4 and r/m16, imm8 sign-extended to 16
950 * 83 /4 and r/m32, imm8 sign-extended to 32
951 * REX.W + 83/4 and r/m64, imm8 sign-extended to 64
954 /* get the first operand */
955 error = memread(vm, vcpuid, gpa, &val1, size, arg);
960 * perform the operation with the pre-fetched immediate
961 * operand and write the result
963 result = val1 & vie->immediate;
964 error = memwrite(vm, vcpuid, gpa, result, size, arg);
972 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
977 * OF and CF are cleared; the SF, ZF and PF flags are set according
978 * to the result; AF is undefined.
980 * The updated status flags are obtained by subtracting 0 from 'result'.
982 rflags2 = getcc(size, result, 0);
983 rflags &= ~RFLAGS_STATUS_BITS;
984 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
986 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
991 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
992 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
995 uint64_t val1, result, rflags, rflags2;
1000 switch (vie->op.op_byte) {
1004 * OR mem (ModRM:r/m) with immediate and store the
1007 * 81 /1 or r/m16, imm16
1008 * 81 /1 or r/m32, imm32
1009 * REX.W + 81 /1 or r/m64, imm32 sign-extended to 64
1011 * 83 /1 or r/m16, imm8 sign-extended to 16
1012 * 83 /1 or r/m32, imm8 sign-extended to 32
1013 * REX.W + 83/1 or r/m64, imm8 sign-extended to 64
1016 /* get the first operand */
1017 error = memread(vm, vcpuid, gpa, &val1, size, arg);
1022 * perform the operation with the pre-fetched immediate
1023 * operand and write the result
1025 result = val1 | vie->immediate;
1026 error = memwrite(vm, vcpuid, gpa, result, size, arg);
1034 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1039 * OF and CF are cleared; the SF, ZF and PF flags are set according
1040 * to the result; AF is undefined.
1042 * The updated status flags are obtained by subtracting 0 from 'result'.
1044 rflags2 = getcc(size, result, 0);
1045 rflags &= ~RFLAGS_STATUS_BITS;
1046 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
1048 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1053 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1054 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1057 uint64_t regop, memop, op1, op2, rflags, rflags2;
1058 enum vm_reg_name reg;
1061 switch (vie->op.op_byte) {
1065 * 39/r CMP r/m16, r16
1066 * 39/r CMP r/m32, r32
1067 * REX.W 39/r CMP r/m64, r64
1069 * 3B/r CMP r16, r/m16
1070 * 3B/r CMP r32, r/m32
1071 * REX.W + 3B/r CMP r64, r/m64
1073 * Compare the first operand with the second operand and
1074 * set status flags in EFLAGS register. The comparison is
1075 * performed by subtracting the second operand from the first
1076 * operand and then setting the status flags.
1079 /* Get the register operand */
1080 reg = gpr_map[vie->reg];
1081 error = vie_read_register(vm, vcpuid, reg, ®op);
1085 /* Get the memory operand */
1086 error = memread(vm, vcpuid, gpa, &memop, size, arg);
1090 if (vie->op.op_byte == 0x3B) {
1097 rflags2 = getcc(size, op1, op2);
1103 * 80 /7 cmp r/m8, imm8
1104 * REX + 80 /7 cmp r/m8, imm8
1106 * 81 /7 cmp r/m16, imm16
1107 * 81 /7 cmp r/m32, imm32
1108 * REX.W + 81 /7 cmp r/m64, imm32 sign-extended to 64
1110 * 83 /7 cmp r/m16, imm8 sign-extended to 16
1111 * 83 /7 cmp r/m32, imm8 sign-extended to 32
1112 * REX.W + 83 /7 cmp r/m64, imm8 sign-extended to 64
1114 * Compare mem (ModRM:r/m) with immediate and set
1115 * status flags according to the results. The
1116 * comparison is performed by subtracting the
1117 * immediate from the first operand and then setting
1121 if (vie->op.op_byte == 0x80)
1124 /* get the first operand */
1125 error = memread(vm, vcpuid, gpa, &op1, size, arg);
1129 rflags2 = getcc(size, op1, vie->immediate);
1134 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1137 rflags &= ~RFLAGS_STATUS_BITS;
1138 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1140 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1145 emulate_sub(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1146 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1149 uint64_t nval, rflags, rflags2, val1, val2;
1150 enum vm_reg_name reg;
1155 switch (vie->op.op_byte) {
1158 * SUB r/m from r and store the result in r
1160 * 2B/r SUB r16, r/m16
1161 * 2B/r SUB r32, r/m32
1162 * REX.W + 2B/r SUB r64, r/m64
1165 /* get the first operand */
1166 reg = gpr_map[vie->reg];
1167 error = vie_read_register(vm, vcpuid, reg, &val1);
1171 /* get the second operand */
1172 error = memread(vm, vcpuid, gpa, &val2, size, arg);
1176 /* perform the operation and write the result */
1178 error = vie_update_register(vm, vcpuid, reg, nval, size);
1185 rflags2 = getcc(size, val1, val2);
1186 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1191 rflags &= ~RFLAGS_STATUS_BITS;
1192 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1193 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1201 emulate_stack_op(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1202 struct vm_guest_paging *paging, mem_region_read_t memread,
1203 mem_region_write_t memwrite, void *arg)
1206 struct vm_copyinfo copyinfo[2];
1208 struct iovec copyinfo[2];
1210 struct seg_desc ss_desc;
1211 uint64_t cr0, rflags, rsp, stack_gla, val;
1212 int error, fault, size, stackaddrsize, pushop;
1216 pushop = (vie->op.op_type == VIE_OP_TYPE_PUSH) ? 1 : 0;
1219 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
1221 if (paging->cpu_mode == CPU_MODE_REAL) {
1223 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
1225 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
1226 * - Stack pointer size is always 64-bits.
1227 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
1228 * - 16-bit PUSH/POP is supported by using the operand size
1229 * override prefix (66H).
1232 size = vie->opsize_override ? 2 : 8;
1235 * In protected or compatibility mode the 'B' flag in the
1236 * stack-segment descriptor determines the size of the
1239 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
1240 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
1242 if (SEG_DESC_DEF32(ss_desc.access))
1248 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
1249 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
1251 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1252 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1254 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
1255 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
1260 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
1261 rsp, size, stackaddrsize, pushop ? PROT_WRITE : PROT_READ,
1263 vm_inject_ss(vm, vcpuid, 0);
1267 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
1268 vm_inject_ss(vm, vcpuid, 0);
1272 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
1273 vm_inject_ac(vm, vcpuid, 0);
1277 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size,
1278 pushop ? PROT_WRITE : PROT_READ, copyinfo, nitems(copyinfo),
1284 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
1286 vm_copyout(vm, vcpuid, &val, copyinfo, size);
1288 vm_copyin(vm, vcpuid, copyinfo, &val, size);
1289 error = memwrite(vm, vcpuid, mmio_gpa, val, size, arg);
1292 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1295 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
1297 KASSERT(error == 0, ("error %d updating rsp", error));
1303 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1304 struct vm_guest_paging *paging, mem_region_read_t memread,
1305 mem_region_write_t memwrite, void *arg)
1310 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1312 * PUSH is part of the group 5 extended opcodes and is identified
1313 * by ModRM:reg = b110.
1315 if ((vie->reg & 7) != 6)
1318 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1324 emulate_pop(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1325 struct vm_guest_paging *paging, mem_region_read_t memread,
1326 mem_region_write_t memwrite, void *arg)
1331 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1333 * POP is part of the group 1A extended opcodes and is identified
1334 * by ModRM:reg = b000.
1336 if ((vie->reg & 7) != 0)
1339 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1345 emulate_group1(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1346 struct vm_guest_paging *paging, mem_region_read_t memread,
1347 mem_region_write_t memwrite, void *memarg)
1351 switch (vie->reg & 7) {
1353 error = emulate_or(vm, vcpuid, gpa, vie,
1354 memread, memwrite, memarg);
1357 error = emulate_and(vm, vcpuid, gpa, vie,
1358 memread, memwrite, memarg);
1361 error = emulate_cmp(vm, vcpuid, gpa, vie,
1362 memread, memwrite, memarg);
1373 emulate_bittest(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1374 mem_region_read_t memread, mem_region_write_t memwrite, void *memarg)
1376 uint64_t val, rflags;
1377 int error, bitmask, bitoff;
1380 * 0F BA is a Group 8 extended opcode.
1382 * Currently we only emulate the 'Bit Test' instruction which is
1383 * identified by a ModR/M:reg encoding of 100b.
1385 if ((vie->reg & 7) != 4)
1388 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1389 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1391 error = memread(vm, vcpuid, gpa, &val, vie->opsize, memarg);
1396 * Intel SDM, Vol 2, Table 3-2:
1397 * "Range of Bit Positions Specified by Bit Offset Operands"
1399 bitmask = vie->opsize * 8 - 1;
1400 bitoff = vie->immediate & bitmask;
1402 /* Copy the bit into the Carry flag in %rflags */
1403 if (val & (1UL << bitoff))
1408 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
1409 KASSERT(error == 0, ("%s: error %d updating rflags", __func__, error));
1415 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1416 struct vm_guest_paging *paging, mem_region_read_t memread,
1417 mem_region_write_t memwrite, void *memarg)
1424 switch (vie->op.op_type) {
1425 case VIE_OP_TYPE_GROUP1:
1426 error = emulate_group1(vm, vcpuid, gpa, vie, paging, memread,
1429 case VIE_OP_TYPE_POP:
1430 error = emulate_pop(vm, vcpuid, gpa, vie, paging, memread,
1433 case VIE_OP_TYPE_PUSH:
1434 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
1437 case VIE_OP_TYPE_CMP:
1438 error = emulate_cmp(vm, vcpuid, gpa, vie,
1439 memread, memwrite, memarg);
1441 case VIE_OP_TYPE_MOV:
1442 error = emulate_mov(vm, vcpuid, gpa, vie,
1443 memread, memwrite, memarg);
1445 case VIE_OP_TYPE_MOVSX:
1446 case VIE_OP_TYPE_MOVZX:
1447 error = emulate_movx(vm, vcpuid, gpa, vie,
1448 memread, memwrite, memarg);
1450 case VIE_OP_TYPE_MOVS:
1451 error = emulate_movs(vm, vcpuid, gpa, vie, paging, memread,
1454 case VIE_OP_TYPE_STOS:
1455 error = emulate_stos(vm, vcpuid, gpa, vie, paging, memread,
1458 case VIE_OP_TYPE_AND:
1459 error = emulate_and(vm, vcpuid, gpa, vie,
1460 memread, memwrite, memarg);
1462 case VIE_OP_TYPE_OR:
1463 error = emulate_or(vm, vcpuid, gpa, vie,
1464 memread, memwrite, memarg);
1466 case VIE_OP_TYPE_SUB:
1467 error = emulate_sub(vm, vcpuid, gpa, vie,
1468 memread, memwrite, memarg);
1470 case VIE_OP_TYPE_BITTEST:
1471 error = emulate_bittest(vm, vcpuid, gpa, vie,
1472 memread, memwrite, memarg);
1483 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
1485 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1486 ("%s: invalid size %d", __func__, size));
1487 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
1489 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
1492 return ((gla & (size - 1)) ? 1 : 0);
1496 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
1500 if (cpu_mode != CPU_MODE_64BIT)
1504 * The value of the bit 47 in the 'gla' should be replicated in the
1505 * most significant 16 bits.
1507 mask = ~((1UL << 48) - 1);
1508 if (gla & (1UL << 47))
1509 return ((gla & mask) != mask);
1511 return ((gla & mask) != 0);
1515 vie_size2mask(int size)
1517 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1518 ("vie_size2mask: invalid size %d", size));
1519 return (size2mask[size]);
1523 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
1524 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
1525 int prot, uint64_t *gla)
1527 uint64_t firstoff, low_limit, high_limit, segbase;
1530 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
1531 ("%s: invalid segment %d", __func__, seg));
1532 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
1533 ("%s: invalid operand size %d", __func__, length));
1534 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
1535 ("%s: invalid prot %#x", __func__, prot));
1538 if (cpu_mode == CPU_MODE_64BIT) {
1539 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
1540 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
1543 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
1544 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
1547 * If the segment selector is loaded with a NULL selector
1548 * then the descriptor is unusable and attempting to use
1549 * it results in a #GP(0).
1551 if (SEG_DESC_UNUSABLE(desc->access))
1555 * The processor generates a #NP exception when a segment
1556 * register is loaded with a selector that points to a
1557 * descriptor that is not present. If this was the case then
1558 * it would have been checked before the VM-exit.
1560 KASSERT(SEG_DESC_PRESENT(desc->access),
1561 ("segment %d not present: %#x", seg, desc->access));
1564 * The descriptor type must indicate a code/data segment.
1566 type = SEG_DESC_TYPE(desc->access);
1567 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
1568 "descriptor type %#x", seg, type));
1570 if (prot & PROT_READ) {
1571 /* #GP on a read access to a exec-only code segment */
1572 if ((type & 0xA) == 0x8)
1576 if (prot & PROT_WRITE) {
1578 * #GP on a write access to a code segment or a
1579 * read-only data segment.
1581 if (type & 0x8) /* code segment */
1584 if ((type & 0xA) == 0) /* read-only data seg */
1589 * 'desc->limit' is fully expanded taking granularity into
1592 if ((type & 0xC) == 0x4) {
1593 /* expand-down data segment */
1594 low_limit = desc->limit + 1;
1595 high_limit = SEG_DESC_DEF32(desc->access) ?
1596 0xffffffff : 0xffff;
1598 /* code segment or expand-up data segment */
1600 high_limit = desc->limit;
1603 while (length > 0) {
1604 offset &= vie_size2mask(addrsize);
1605 if (offset < low_limit || offset > high_limit)
1613 * In 64-bit mode all segments except %fs and %gs have a segment
1614 * base address of 0.
1616 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1617 seg != VM_REG_GUEST_GS) {
1620 segbase = desc->base;
1624 * Truncate 'firstoff' to the effective address size before adding
1625 * it to the segment base.
1627 firstoff &= vie_size2mask(addrsize);
1628 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1634 vie_init(struct vie *vie, const char *inst_bytes, int inst_length)
1636 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE,
1637 ("%s: invalid instruction length (%d)", __func__, inst_length));
1639 bzero(vie, sizeof(struct vie));
1641 vie->base_register = VM_REG_LAST;
1642 vie->index_register = VM_REG_LAST;
1643 vie->segment_register = VM_REG_LAST;
1646 bcopy(inst_bytes, vie->inst, inst_length);
1647 vie->num_valid = inst_length;
1652 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1657 error_code |= PGEX_P;
1658 if (prot & VM_PROT_WRITE)
1659 error_code |= PGEX_W;
1661 error_code |= PGEX_U;
1663 error_code |= PGEX_RSV;
1664 if (prot & VM_PROT_EXECUTE)
1665 error_code |= PGEX_I;
1667 return (error_code);
1671 ptp_release(void **cookie)
1673 if (*cookie != NULL) {
1674 vm_gpa_release(*cookie);
1680 ptp_hold(struct vm *vm, int vcpu, vm_paddr_t ptpphys, size_t len, void **cookie)
1684 ptp_release(cookie);
1685 ptr = vm_gpa_hold(vm, vcpu, ptpphys, len, VM_PROT_RW, cookie);
1690 vm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1691 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault)
1693 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1695 uint64_t *ptpbase, ptpphys, pte, pgsize;
1696 uint32_t *ptpbase32, pte32;
1701 usermode = (paging->cpl == 3 ? 1 : 0);
1702 writable = prot & VM_PROT_WRITE;
1707 ptpphys = paging->cr3; /* root of the page tables */
1708 ptp_release(&cookie);
1712 if (vie_canonical_check(paging->cpu_mode, gla)) {
1714 * XXX assuming a non-stack reference otherwise a stack fault
1715 * should be generated.
1717 vm_inject_gp(vm, vcpuid);
1721 if (paging->paging_mode == PAGING_MODE_FLAT) {
1726 if (paging->paging_mode == PAGING_MODE_32) {
1728 while (--nlevels >= 0) {
1729 /* Zero out the lower 12 bits. */
1732 ptpbase32 = ptp_hold(vm, vcpuid, ptpphys, PAGE_SIZE,
1735 if (ptpbase32 == NULL)
1738 ptpshift = PAGE_SHIFT + nlevels * 10;
1739 ptpindex = (gla >> ptpshift) & 0x3FF;
1740 pgsize = 1UL << ptpshift;
1742 pte32 = ptpbase32[ptpindex];
1744 if ((pte32 & PG_V) == 0 ||
1745 (usermode && (pte32 & PG_U) == 0) ||
1746 (writable && (pte32 & PG_RW) == 0)) {
1747 pfcode = pf_error_code(usermode, prot, 0,
1749 vm_inject_pf(vm, vcpuid, pfcode, gla);
1754 * Emulate the x86 MMU's management of the accessed
1755 * and dirty flags. While the accessed flag is set
1756 * at every level of the page table, the dirty flag
1757 * is only set at the last level providing the guest
1760 if ((pte32 & PG_A) == 0) {
1761 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1762 pte32, pte32 | PG_A) == 0) {
1767 /* XXX must be ignored if CR4.PSE=0 */
1768 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1774 /* Set the dirty bit in the page table entry if necessary */
1775 if (writable && (pte32 & PG_M) == 0) {
1776 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1777 pte32, pte32 | PG_M) == 0) {
1782 /* Zero out the lower 'ptpshift' bits */
1783 pte32 >>= ptpshift; pte32 <<= ptpshift;
1784 *gpa = pte32 | (gla & (pgsize - 1));
1788 if (paging->paging_mode == PAGING_MODE_PAE) {
1789 /* Zero out the lower 5 bits and the upper 32 bits */
1790 ptpphys &= 0xffffffe0UL;
1792 ptpbase = ptp_hold(vm, vcpuid, ptpphys, sizeof(*ptpbase) * 4,
1794 if (ptpbase == NULL)
1797 ptpindex = (gla >> 30) & 0x3;
1799 pte = ptpbase[ptpindex];
1801 if ((pte & PG_V) == 0) {
1802 pfcode = pf_error_code(usermode, prot, 0, pte);
1803 vm_inject_pf(vm, vcpuid, pfcode, gla);
1812 while (--nlevels >= 0) {
1813 /* Zero out the lower 12 bits and the upper 12 bits */
1814 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1816 ptpbase = ptp_hold(vm, vcpuid, ptpphys, PAGE_SIZE, &cookie);
1817 if (ptpbase == NULL)
1820 ptpshift = PAGE_SHIFT + nlevels * 9;
1821 ptpindex = (gla >> ptpshift) & 0x1FF;
1822 pgsize = 1UL << ptpshift;
1824 pte = ptpbase[ptpindex];
1826 if ((pte & PG_V) == 0 ||
1827 (usermode && (pte & PG_U) == 0) ||
1828 (writable && (pte & PG_RW) == 0)) {
1829 pfcode = pf_error_code(usermode, prot, 0, pte);
1830 vm_inject_pf(vm, vcpuid, pfcode, gla);
1834 /* Set the accessed bit in the page table entry */
1835 if ((pte & PG_A) == 0) {
1836 if (atomic_cmpset_64(&ptpbase[ptpindex],
1837 pte, pte | PG_A) == 0) {
1842 if (nlevels > 0 && (pte & PG_PS) != 0) {
1843 if (pgsize > 1 * GB) {
1844 pfcode = pf_error_code(usermode, prot, 1, pte);
1845 vm_inject_pf(vm, vcpuid, pfcode, gla);
1854 /* Set the dirty bit in the page table entry if necessary */
1855 if (writable && (pte & PG_M) == 0) {
1856 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1860 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1861 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1862 *gpa = pte | (gla & (pgsize - 1));
1864 ptp_release(&cookie);
1865 KASSERT(retval == 0 || retval == EFAULT, ("%s: unexpected retval %d",
1877 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1878 uint64_t rip, int inst_length, struct vie *vie, int *faultptr)
1880 struct vm_copyinfo copyinfo[2];
1883 if (inst_length > VIE_INST_SIZE)
1884 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1886 prot = PROT_READ | PROT_EXEC;
1887 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1888 copyinfo, nitems(copyinfo), faultptr);
1889 if (error || *faultptr)
1892 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1893 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1894 vie->num_valid = inst_length;
1899 vie_peek(struct vie *vie, uint8_t *x)
1902 if (vie->num_processed < vie->num_valid) {
1903 *x = vie->inst[vie->num_processed];
1910 vie_advance(struct vie *vie)
1913 vie->num_processed++;
1917 segment_override(uint8_t x, int *seg)
1922 *seg = VM_REG_GUEST_CS;
1925 *seg = VM_REG_GUEST_SS;
1928 *seg = VM_REG_GUEST_DS;
1931 *seg = VM_REG_GUEST_ES;
1934 *seg = VM_REG_GUEST_FS;
1937 *seg = VM_REG_GUEST_GS;
1946 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
1951 if (vie_peek(vie, &x))
1955 vie->opsize_override = 1;
1957 vie->addrsize_override = 1;
1959 vie->repz_present = 1;
1961 vie->repnz_present = 1;
1962 else if (segment_override(x, &vie->segment_register))
1963 vie->segment_override = 1;
1971 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
1972 * - Only one REX prefix is allowed per instruction.
1973 * - The REX prefix must immediately precede the opcode byte or the
1974 * escape opcode byte.
1975 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
1976 * the mandatory prefix must come before the REX prefix.
1978 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
1979 vie->rex_present = 1;
1980 vie->rex_w = x & 0x8 ? 1 : 0;
1981 vie->rex_r = x & 0x4 ? 1 : 0;
1982 vie->rex_x = x & 0x2 ? 1 : 0;
1983 vie->rex_b = x & 0x1 ? 1 : 0;
1988 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
1990 if (cpu_mode == CPU_MODE_64BIT) {
1992 * Default address size is 64-bits and default operand size
1995 vie->addrsize = vie->addrsize_override ? 4 : 8;
1998 else if (vie->opsize_override)
2003 /* Default address and operand sizes are 32-bits */
2004 vie->addrsize = vie->addrsize_override ? 2 : 4;
2005 vie->opsize = vie->opsize_override ? 2 : 4;
2007 /* Default address and operand sizes are 16-bits */
2008 vie->addrsize = vie->addrsize_override ? 4 : 2;
2009 vie->opsize = vie->opsize_override ? 4 : 2;
2015 decode_two_byte_opcode(struct vie *vie)
2019 if (vie_peek(vie, &x))
2022 vie->op = two_byte_opcodes[x];
2024 if (vie->op.op_type == VIE_OP_TYPE_NONE)
2032 decode_opcode(struct vie *vie)
2036 if (vie_peek(vie, &x))
2039 vie->op = one_byte_opcodes[x];
2041 if (vie->op.op_type == VIE_OP_TYPE_NONE)
2046 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
2047 return (decode_two_byte_opcode(vie));
2053 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
2057 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
2060 if (cpu_mode == CPU_MODE_REAL)
2063 if (vie_peek(vie, &x))
2066 vie->mod = (x >> 6) & 0x3;
2067 vie->rm = (x >> 0) & 0x7;
2068 vie->reg = (x >> 3) & 0x7;
2071 * A direct addressing mode makes no sense in the context of an EPT
2072 * fault. There has to be a memory access involved to cause the
2075 if (vie->mod == VIE_MOD_DIRECT)
2078 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
2079 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
2081 * Table 2-5: Special Cases of REX Encodings
2083 * mod=0, r/m=5 is used in the compatibility mode to
2084 * indicate a disp32 without a base register.
2086 * mod!=3, r/m=4 is used in the compatibility mode to
2087 * indicate that the SIB byte is present.
2089 * The 'b' bit in the REX prefix is don't care in
2093 vie->rm |= (vie->rex_b << 3);
2096 vie->reg |= (vie->rex_r << 3);
2099 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
2102 vie->base_register = gpr_map[vie->rm];
2105 case VIE_MOD_INDIRECT_DISP8:
2106 vie->disp_bytes = 1;
2108 case VIE_MOD_INDIRECT_DISP32:
2109 vie->disp_bytes = 4;
2111 case VIE_MOD_INDIRECT:
2112 if (vie->rm == VIE_RM_DISP32) {
2113 vie->disp_bytes = 4;
2115 * Table 2-7. RIP-Relative Addressing
2117 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
2118 * whereas in compatibility mode it just implies disp32.
2121 if (cpu_mode == CPU_MODE_64BIT)
2122 vie->base_register = VM_REG_GUEST_RIP;
2124 vie->base_register = VM_REG_LAST;
2136 decode_sib(struct vie *vie)
2140 /* Proceed only if SIB byte is present */
2141 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
2144 if (vie_peek(vie, &x))
2147 /* De-construct the SIB byte */
2148 vie->ss = (x >> 6) & 0x3;
2149 vie->index = (x >> 3) & 0x7;
2150 vie->base = (x >> 0) & 0x7;
2152 /* Apply the REX prefix modifiers */
2153 vie->index |= vie->rex_x << 3;
2154 vie->base |= vie->rex_b << 3;
2157 case VIE_MOD_INDIRECT_DISP8:
2158 vie->disp_bytes = 1;
2160 case VIE_MOD_INDIRECT_DISP32:
2161 vie->disp_bytes = 4;
2165 if (vie->mod == VIE_MOD_INDIRECT &&
2166 (vie->base == 5 || vie->base == 13)) {
2168 * Special case when base register is unused if mod = 0
2169 * and base = %rbp or %r13.
2172 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2173 * Table 2-5: Special Cases of REX Encodings
2175 vie->disp_bytes = 4;
2177 vie->base_register = gpr_map[vie->base];
2181 * All encodings of 'index' are valid except for %rsp (4).
2184 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
2185 * Table 2-5: Special Cases of REX Encodings
2187 if (vie->index != 4)
2188 vie->index_register = gpr_map[vie->index];
2190 /* 'scale' makes sense only in the context of an index register */
2191 if (vie->index_register < VM_REG_LAST)
2192 vie->scale = 1 << vie->ss;
2200 decode_displacement(struct vie *vie)
2211 if ((n = vie->disp_bytes) == 0)
2214 if (n != 1 && n != 4)
2215 panic("decode_displacement: invalid disp_bytes %d", n);
2217 for (i = 0; i < n; i++) {
2218 if (vie_peek(vie, &x))
2226 vie->displacement = u.signed8; /* sign-extended */
2228 vie->displacement = u.signed32; /* sign-extended */
2234 decode_immediate(struct vie *vie)
2245 /* Figure out immediate operand size (if any) */
2246 if (vie->op.op_flags & VIE_OP_F_IMM) {
2248 * Section 2.2.1.5 "Immediates", Intel SDM:
2249 * In 64-bit mode the typical size of immediate operands
2250 * remains 32-bits. When the operand size if 64-bits, the
2251 * processor sign-extends all immediates to 64-bits prior
2254 if (vie->opsize == 4 || vie->opsize == 8)
2258 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
2262 if ((n = vie->imm_bytes) == 0)
2265 KASSERT(n == 1 || n == 2 || n == 4,
2266 ("%s: invalid number of immediate bytes: %d", __func__, n));
2268 for (i = 0; i < n; i++) {
2269 if (vie_peek(vie, &x))
2276 /* sign-extend the immediate value before use */
2278 vie->immediate = u.signed8;
2280 vie->immediate = u.signed16;
2282 vie->immediate = u.signed32;
2288 decode_moffset(struct vie *vie)
2297 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
2301 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
2302 * The memory offset size follows the address-size of the instruction.
2305 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
2308 for (i = 0; i < n; i++) {
2309 if (vie_peek(vie, &x))
2315 vie->displacement = u.u64;
2320 * Verify that the 'guest linear address' provided as collateral of the nested
2321 * page table fault matches with our instruction decoding.
2324 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie,
2325 enum vm_cpu_mode cpu_mode)
2328 uint64_t base, segbase, idx, gla2;
2329 enum vm_reg_name seg;
2330 struct seg_desc desc;
2332 /* Skip 'gla' verification */
2333 if (gla == VIE_INVALID_GLA)
2337 if (vie->base_register != VM_REG_LAST) {
2338 error = vm_get_register(vm, cpuid, vie->base_register, &base);
2340 printf("verify_gla: error %d getting base reg %d\n",
2341 error, vie->base_register);
2346 * RIP-relative addressing starts from the following
2349 if (vie->base_register == VM_REG_GUEST_RIP)
2350 base += vie->num_processed;
2354 if (vie->index_register != VM_REG_LAST) {
2355 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
2357 printf("verify_gla: error %d getting index reg %d\n",
2358 error, vie->index_register);
2364 * From "Specifying a Segment Selector", Intel SDM, Vol 1
2366 * In 64-bit mode, segmentation is generally (but not
2367 * completely) disabled. The exceptions are the FS and GS
2370 * In legacy IA-32 mode, when the ESP or EBP register is used
2371 * as the base, the SS segment is the default segment. For
2372 * other data references, except when relative to stack or
2373 * string destination the DS segment is the default. These
2374 * can be overridden to allow other segments to be accessed.
2376 if (vie->segment_override)
2377 seg = vie->segment_register;
2378 else if (vie->base_register == VM_REG_GUEST_RSP ||
2379 vie->base_register == VM_REG_GUEST_RBP)
2380 seg = VM_REG_GUEST_SS;
2382 seg = VM_REG_GUEST_DS;
2383 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
2384 seg != VM_REG_GUEST_GS) {
2387 error = vm_get_seg_desc(vm, cpuid, seg, &desc);
2389 printf("verify_gla: error %d getting segment"
2390 " descriptor %d", error,
2391 vie->segment_register);
2394 segbase = desc.base;
2397 gla2 = segbase + base + vie->scale * idx + vie->displacement;
2398 gla2 &= size2mask[vie->addrsize];
2400 printf("verify_gla mismatch: segbase(0x%0lx)"
2401 "base(0x%0lx), scale(%d), index(0x%0lx), "
2402 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
2403 segbase, base, vie->scale, idx, vie->displacement,
2412 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
2413 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
2416 if (decode_prefixes(vie, cpu_mode, cs_d))
2419 if (decode_opcode(vie))
2422 if (decode_modrm(vie, cpu_mode))
2425 if (decode_sib(vie))
2428 if (decode_displacement(vie))
2431 if (decode_immediate(vie))
2434 if (decode_moffset(vie))
2437 if ((vie->op.op_flags & VIE_OP_F_NO_GLA_VERIFICATION) == 0) {
2438 if (verify_gla(vm, cpuid, gla, vie, cpu_mode))
2442 vie->decoded = 1; /* success */
2446 #endif /* _KERNEL */