2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
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12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <x86/specialreg.h>
37 #include <x86/apicreg.h>
39 #include <machine/vmm.h>
42 #include "vmm_lapic.h"
46 * Some MSI message definitions
48 #define MSI_X86_ADDR_MASK 0xfff00000
49 #define MSI_X86_ADDR_BASE 0xfee00000
50 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */
51 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */
54 lapic_set_intr(struct vm *vm, int cpu, int vector, bool level)
56 struct vlapic *vlapic;
58 if (cpu < 0 || cpu >= VM_MAXCPU)
61 if (vector < 32 || vector > 255)
64 vlapic = vm_lapic(vm, cpu);
65 if (vlapic_set_intr_ready(vlapic, vector, level))
66 vcpu_notify_event(vm, cpu, true);
71 lapic_set_local_intr(struct vm *vm, int cpu, int vector)
73 struct vlapic *vlapic;
77 if (cpu < -1 || cpu >= VM_MAXCPU)
81 dmask = vm_active_cpus(vm);
83 CPU_SETOF(cpu, &dmask);
85 while ((cpu = CPU_FFS(&dmask)) != 0) {
88 vlapic = vm_lapic(vm, cpu);
89 error = vlapic_trigger_lvt(vlapic, vector);
98 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
104 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg);
106 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) {
107 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr);
112 * Extract the x86-specific fields from the MSI addr/msg
113 * params according to the Intel Arch spec, Vol3 Ch 10.
115 * The PCI specification does not support level triggered
116 * MSI/MSI-X so ignore trigger level in 'msg'.
118 * The 'dest' is interpreted as a logical APIC ID if both
119 * the Redirection Hint and Destination Mode are '1' and
120 * physical otherwise.
122 dest = (addr >> 12) & 0xff;
123 phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) !=
124 (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG));
125 delmode = msg & APIC_DELMODE_MASK;
128 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d",
129 phys ? "physical" : "logical", dest, vec);
131 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec);
136 x2apic_msr(u_int msr)
138 if (msr >= 0x800 && msr <= 0xBFF)
145 x2apic_msr_to_regoff(u_int msr)
148 return ((msr - 0x800) << 4);
155 if (x2apic_msr(msr) || (msr == MSR_APICBASE))
162 lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu)
166 struct vlapic *vlapic;
168 vlapic = vm_lapic(vm, cpu);
170 if (msr == MSR_APICBASE) {
171 *rval = vlapic_get_apicbase(vlapic);
174 offset = x2apic_msr_to_regoff(msr);
175 error = vlapic_read(vlapic, 0, offset, rval, retu);
182 lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu)
186 struct vlapic *vlapic;
188 vlapic = vm_lapic(vm, cpu);
190 if (msr == MSR_APICBASE) {
191 error = vlapic_set_apicbase(vlapic, val);
193 offset = x2apic_msr_to_regoff(msr);
194 error = vlapic_write(vlapic, 0, offset, val, retu);
201 lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size,
206 struct vlapic *vlapic;
208 off = gpa - DEFAULT_APIC_BASE;
211 * Memory mapped local apic accesses must be 4 bytes wide and
212 * aligned on a 16-byte boundary.
214 if (size != 4 || off & 0xf)
217 vlapic = vm_lapic(vm, cpu);
218 error = vlapic_write(vlapic, 1, off, wval, arg);
223 lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size,
228 struct vlapic *vlapic;
230 off = gpa - DEFAULT_APIC_BASE;
233 * Memory mapped local apic accesses must be 4 bytes wide and
234 * aligned on a 16-byte boundary.
236 if (size != 4 || off & 0xf)
239 vlapic = vm_lapic(vm, cpu);
240 error = vlapic_read(vlapic, 1, off, rval, arg);