2 * Copyright (c) 2011 NetApp, Inc.
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29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <x86/specialreg.h>
37 #include <x86/apicreg.h>
39 #include <machine/vmm.h>
41 #include "vmm_lapic.h"
45 * Some MSI message definitions
47 #define MSI_X86_ADDR_MASK 0xfff00000
48 #define MSI_X86_ADDR_BASE 0xfee00000
49 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */
50 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */
53 lapic_set_intr(struct vm *vm, int cpu, int vector, bool level)
55 struct vlapic *vlapic;
57 if (cpu < 0 || cpu >= VM_MAXCPU)
61 * According to section "Maskable Hardware Interrupts" in Intel SDM
62 * vectors 16 through 255 can be delivered through the local APIC.
64 if (vector < 16 || vector > 255)
67 vlapic = vm_lapic(vm, cpu);
68 if (vlapic_set_intr_ready(vlapic, vector, level))
69 vcpu_notify_event(vm, cpu, true);
74 lapic_set_local_intr(struct vm *vm, int cpu, int vector)
76 struct vlapic *vlapic;
80 if (cpu < -1 || cpu >= VM_MAXCPU)
84 dmask = vm_active_cpus(vm);
86 CPU_SETOF(cpu, &dmask);
88 while ((cpu = CPU_FFS(&dmask)) != 0) {
91 vlapic = vm_lapic(vm, cpu);
92 error = vlapic_trigger_lvt(vlapic, vector);
101 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
107 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg);
109 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) {
110 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr);
115 * Extract the x86-specific fields from the MSI addr/msg
116 * params according to the Intel Arch spec, Vol3 Ch 10.
118 * The PCI specification does not support level triggered
119 * MSI/MSI-X so ignore trigger level in 'msg'.
121 * The 'dest' is interpreted as a logical APIC ID if both
122 * the Redirection Hint and Destination Mode are '1' and
123 * physical otherwise.
125 dest = (addr >> 12) & 0xff;
126 phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) !=
127 (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG));
128 delmode = msg & APIC_DELMODE_MASK;
131 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d",
132 phys ? "physical" : "logical", dest, vec);
134 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec);
139 x2apic_msr(u_int msr)
141 if (msr >= 0x800 && msr <= 0xBFF)
148 x2apic_msr_to_regoff(u_int msr)
151 return ((msr - 0x800) << 4);
158 if (x2apic_msr(msr) || (msr == MSR_APICBASE))
165 lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu)
169 struct vlapic *vlapic;
171 vlapic = vm_lapic(vm, cpu);
173 if (msr == MSR_APICBASE) {
174 *rval = vlapic_get_apicbase(vlapic);
177 offset = x2apic_msr_to_regoff(msr);
178 error = vlapic_read(vlapic, 0, offset, rval, retu);
185 lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu)
189 struct vlapic *vlapic;
191 vlapic = vm_lapic(vm, cpu);
193 if (msr == MSR_APICBASE) {
194 error = vlapic_set_apicbase(vlapic, val);
196 offset = x2apic_msr_to_regoff(msr);
197 error = vlapic_write(vlapic, 0, offset, val, retu);
204 lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size,
209 struct vlapic *vlapic;
211 off = gpa - DEFAULT_APIC_BASE;
214 * Memory mapped local apic accesses must be 4 bytes wide and
215 * aligned on a 16-byte boundary.
217 if (size != 4 || off & 0xf)
220 vlapic = vm_lapic(vm, cpu);
221 error = vlapic_write(vlapic, 1, off, wval, arg);
226 lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size,
231 struct vlapic *vlapic;
233 off = gpa - DEFAULT_APIC_BASE;
236 * Memory mapped local apic accesses should be aligned on a
237 * 16-byte boundary. They are also suggested to be 4 bytes
238 * wide, alas not all OSes follow suggestions.
244 vlapic = vm_lapic(vm, cpu);
245 error = vlapic_read(vlapic, 1, off, rval, arg);