2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sysctl.h>
39 #include <machine/clock.h>
40 #include <machine/cpufunc.h>
41 #include <machine/md_var.h>
42 #include <machine/segments.h>
43 #include <machine/specialreg.h>
45 #include <machine/vmm.h>
53 static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD, 0, NULL);
55 #define CPUID_VM_HIGH 0x40000000
57 static const char bhyve_id[12] = "bhyve bhyve ";
59 static uint64_t bhyve_xcpuids;
60 SYSCTL_ULONG(_hw_vmm, OID_AUTO, bhyve_xcpuids, CTLFLAG_RW, &bhyve_xcpuids, 0,
61 "Number of times an unknown cpuid leaf was accessed");
63 #if __FreeBSD_version < 1200060 /* Remove after 11 EOL helps MFCing */
64 extern u_int threads_per_core;
65 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, threads_per_core, CTLFLAG_RDTUN,
66 &threads_per_core, 0, NULL);
68 extern u_int cores_per_package;
69 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, cores_per_package, CTLFLAG_RDTUN,
70 &cores_per_package, 0, NULL);
73 static int cpuid_leaf_b = 1;
74 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN,
75 &cpuid_leaf_b, 0, NULL);
78 * Round up to the next power of two, if necessary, and then take log2.
79 * Returns -1 if argument is zero.
85 return (fls(x << (1 - powerof2(x))) - 1);
89 x86_emulate_cpuid(struct vm *vm, int vcpu_id,
90 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
92 const struct xsave_limits *limits;
94 int error, enable_invpcid, level, width, x2apic_id;
95 unsigned int func, regs[4], logical_cpus;
96 enum x2apic_state x2apic_state;
97 uint16_t cores, maxcpus, sockets, threads;
99 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", *eax, *ecx);
102 * Requests for invalid CPUID levels should map to the highest
103 * available level instead.
105 if (cpu_exthigh != 0 && *eax >= 0x80000000) {
106 if (*eax > cpu_exthigh)
108 } else if (*eax >= 0x40000000) {
109 if (*eax > CPUID_VM_HIGH)
110 *eax = CPUID_VM_HIGH;
111 } else if (*eax > cpu_high) {
118 * In general the approach used for CPU topology is to
119 * advertise a flat topology where all CPUs are packages with
120 * no multi-core or SMT.
124 * Pass these through to the guest
126 case CPUID_0000_0000:
127 case CPUID_0000_0002:
128 case CPUID_0000_0003:
129 case CPUID_8000_0000:
130 case CPUID_8000_0002:
131 case CPUID_8000_0003:
132 case CPUID_8000_0004:
133 case CPUID_8000_0006:
134 cpuid_count(*eax, *ecx, regs);
136 case CPUID_8000_0008:
137 cpuid_count(*eax, *ecx, regs);
140 * XXX this might appear silly because AMD
141 * cpus don't have threads.
143 * However this matches the logical cpus as
144 * advertised by leaf 0x1 and will work even
145 * if threads is set incorrectly on an AMD host.
147 vm_get_topology(vm, &sockets, &cores, &threads,
149 logical_cpus = threads * cores;
150 regs[2] = logical_cpus - 1;
154 case CPUID_8000_0001:
155 cpuid_count(*eax, *ecx, regs);
158 * Hide SVM and Topology Extension features from guest.
160 regs[2] &= ~(AMDID2_SVM | AMDID2_TOPOLOGY);
163 * Don't advertise extended performance counter MSRs
166 regs[2] &= ~AMDID2_PCXC;
167 regs[2] &= ~AMDID2_PNXC;
168 regs[2] &= ~AMDID2_PTSCEL2I;
171 * Don't advertise Instruction Based Sampling feature.
173 regs[2] &= ~AMDID2_IBS;
175 /* NodeID MSR not available */
176 regs[2] &= ~AMDID2_NODE_ID;
178 /* Don't advertise the OS visible workaround feature */
179 regs[2] &= ~AMDID2_OSVW;
181 /* Hide mwaitx/monitorx capability from the guest */
182 regs[2] &= ~AMDID2_MWAITX;
185 * Hide rdtscp/ia32_tsc_aux until we know how
188 regs[3] &= ~AMDID_RDTSCP;
191 case CPUID_8000_0007:
193 * AMD uses this leaf to advertise the processor's
194 * power monitoring and RAS capabilities. These
195 * features are hardware-specific and exposing
196 * them to a guest doesn't make a lot of sense.
198 * Intel uses this leaf only to advertise the
199 * "Invariant TSC" feature with all other bits
200 * being reserved (set to zero).
208 * "Invariant TSC" can be advertised to the guest if:
209 * - host TSC frequency is invariant
210 * - host TSCs are synchronized across physical cpus
212 * XXX This still falls short because the vcpu
213 * can observe the TSC moving backwards as it
214 * migrates across physical cpus. But at least
215 * it should discourage the guest from using the
216 * TSC to keep track of time.
218 if (tsc_is_invariant && smp_tsc)
219 regs[3] |= AMDPM_TSC_INVARIANT;
222 case CPUID_0000_0001:
225 error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state);
227 panic("x86_emulate_cpuid: error %d "
228 "fetching x2apic state", error);
232 * Override the APIC ID only in ebx
234 regs[1] &= ~(CPUID_LOCAL_APIC_ID);
235 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
238 * Don't expose VMX, SpeedStep, TME or SMX capability.
239 * Advertise x2APIC capability and Hypervisor guest.
241 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
242 regs[2] &= ~(CPUID2_SMX);
244 regs[2] |= CPUID2_HV;
246 if (x2apic_state != X2APIC_DISABLED)
247 regs[2] |= CPUID2_X2APIC;
249 regs[2] &= ~CPUID2_X2APIC;
252 * Only advertise CPUID2_XSAVE in the guest if
253 * the host is using XSAVE.
255 if (!(regs[2] & CPUID2_OSXSAVE))
256 regs[2] &= ~CPUID2_XSAVE;
259 * If CPUID2_XSAVE is being advertised and the
260 * guest has set CR4_XSAVE, set
263 regs[2] &= ~CPUID2_OSXSAVE;
264 if (regs[2] & CPUID2_XSAVE) {
265 error = vm_get_register(vm, vcpu_id,
266 VM_REG_GUEST_CR4, &cr4);
268 panic("x86_emulate_cpuid: error %d "
269 "fetching %%cr4", error);
271 regs[2] |= CPUID2_OSXSAVE;
275 * Hide monitor/mwait until we know how to deal with
276 * these instructions.
278 regs[2] &= ~CPUID2_MON;
281 * Hide the performance and debug features.
283 regs[2] &= ~CPUID2_PDCM;
286 * No TSC deadline support in the APIC yet
288 regs[2] &= ~CPUID2_TSCDLT;
291 * Hide thermal monitoring
293 regs[3] &= ~(CPUID_ACPI | CPUID_TM);
296 * Hide the debug store capability.
298 regs[3] &= ~CPUID_DS;
301 * Advertise the Machine Check and MTRR capability.
303 * Some guest OSes (e.g. Windows) will not boot if
304 * these features are absent.
306 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR);
308 vm_get_topology(vm, &sockets, &cores, &threads,
310 logical_cpus = threads * cores;
311 regs[1] &= ~CPUID_HTT_CORES;
312 regs[1] |= (logical_cpus & 0xff) << 16;
313 regs[3] |= CPUID_HTT;
316 case CPUID_0000_0004:
317 cpuid_count(*eax, *ecx, regs);
319 if (regs[0] || regs[1] || regs[2] || regs[3]) {
320 vm_get_topology(vm, &sockets, &cores, &threads,
323 regs[0] |= (cores - 1) << 26;
326 * - L1 and L2 are shared only by the logical
327 * processors in a single core.
328 * - L3 and above are shared by all logical
329 * processors in the package.
331 logical_cpus = threads;
332 level = (regs[0] >> 5) & 0x7;
334 logical_cpus *= cores;
335 regs[0] |= (logical_cpus - 1) << 14;
339 case CPUID_0000_0007:
347 cpuid_count(*eax, *ecx, regs);
349 /* Only leaf 0 is supported */
353 * Expose known-safe features.
355 regs[1] &= (CPUID_STDEXT_FSGSBASE |
356 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
357 CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 |
358 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
359 CPUID_STDEXT_AVX512F |
360 CPUID_STDEXT_AVX512PF |
361 CPUID_STDEXT_AVX512ER |
362 CPUID_STDEXT_AVX512CD);
366 /* Advertise INVPCID if it is enabled. */
367 error = vm_get_capability(vm, vcpu_id,
368 VM_CAP_ENABLE_INVPCID, &enable_invpcid);
369 if (error == 0 && enable_invpcid)
370 regs[1] |= CPUID_STDEXT_INVPCID;
374 case CPUID_0000_0006:
375 regs[0] = CPUTPM1_ARAT;
381 case CPUID_0000_000A:
383 * Handle the access, but report 0 for
392 case CPUID_0000_000B:
394 * Processor topology enumeration
396 vm_get_topology(vm, &sockets, &cores, &threads,
399 logical_cpus = threads;
400 width = log2(logical_cpus);
401 level = CPUID_TYPE_SMT;
406 logical_cpus = threads * cores;
407 width = log2(logical_cpus);
408 level = CPUID_TYPE_CORE;
412 if (!cpuid_leaf_b || *ecx >= 2) {
419 regs[0] = width & 0x1f;
420 regs[1] = logical_cpus & 0xffff;
421 regs[2] = (level << 8) | (*ecx & 0xff);
425 case CPUID_0000_000D:
426 limits = vmm_get_xsave_limits();
427 if (!limits->xsave_enabled) {
435 cpuid_count(*eax, *ecx, regs);
439 * Only permit the guest to use bits
440 * that are active in the host in
441 * %xcr0. Also, claim that the
442 * maximum save area size is
443 * equivalent to the host's current
444 * save area size. Since this runs
445 * "inside" of vmrun(), it runs with
446 * the guest's xcr0, so the current
447 * save area size is correct as-is.
449 regs[0] &= limits->xcr0_allowed;
450 regs[2] = limits->xsave_max_size;
451 regs[3] &= (limits->xcr0_allowed >> 32);
454 /* Only permit XSAVEOPT. */
455 regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
462 * If the leaf is for a permitted feature,
463 * pass through as-is, otherwise return
466 if (!(limits->xcr0_allowed & (1ul << *ecx))) {
477 regs[0] = CPUID_VM_HIGH;
478 bcopy(bhyve_id, ®s[1], 4);
479 bcopy(bhyve_id + 4, ®s[2], 4);
480 bcopy(bhyve_id + 8, ®s[3], 4);
485 * The leaf value has already been clamped so
486 * simply pass this through, keeping count of
487 * how many unhandled leaf values have been seen.
489 atomic_add_long(&bhyve_xcpuids, 1);
490 cpuid_count(*eax, *ecx, regs);
503 vm_cpuid_capability(struct vm *vm, int vcpuid, enum vm_cpuid_capability cap)
507 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d",
511 * Simply passthrough the capabilities of the host cpu for now.
516 if (amd_feature & AMDID_NX)
520 if (amd_feature & AMDID_FFXSR)
524 if (amd_feature2 & AMDID2_TCE)
528 panic("%s: unknown vm_cpu_capability %d", __func__, cap);