sys/amd64/vmm/x86.c

   1 /*-
   2  * Copyright (c) 2011 NetApp, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/types.h>
  34 #include <sys/systm.h>
  35 #include <sys/cpuset.h>
  36
  37 #include <machine/clock.h>
  38 #include <machine/cpufunc.h>
  39 #include <machine/md_var.h>
  40 #include <machine/specialreg.h>
  41
  42 #include <machine/vmm.h>
  43
  44 #include "x86.h"
  45
  46 #define CPUID_VM_HIGH           0x40000000
  47
  48 static const char bhyve_id[12] = "BHyVE BHyVE ";
  49
  50 int
  51 x86_emulate_cpuid(struct vm *vm, int vcpu_id,
  52                   uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
  53 {
  54         int error;
  55         unsigned int    func, regs[4];
  56         enum x2apic_state x2apic_state;
  57
  58         /*
  59          * Requests for invalid CPUID levels should map to the highest
  60          * available level instead.
  61          */
  62         if (cpu_exthigh != 0 && *eax >= 0x80000000) {
  63                 if (*eax > cpu_exthigh)
  64                         *eax = cpu_exthigh;
  65         } else if (*eax >= 0x40000000) {
  66                 if (*eax > CPUID_VM_HIGH)
  67                         *eax = CPUID_VM_HIGH;
  68         } else if (*eax > cpu_high) {
  69                 *eax = cpu_high;
  70         }
  71
  72         func = *eax;
  73
  74         /*
  75          * In general the approach used for CPU topology is to
  76          * advertise a flat topology where all CPUs are packages with
  77          * no multi-core or SMT.
  78          */
  79         switch (func) {
  80                 case CPUID_0000_0000:
  81                 case CPUID_0000_0002:
  82                 case CPUID_0000_0003:
  83                 case CPUID_0000_000A:
  84                         cpuid_count(*eax, *ecx, regs);
  85                         break;
  86
  87                 case CPUID_8000_0000:
  88                 case CPUID_8000_0001:
  89                 case CPUID_8000_0002:
  90                 case CPUID_8000_0003:
  91                 case CPUID_8000_0004:
  92                 case CPUID_8000_0006:
  93                 case CPUID_8000_0008:
  94                         cpuid_count(*eax, *ecx, regs);
  95                         break;
  96
  97                 case CPUID_8000_0007:
  98                         cpuid_count(*eax, *ecx, regs);
  99                         /*
 100                          * If the host TSCs are not synchronized across
 101                          * physical cpus then we cannot advertise an
 102                          * invariant tsc to a vcpu.
 103                          *
 104                          * XXX This still falls short because the vcpu
 105                          * can observe the TSC moving backwards as it
 106                          * migrates across physical cpus. But at least
 107                          * it should discourage the guest from using the
 108                          * TSC to keep track of time.
 109                          */
 110                         if (!smp_tsc)
 111                                 regs[3] &= ~AMDPM_TSC_INVARIANT;
 112                         break;
 113
 114                 case CPUID_0000_0001:
 115                         do_cpuid(1, regs);
 116
 117                         error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state);
 118                         if (error) {
 119                                 panic("x86_emulate_cpuid: error %d "
 120                                       "fetching x2apic state", error);
 121                         }
 122
 123                         /*
 124                          * Override the APIC ID only in ebx
 125                          */
 126                         regs[1] &= ~(CPUID_LOCAL_APIC_ID);
 127                         regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
 128
 129                         /*
 130                          * Don't expose VMX, SpeedStep or TME capability.
 131                          * Advertise x2APIC capability and Hypervisor guest.
 132                          */
 133                         regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
 134
 135                         regs[2] |= CPUID2_HV;
 136
 137                         if (x2apic_state != X2APIC_DISABLED)
 138                                 regs[2] |= CPUID2_X2APIC;
 139
 140                         /*
 141                          * Hide xsave/osxsave/avx until the FPU save/restore
 142                          * issues are resolved
 143                          */
 144                         regs[2] &= ~(CPUID2_XSAVE | CPUID2_OSXSAVE |
 145                                      CPUID2_AVX);
 146
 147                         /*
 148                          * Hide monitor/mwait until we know how to deal with
 149                          * these instructions.
 150                          */
 151                         regs[2] &= ~CPUID2_MON;
 152
 153                         /*
 154                          * Hide thermal monitoring
 155                          */
 156                         regs[3] &= ~(CPUID_ACPI | CPUID_TM);
 157
 158                         /*
 159                          * Machine check handling is done in the host.
 160                          * Hide MTRR capability.
 161                          */
 162                         regs[3] &= ~(CPUID_MCA | CPUID_MCE | CPUID_MTRR);
 163
 164                         /*
 165                          * Disable multi-core.
 166                          */
 167                         regs[1] &= ~CPUID_HTT_CORES;
 168                         regs[3] &= ~CPUID_HTT;
 169                         break;
 170
 171                 case CPUID_0000_0004:
 172                         do_cpuid(4, regs);
 173
 174                         /*
 175                          * Do not expose topology.
 176                          */
 177                         regs[0] &= 0xffff8000;
 178                         regs[0] |= 0x04008000;
 179                         break;
 180
 181                 case CPUID_0000_0006:
 182                 case CPUID_0000_0007:
 183                         /*
 184                          * Handle the access, but report 0 for
 185                          * all options
 186                          */
 187                         regs[0] = 0;
 188                         regs[1] = 0;
 189                         regs[2] = 0;
 190                         regs[3] = 0;
 191                         break;
 192
 193                 case CPUID_0000_000B:
 194                         /*
 195                          * Processor topology enumeration
 196                          */
 197                         regs[0] = 0;
 198                         regs[1] = 0;
 199                         regs[2] = *ecx & 0xff;
 200                         regs[3] = vcpu_id;
 201                         break;
 202
 203                 case 0x40000000:
 204                         regs[0] = CPUID_VM_HIGH;
 205                         bcopy(bhyve_id, &regs[1], 4);
 206                         bcopy(bhyve_id, &regs[2], 4);
 207                         bcopy(bhyve_id, &regs[3], 4);
 208                         break;
 209                 default:
 210                         /* XXX: Leaf 5? */
 211                         return (0);
 212         }
 213
 214         *eax = regs[0];
 215         *ebx = regs[1];
 216         *ecx = regs[2];
 217         *edx = regs[3];
 218         return (1);
 219 }