sys/amd64/vmm/x86.c

   1 /*-
   2  * Copyright (c) 2011 NetApp, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/pcpu.h>
  34 #include <sys/systm.h>
  35 #include <sys/cpuset.h>
  36 #include <sys/sysctl.h>
  37
  38 #include <machine/clock.h>
  39 #include <machine/cpufunc.h>
  40 #include <machine/md_var.h>
  41 #include <machine/segments.h>
  42 #include <machine/specialreg.h>
  43
  44 #include <machine/vmm.h>
  45
  46 #include "vmm_host.h"
  47 #include "x86.h"
  48
  49 SYSCTL_DECL(_hw_vmm);
  50 static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD, 0, NULL);
  51
  52 #define CPUID_VM_HIGH           0x40000000
  53
  54 static const char bhyve_id[12] = "bhyve bhyve ";
  55
  56 static uint64_t bhyve_xcpuids;
  57
  58 /*
  59  * The default CPU topology is a single thread per package.
  60  */
  61 static u_int threads_per_core = 1;
  62 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, threads_per_core, CTLFLAG_RDTUN,
  63     &threads_per_core, 0, NULL);
  64
  65 static u_int cores_per_package = 1;
  66 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, cores_per_package, CTLFLAG_RDTUN,
  67     &cores_per_package, 0, NULL);
  68
  69 static int cpuid_leaf_b = 1;
  70 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN,
  71     &cpuid_leaf_b, 0, NULL);
  72
  73 /*
  74  * Round up to the next power of two, if necessary, and then take log2.
  75  * Returns -1 if argument is zero.
  76  */
  77 static __inline int
  78 log2(u_int x)
  79 {
  80
  81         return (fls(x << (1 - powerof2(x))) - 1);
  82 }
  83
  84 int
  85 x86_emulate_cpuid(struct vm *vm, int vcpu_id,
  86                   uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
  87 {
  88         const struct xsave_limits *limits;
  89         uint64_t cr4;
  90         int error, enable_invpcid, level, width, x2apic_id;
  91         unsigned int func, regs[4], logical_cpus;
  92         enum x2apic_state x2apic_state;
  93
  94         /*
  95          * Requests for invalid CPUID levels should map to the highest
  96          * available level instead.
  97          */
  98         if (cpu_exthigh != 0 && *eax >= 0x80000000) {
  99                 if (*eax > cpu_exthigh)
 100                         *eax = cpu_exthigh;
 101         } else if (*eax >= 0x40000000) {
 102                 if (*eax > CPUID_VM_HIGH)
 103                         *eax = CPUID_VM_HIGH;
 104         } else if (*eax > cpu_high) {
 105                 *eax = cpu_high;
 106         }
 107
 108         func = *eax;
 109
 110         /*
 111          * In general the approach used for CPU topology is to
 112          * advertise a flat topology where all CPUs are packages with
 113          * no multi-core or SMT.
 114          */
 115         switch (func) {
 116                 /*
 117                  * Pass these through to the guest
 118                  */
 119                 case CPUID_0000_0000:
 120                 case CPUID_0000_0002:
 121                 case CPUID_0000_0003:
 122                 case CPUID_8000_0000:
 123                 case CPUID_8000_0002:
 124                 case CPUID_8000_0003:
 125                 case CPUID_8000_0004:
 126                 case CPUID_8000_0006:
 127                 case CPUID_8000_0008:
 128                         cpuid_count(*eax, *ecx, regs);
 129                         break;
 130
 131                 case CPUID_8000_0001:
 132                         /* Hide SVM capability from guest. */
 133                         regs[2] &= ~AMDID2_SVM;
 134                         /*
 135                          * Hide rdtscp/ia32_tsc_aux until we know how
 136                          * to deal with them.
 137                          */
 138                         cpuid_count(*eax, *ecx, regs);
 139                         regs[3] &= ~AMDID_RDTSCP;
 140                         break;
 141
 142                 case CPUID_8000_0007:
 143                         cpuid_count(*eax, *ecx, regs);
 144                         /*
 145                          * If the host TSCs are not synchronized across
 146                          * physical cpus then we cannot advertise an
 147                          * invariant tsc to a vcpu.
 148                          *
 149                          * XXX This still falls short because the vcpu
 150                          * can observe the TSC moving backwards as it
 151                          * migrates across physical cpus. But at least
 152                          * it should discourage the guest from using the
 153                          * TSC to keep track of time.
 154                          */
 155                         if (!smp_tsc)
 156                                 regs[3] &= ~AMDPM_TSC_INVARIANT;
 157                         break;
 158
 159                 case CPUID_0000_0001:
 160                         do_cpuid(1, regs);
 161
 162                         error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state);
 163                         if (error) {
 164                                 panic("x86_emulate_cpuid: error %d "
 165                                       "fetching x2apic state", error);
 166                         }
 167
 168                         /*
 169                          * Override the APIC ID only in ebx
 170                          */
 171                         regs[1] &= ~(CPUID_LOCAL_APIC_ID);
 172                         regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
 173
 174                         /*
 175                          * Don't expose VMX, SpeedStep or TME capability.
 176                          * Advertise x2APIC capability and Hypervisor guest.
 177                          */
 178                         regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
 179
 180                         regs[2] |= CPUID2_HV;
 181
 182                         if (x2apic_state != X2APIC_DISABLED)
 183                                 regs[2] |= CPUID2_X2APIC;
 184                         else
 185                                 regs[2] &= ~CPUID2_X2APIC;
 186
 187                         /*
 188                          * Only advertise CPUID2_XSAVE in the guest if
 189                          * the host is using XSAVE.
 190                          */
 191                         if (!(regs[2] & CPUID2_OSXSAVE))
 192                                 regs[2] &= ~CPUID2_XSAVE;
 193
 194                         /*
 195                          * If CPUID2_XSAVE is being advertised and the
 196                          * guest has set CR4_XSAVE, set
 197                          * CPUID2_OSXSAVE.
 198                          */
 199                         regs[2] &= ~CPUID2_OSXSAVE;
 200                         if (regs[2] & CPUID2_XSAVE) {
 201                                 error = vm_get_register(vm, vcpu_id,
 202                                     VM_REG_GUEST_CR4, &cr4);
 203                                 if (error)
 204                                         panic("x86_emulate_cpuid: error %d "
 205                                               "fetching %%cr4", error);
 206                                 if (cr4 & CR4_XSAVE)
 207                                         regs[2] |= CPUID2_OSXSAVE;
 208                         }
 209
 210                         /*
 211                          * Hide monitor/mwait until we know how to deal with
 212                          * these instructions.
 213                          */
 214                         regs[2] &= ~CPUID2_MON;
 215
 216                         /*
 217                          * Hide the performance and debug features.
 218                          */
 219                         regs[2] &= ~CPUID2_PDCM;
 220
 221                         /*
 222                          * No TSC deadline support in the APIC yet
 223                          */
 224                         regs[2] &= ~CPUID2_TSCDLT;
 225
 226                         /*
 227                          * Hide thermal monitoring
 228                          */
 229                         regs[3] &= ~(CPUID_ACPI | CPUID_TM);
 230
 231                         /*
 232                          * Machine check handling is done in the host.
 233                          * Hide MTRR capability.
 234                          */
 235                         regs[3] &= ~(CPUID_MCA | CPUID_MCE | CPUID_MTRR);
 236
 237                         /*
 238                         * Hide the debug store capability.
 239                         */
 240                         regs[3] &= ~CPUID_DS;
 241
 242                         logical_cpus = threads_per_core * cores_per_package;
 243                         regs[1] &= ~CPUID_HTT_CORES;
 244                         regs[1] |= (logical_cpus & 0xff) << 16;
 245                         regs[3] |= CPUID_HTT;
 246                         break;
 247
 248                 case CPUID_0000_0004:
 249                         cpuid_count(*eax, *ecx, regs);
 250
 251                         if (regs[0] || regs[1] || regs[2] || regs[3]) {
 252                                 regs[0] &= 0x3ff;
 253                                 regs[0] |= (cores_per_package - 1) << 26;
 254                                 /*
 255                                  * Cache topology:
 256                                  * - L1 and L2 are shared only by the logical
 257                                  *   processors in a single core.
 258                                  * - L3 and above are shared by all logical
 259                                  *   processors in the package.
 260                                  */
 261                                 logical_cpus = threads_per_core;
 262                                 level = (regs[0] >> 5) & 0x7;
 263                                 if (level >= 3)
 264                                         logical_cpus *= cores_per_package;
 265                                 regs[0] |= (logical_cpus - 1) << 14;
 266                         }
 267                         break;
 268
 269                 case CPUID_0000_0007:
 270                         regs[0] = 0;
 271                         regs[1] = 0;
 272                         regs[2] = 0;
 273                         regs[3] = 0;
 274
 275                         /* leaf 0 */
 276                         if (*ecx == 0) {
 277                                 cpuid_count(*eax, *ecx, regs);
 278
 279                                 /* Only leaf 0 is supported */
 280                                 regs[0] = 0;
 281
 282                                 /*
 283                                  * Expose known-safe features.
 284                                  */
 285                                 regs[1] &= (CPUID_STDEXT_FSGSBASE |
 286                                     CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
 287                                     CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 |
 288                                     CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
 289                                     CPUID_STDEXT_AVX512F |
 290                                     CPUID_STDEXT_AVX512PF |
 291                                     CPUID_STDEXT_AVX512ER |
 292                                     CPUID_STDEXT_AVX512CD);
 293                                 regs[2] = 0;
 294                                 regs[3] = 0;
 295
 296                                 /* Advertise INVPCID if it is enabled. */
 297                                 error = vm_get_capability(vm, vcpu_id,
 298                                     VM_CAP_ENABLE_INVPCID, &enable_invpcid);
 299                                 if (error == 0 && enable_invpcid)
 300                                         regs[1] |= CPUID_STDEXT_INVPCID;
 301                         }
 302                         break;
 303
 304                 case CPUID_0000_0006:
 305                 case CPUID_0000_000A:
 306                         /*
 307                          * Handle the access, but report 0 for
 308                          * all options
 309                          */
 310                         regs[0] = 0;
 311                         regs[1] = 0;
 312                         regs[2] = 0;
 313                         regs[3] = 0;
 314                         break;
 315
 316                 case CPUID_0000_000B:
 317                         /*
 318                          * Processor topology enumeration
 319                          */
 320                         if (*ecx == 0) {
 321                                 logical_cpus = threads_per_core;
 322                                 width = log2(logical_cpus);
 323                                 level = CPUID_TYPE_SMT;
 324                                 x2apic_id = vcpu_id;
 325                         }
 326
 327                         if (*ecx == 1) {
 328                                 logical_cpus = threads_per_core *
 329                                     cores_per_package;
 330                                 width = log2(logical_cpus);
 331                                 level = CPUID_TYPE_CORE;
 332                                 x2apic_id = vcpu_id;
 333                         }
 334
 335                         if (!cpuid_leaf_b || *ecx >= 2) {
 336                                 width = 0;
 337                                 logical_cpus = 0;
 338                                 level = 0;
 339                                 x2apic_id = 0;
 340                         }
 341
 342                         regs[0] = width & 0x1f;
 343                         regs[1] = logical_cpus & 0xffff;
 344                         regs[2] = (level << 8) | (*ecx & 0xff);
 345                         regs[3] = x2apic_id;
 346                         break;
 347
 348                 case CPUID_0000_000D:
 349                         limits = vmm_get_xsave_limits();
 350                         if (!limits->xsave_enabled) {
 351                                 regs[0] = 0;
 352                                 regs[1] = 0;
 353                                 regs[2] = 0;
 354                                 regs[3] = 0;
 355                                 break;
 356                         }
 357
 358                         cpuid_count(*eax, *ecx, regs);
 359                         switch (*ecx) {
 360                         case 0:
 361                                 /*
 362                                  * Only permit the guest to use bits
 363                                  * that are active in the host in
 364                                  * %xcr0.  Also, claim that the
 365                                  * maximum save area size is
 366                                  * equivalent to the host's current
 367                                  * save area size.  Since this runs
 368                                  * "inside" of vmrun(), it runs with
 369                                  * the guest's xcr0, so the current
 370                                  * save area size is correct as-is.
 371                                  */
 372                                 regs[0] &= limits->xcr0_allowed;
 373                                 regs[2] = limits->xsave_max_size;
 374                                 regs[3] &= (limits->xcr0_allowed >> 32);
 375                                 break;
 376                         case 1:
 377                                 /* Only permit XSAVEOPT. */
 378                                 regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
 379                                 regs[1] = 0;
 380                                 regs[2] = 0;
 381                                 regs[3] = 0;
 382                                 break;
 383                         default:
 384                                 /*
 385                                  * If the leaf is for a permitted feature,
 386                                  * pass through as-is, otherwise return
 387                                  * all zeroes.
 388                                  */
 389                                 if (!(limits->xcr0_allowed & (1ul << *ecx))) {
 390                                         regs[0] = 0;
 391                                         regs[1] = 0;
 392                                         regs[2] = 0;
 393                                         regs[3] = 0;
 394                                 }
 395                                 break;
 396                         }
 397                         break;
 398
 399                 case 0x40000000:
 400                         regs[0] = CPUID_VM_HIGH;
 401                         bcopy(bhyve_id, &regs[1], 4);
 402                         bcopy(bhyve_id + 4, &regs[2], 4);
 403                         bcopy(bhyve_id + 8, &regs[3], 4);
 404                         break;
 405
 406                 default:
 407                         /*
 408                          * The leaf value has already been clamped so
 409                          * simply pass this through, keeping count of
 410                          * how many unhandled leaf values have been seen.
 411                          */
 412                         atomic_add_long(&bhyve_xcpuids, 1);
 413                         cpuid_count(*eax, *ecx, regs);
 414                         break;
 415         }
 416
 417         *eax = regs[0];
 418         *ebx = regs[1];
 419         *ecx = regs[2];
 420         *edx = regs[3];
 421
 422         return (1);
 423 }