sys/amd64/vmm/x86.c

   1 /*-
   2  * Copyright (c) 2011 NetApp, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/pcpu.h>
  34 #include <sys/systm.h>
  35 #include <sys/cpuset.h>
  36
  37 #include <machine/clock.h>
  38 #include <machine/cpufunc.h>
  39 #include <machine/md_var.h>
  40 #include <machine/segments.h>
  41 #include <machine/specialreg.h>
  42
  43 #include <machine/vmm.h>
  44
  45 #include "vmm_host.h"
  46 #include "x86.h"
  47
  48 #define CPUID_VM_HIGH           0x40000000
  49
  50 static const char bhyve_id[12] = "bhyve bhyve ";
  51
  52 static uint64_t bhyve_xcpuids;
  53
  54 int
  55 x86_emulate_cpuid(struct vm *vm, int vcpu_id,
  56                   uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
  57 {
  58         const struct xsave_limits *limits;
  59         uint64_t cr4;
  60         int error, enable_invpcid;
  61         unsigned int    func, regs[4];
  62         enum x2apic_state x2apic_state;
  63
  64         /*
  65          * Requests for invalid CPUID levels should map to the highest
  66          * available level instead.
  67          */
  68         if (cpu_exthigh != 0 && *eax >= 0x80000000) {
  69                 if (*eax > cpu_exthigh)
  70                         *eax = cpu_exthigh;
  71         } else if (*eax >= 0x40000000) {
  72                 if (*eax > CPUID_VM_HIGH)
  73                         *eax = CPUID_VM_HIGH;
  74         } else if (*eax > cpu_high) {
  75                 *eax = cpu_high;
  76         }
  77
  78         func = *eax;
  79
  80         /*
  81          * In general the approach used for CPU topology is to
  82          * advertise a flat topology where all CPUs are packages with
  83          * no multi-core or SMT.
  84          */
  85         switch (func) {
  86                 /*
  87                  * Pass these through to the guest
  88                  */
  89                 case CPUID_0000_0000:
  90                 case CPUID_0000_0002:
  91                 case CPUID_0000_0003:
  92                 case CPUID_8000_0000:
  93                 case CPUID_8000_0002:
  94                 case CPUID_8000_0003:
  95                 case CPUID_8000_0004:
  96                 case CPUID_8000_0006:
  97                 case CPUID_8000_0008:
  98                         cpuid_count(*eax, *ecx, regs);
  99                         break;
 100
 101                 case CPUID_8000_0001:
 102                         /* Hide SVM capability from guest. */
 103                         regs[2] &= ~AMDID2_SVM;
 104                         /*
 105                          * Hide rdtscp/ia32_tsc_aux until we know how
 106                          * to deal with them.
 107                          */
 108                         cpuid_count(*eax, *ecx, regs);
 109                         regs[3] &= ~AMDID_RDTSCP;
 110                         break;
 111
 112                 case CPUID_8000_0007:
 113                         cpuid_count(*eax, *ecx, regs);
 114                         /*
 115                          * If the host TSCs are not synchronized across
 116                          * physical cpus then we cannot advertise an
 117                          * invariant tsc to a vcpu.
 118                          *
 119                          * XXX This still falls short because the vcpu
 120                          * can observe the TSC moving backwards as it
 121                          * migrates across physical cpus. But at least
 122                          * it should discourage the guest from using the
 123                          * TSC to keep track of time.
 124                          */
 125                         if (!smp_tsc)
 126                                 regs[3] &= ~AMDPM_TSC_INVARIANT;
 127                         break;
 128
 129                 case CPUID_0000_0001:
 130                         do_cpuid(1, regs);
 131
 132                         error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state);
 133                         if (error) {
 134                                 panic("x86_emulate_cpuid: error %d "
 135                                       "fetching x2apic state", error);
 136                         }
 137
 138                         /*
 139                          * Override the APIC ID only in ebx
 140                          */
 141                         regs[1] &= ~(CPUID_LOCAL_APIC_ID);
 142                         regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
 143
 144                         /*
 145                          * Don't expose VMX, SpeedStep or TME capability.
 146                          * Advertise x2APIC capability and Hypervisor guest.
 147                          */
 148                         regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
 149
 150                         regs[2] |= CPUID2_HV;
 151
 152                         if (x2apic_state != X2APIC_DISABLED)
 153                                 regs[2] |= CPUID2_X2APIC;
 154                         else
 155                                 regs[2] &= ~CPUID2_X2APIC;
 156
 157                         /*
 158                          * Only advertise CPUID2_XSAVE in the guest if
 159                          * the host is using XSAVE.
 160                          */
 161                         if (!(regs[2] & CPUID2_OSXSAVE))
 162                                 regs[2] &= ~CPUID2_XSAVE;
 163
 164                         /*
 165                          * If CPUID2_XSAVE is being advertised and the
 166                          * guest has set CR4_XSAVE, set
 167                          * CPUID2_OSXSAVE.
 168                          */
 169                         regs[2] &= ~CPUID2_OSXSAVE;
 170                         if (regs[2] & CPUID2_XSAVE) {
 171                                 error = vm_get_register(vm, vcpu_id,
 172                                     VM_REG_GUEST_CR4, &cr4);
 173                                 if (error)
 174                                         panic("x86_emulate_cpuid: error %d "
 175                                               "fetching %%cr4", error);
 176                                 if (cr4 & CR4_XSAVE)
 177                                         regs[2] |= CPUID2_OSXSAVE;
 178                         }
 179
 180                         /*
 181                          * Hide monitor/mwait until we know how to deal with
 182                          * these instructions.
 183                          */
 184                         regs[2] &= ~CPUID2_MON;
 185
 186                         /*
 187                          * Hide the performance and debug features.
 188                          */
 189                         regs[2] &= ~CPUID2_PDCM;
 190
 191                         /*
 192                          * No TSC deadline support in the APIC yet
 193                          */
 194                         regs[2] &= ~CPUID2_TSCDLT;
 195
 196                         /*
 197                          * Hide thermal monitoring
 198                          */
 199                         regs[3] &= ~(CPUID_ACPI | CPUID_TM);
 200
 201                         /*
 202                          * Machine check handling is done in the host.
 203                          * Hide MTRR capability.
 204                          */
 205                         regs[3] &= ~(CPUID_MCA | CPUID_MCE | CPUID_MTRR);
 206
 207                         /*
 208                         * Hide the debug store capability.
 209                         */
 210                         regs[3] &= ~CPUID_DS;
 211
 212                         /*
 213                          * Disable multi-core.
 214                          */
 215                         regs[1] &= ~CPUID_HTT_CORES;
 216                         regs[3] &= ~CPUID_HTT;
 217                         break;
 218
 219                 case CPUID_0000_0004:
 220                         do_cpuid(4, regs);
 221
 222                         /*
 223                          * Do not expose topology.
 224                          *
 225                          * The maximum number of processor cores in
 226                          * this physical processor package and the
 227                          * maximum number of threads sharing this
 228                          * cache are encoded with "plus 1" encoding.
 229                          * Adding one to the value in this register
 230                          * field to obtains the actual value.
 231                          *
 232                          * Therefore 0 for both indicates 1 core per
 233                          * package and no cache sharing.
 234                          */
 235                         regs[0] &= 0xffff8000;
 236                         break;
 237
 238                 case CPUID_0000_0007:
 239                         regs[0] = 0;
 240                         regs[1] = 0;
 241                         regs[2] = 0;
 242                         regs[3] = 0;
 243
 244                         /* leaf 0 */
 245                         if (*ecx == 0) {
 246                                 cpuid_count(*eax, *ecx, regs);
 247
 248                                 /* Only leaf 0 is supported */
 249                                 regs[0] = 0;
 250
 251                                 /*
 252                                  * Expose known-safe features.
 253                                  */
 254                                 regs[1] &= (CPUID_STDEXT_FSGSBASE |
 255                                     CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
 256                                     CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 |
 257                                     CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
 258                                     CPUID_STDEXT_AVX512F |
 259                                     CPUID_STDEXT_AVX512PF |
 260                                     CPUID_STDEXT_AVX512ER |
 261                                     CPUID_STDEXT_AVX512CD);
 262                                 regs[2] = 0;
 263                                 regs[3] = 0;
 264
 265                                 /* Advertise INVPCID if it is enabled. */
 266                                 error = vm_get_capability(vm, vcpu_id,
 267                                     VM_CAP_ENABLE_INVPCID, &enable_invpcid);
 268                                 if (error == 0 && enable_invpcid)
 269                                         regs[1] |= CPUID_STDEXT_INVPCID;
 270                         }
 271                         break;
 272
 273                 case CPUID_0000_0006:
 274                 case CPUID_0000_000A:
 275                         /*
 276                          * Handle the access, but report 0 for
 277                          * all options
 278                          */
 279                         regs[0] = 0;
 280                         regs[1] = 0;
 281                         regs[2] = 0;
 282                         regs[3] = 0;
 283                         break;
 284
 285                 case CPUID_0000_000B:
 286                         /*
 287                          * Processor topology enumeration
 288                          */
 289                         regs[0] = 0;
 290                         regs[1] = 0;
 291                         regs[2] = *ecx & 0xff;
 292                         regs[3] = vcpu_id;
 293                         break;
 294
 295                 case CPUID_0000_000D:
 296                         limits = vmm_get_xsave_limits();
 297                         if (!limits->xsave_enabled) {
 298                                 regs[0] = 0;
 299                                 regs[1] = 0;
 300                                 regs[2] = 0;
 301                                 regs[3] = 0;
 302                                 break;
 303                         }
 304
 305                         cpuid_count(*eax, *ecx, regs);
 306                         switch (*ecx) {
 307                         case 0:
 308                                 /*
 309                                  * Only permit the guest to use bits
 310                                  * that are active in the host in
 311                                  * %xcr0.  Also, claim that the
 312                                  * maximum save area size is
 313                                  * equivalent to the host's current
 314                                  * save area size.  Since this runs
 315                                  * "inside" of vmrun(), it runs with
 316                                  * the guest's xcr0, so the current
 317                                  * save area size is correct as-is.
 318                                  */
 319                                 regs[0] &= limits->xcr0_allowed;
 320                                 regs[2] = limits->xsave_max_size;
 321                                 regs[3] &= (limits->xcr0_allowed >> 32);
 322                                 break;
 323                         case 1:
 324                                 /* Only permit XSAVEOPT. */
 325                                 regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
 326                                 regs[1] = 0;
 327                                 regs[2] = 0;
 328                                 regs[3] = 0;
 329                                 break;
 330                         default:
 331                                 /*
 332                                  * If the leaf is for a permitted feature,
 333                                  * pass through as-is, otherwise return
 334                                  * all zeroes.
 335                                  */
 336                                 if (!(limits->xcr0_allowed & (1ul << *ecx))) {
 337                                         regs[0] = 0;
 338                                         regs[1] = 0;
 339                                         regs[2] = 0;
 340                                         regs[3] = 0;
 341                                 }
 342                                 break;
 343                         }
 344                         break;
 345
 346                 case 0x40000000:
 347                         regs[0] = CPUID_VM_HIGH;
 348                         bcopy(bhyve_id, &regs[1], 4);
 349                         bcopy(bhyve_id + 4, &regs[2], 4);
 350                         bcopy(bhyve_id + 8, &regs[3], 4);
 351                         break;
 352
 353                 default:
 354                         /*
 355                          * The leaf value has already been clamped so
 356                          * simply pass this through, keeping count of
 357                          * how many unhandled leaf values have been seen.
 358                          */
 359                         atomic_add_long(&bhyve_xcpuids, 1);
 360                         cpuid_count(*eax, *ecx, regs);
 361                         break;
 362         }
 363
 364         *eax = regs[0];
 365         *ebx = regs[1];
 366         *ecx = regs[2];
 367         *edx = regs[3];
 368
 369         return (1);
 370 }