sys/amd64/vmm/x86.c

   1 /*-
   2  * Copyright (c) 2011 NetApp, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/pcpu.h>
  34 #include <sys/systm.h>
  35 #include <sys/cpuset.h>
  36
  37 #include <machine/clock.h>
  38 #include <machine/cpufunc.h>
  39 #include <machine/md_var.h>
  40 #include <machine/segments.h>
  41 #include <machine/specialreg.h>
  42
  43 #include <machine/vmm.h>
  44
  45 #include "vmm_host.h"
  46 #include "x86.h"
  47
  48 #define CPUID_VM_HIGH           0x40000000
  49
  50 static const char bhyve_id[12] = "bhyve bhyve ";
  51
  52 static uint64_t bhyve_xcpuids;
  53
  54 int
  55 x86_emulate_cpuid(struct vm *vm, int vcpu_id,
  56                   uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
  57 {
  58         const struct xsave_limits *limits;
  59         uint64_t cr4;
  60         int error, enable_invpcid;
  61         unsigned int    func, regs[4];
  62         enum x2apic_state x2apic_state;
  63
  64         /*
  65          * Requests for invalid CPUID levels should map to the highest
  66          * available level instead.
  67          */
  68         if (cpu_exthigh != 0 && *eax >= 0x80000000) {
  69                 if (*eax > cpu_exthigh)
  70                         *eax = cpu_exthigh;
  71         } else if (*eax >= 0x40000000) {
  72                 if (*eax > CPUID_VM_HIGH)
  73                         *eax = CPUID_VM_HIGH;
  74         } else if (*eax > cpu_high) {
  75                 *eax = cpu_high;
  76         }
  77
  78         func = *eax;
  79
  80         /*
  81          * In general the approach used for CPU topology is to
  82          * advertise a flat topology where all CPUs are packages with
  83          * no multi-core or SMT.
  84          */
  85         switch (func) {
  86                 /*
  87                  * Pass these through to the guest
  88                  */
  89                 case CPUID_0000_0000:
  90                 case CPUID_0000_0002:
  91                 case CPUID_0000_0003:
  92                 case CPUID_8000_0000:
  93                 case CPUID_8000_0002:
  94                 case CPUID_8000_0003:
  95                 case CPUID_8000_0004:
  96                 case CPUID_8000_0006:
  97                 case CPUID_8000_0008:
  98                         cpuid_count(*eax, *ecx, regs);
  99                         break;
 100
 101                 case CPUID_8000_0001:
 102                         /*
 103                          * Hide rdtscp/ia32_tsc_aux until we know how
 104                          * to deal with them.
 105                          */
 106                         cpuid_count(*eax, *ecx, regs);
 107                         regs[3] &= ~AMDID_RDTSCP;
 108                         break;
 109
 110                 case CPUID_8000_0007:
 111                         cpuid_count(*eax, *ecx, regs);
 112                         /*
 113                          * If the host TSCs are not synchronized across
 114                          * physical cpus then we cannot advertise an
 115                          * invariant tsc to a vcpu.
 116                          *
 117                          * XXX This still falls short because the vcpu
 118                          * can observe the TSC moving backwards as it
 119                          * migrates across physical cpus. But at least
 120                          * it should discourage the guest from using the
 121                          * TSC to keep track of time.
 122                          */
 123                         if (!smp_tsc)
 124                                 regs[3] &= ~AMDPM_TSC_INVARIANT;
 125                         break;
 126
 127                 case CPUID_0000_0001:
 128                         do_cpuid(1, regs);
 129
 130                         error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state);
 131                         if (error) {
 132                                 panic("x86_emulate_cpuid: error %d "
 133                                       "fetching x2apic state", error);
 134                         }
 135
 136                         /*
 137                          * Override the APIC ID only in ebx
 138                          */
 139                         regs[1] &= ~(CPUID_LOCAL_APIC_ID);
 140                         regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
 141
 142                         /*
 143                          * Don't expose VMX, SpeedStep or TME capability.
 144                          * Advertise x2APIC capability and Hypervisor guest.
 145                          */
 146                         regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
 147
 148                         regs[2] |= CPUID2_HV;
 149
 150                         if (x2apic_state != X2APIC_DISABLED)
 151                                 regs[2] |= CPUID2_X2APIC;
 152                         else
 153                                 regs[2] &= ~CPUID2_X2APIC;
 154
 155                         /*
 156                          * Only advertise CPUID2_XSAVE in the guest if
 157                          * the host is using XSAVE.
 158                          */
 159                         if (!(regs[2] & CPUID2_OSXSAVE))
 160                                 regs[2] &= ~CPUID2_XSAVE;
 161
 162                         /*
 163                          * If CPUID2_XSAVE is being advertised and the
 164                          * guest has set CR4_XSAVE, set
 165                          * CPUID2_OSXSAVE.
 166                          */
 167                         regs[2] &= ~CPUID2_OSXSAVE;
 168                         if (regs[2] & CPUID2_XSAVE) {
 169                                 error = vm_get_register(vm, vcpu_id,
 170                                     VM_REG_GUEST_CR4, &cr4);
 171                                 if (error)
 172                                         panic("x86_emulate_cpuid: error %d "
 173                                               "fetching %%cr4", error);
 174                                 if (cr4 & CR4_XSAVE)
 175                                         regs[2] |= CPUID2_OSXSAVE;
 176                         }
 177
 178                         /*
 179                          * Hide monitor/mwait until we know how to deal with
 180                          * these instructions.
 181                          */
 182                         regs[2] &= ~CPUID2_MON;
 183
 184                         /*
 185                          * Hide the performance and debug features.
 186                          */
 187                         regs[2] &= ~CPUID2_PDCM;
 188
 189                         /*
 190                          * No TSC deadline support in the APIC yet
 191                          */
 192                         regs[2] &= ~CPUID2_TSCDLT;
 193
 194                         /*
 195                          * Hide thermal monitoring
 196                          */
 197                         regs[3] &= ~(CPUID_ACPI | CPUID_TM);
 198
 199                         /*
 200                          * Machine check handling is done in the host.
 201                          * Hide MTRR capability.
 202                          */
 203                         regs[3] &= ~(CPUID_MCA | CPUID_MCE | CPUID_MTRR);
 204
 205                         /*
 206                         * Hide the debug store capability.
 207                         */
 208                         regs[3] &= ~CPUID_DS;
 209
 210                         /*
 211                          * Disable multi-core.
 212                          */
 213                         regs[1] &= ~CPUID_HTT_CORES;
 214                         regs[3] &= ~CPUID_HTT;
 215                         break;
 216
 217                 case CPUID_0000_0004:
 218                         do_cpuid(4, regs);
 219
 220                         /*
 221                          * Do not expose topology.
 222                          */
 223                         regs[0] &= 0xffff8000;
 224                         regs[0] |= 0x04008000;
 225                         break;
 226
 227                 case CPUID_0000_0007:
 228                         regs[0] = 0;
 229                         regs[1] = 0;
 230                         regs[2] = 0;
 231                         regs[3] = 0;
 232
 233                         /* leaf 0 */
 234                         if (*ecx == 0) {
 235                                 cpuid_count(*eax, *ecx, regs);
 236
 237                                 /* Only leaf 0 is supported */
 238                                 regs[0] = 0;
 239
 240                                 /*
 241                                  * Expose known-safe features.
 242                                  */
 243                                 regs[1] &= (CPUID_STDEXT_FSGSBASE |
 244                                     CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
 245                                     CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 |
 246                                     CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
 247                                     CPUID_STDEXT_AVX512F |
 248                                     CPUID_STDEXT_AVX512PF |
 249                                     CPUID_STDEXT_AVX512ER |
 250                                     CPUID_STDEXT_AVX512CD);
 251                                 regs[2] = 0;
 252                                 regs[3] = 0;
 253
 254                                 /* Advertise INVPCID if it is enabled. */
 255                                 error = vm_get_capability(vm, vcpu_id,
 256                                     VM_CAP_ENABLE_INVPCID, &enable_invpcid);
 257                                 if (error == 0 && enable_invpcid)
 258                                         regs[1] |= CPUID_STDEXT_INVPCID;
 259                         }
 260                         break;
 261
 262                 case CPUID_0000_0006:
 263                 case CPUID_0000_000A:
 264                         /*
 265                          * Handle the access, but report 0 for
 266                          * all options
 267                          */
 268                         regs[0] = 0;
 269                         regs[1] = 0;
 270                         regs[2] = 0;
 271                         regs[3] = 0;
 272                         break;
 273
 274                 case CPUID_0000_000B:
 275                         /*
 276                          * Processor topology enumeration
 277                          */
 278                         regs[0] = 0;
 279                         regs[1] = 0;
 280                         regs[2] = *ecx & 0xff;
 281                         regs[3] = vcpu_id;
 282                         break;
 283
 284                 case CPUID_0000_000D:
 285                         limits = vmm_get_xsave_limits();
 286                         if (!limits->xsave_enabled) {
 287                                 regs[0] = 0;
 288                                 regs[1] = 0;
 289                                 regs[2] = 0;
 290                                 regs[3] = 0;
 291                                 break;
 292                         }
 293
 294                         cpuid_count(*eax, *ecx, regs);
 295                         switch (*ecx) {
 296                         case 0:
 297                                 /*
 298                                  * Only permit the guest to use bits
 299                                  * that are active in the host in
 300                                  * %xcr0.  Also, claim that the
 301                                  * maximum save area size is
 302                                  * equivalent to the host's current
 303                                  * save area size.  Since this runs
 304                                  * "inside" of vmrun(), it runs with
 305                                  * the guest's xcr0, so the current
 306                                  * save area size is correct as-is.
 307                                  */
 308                                 regs[0] &= limits->xcr0_allowed;
 309                                 regs[2] = limits->xsave_max_size;
 310                                 regs[3] &= (limits->xcr0_allowed >> 32);
 311                                 break;
 312                         case 1:
 313                                 /* Only permit XSAVEOPT. */
 314                                 regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
 315                                 regs[1] = 0;
 316                                 regs[2] = 0;
 317                                 regs[3] = 0;
 318                                 break;
 319                         default:
 320                                 /*
 321                                  * If the leaf is for a permitted feature,
 322                                  * pass through as-is, otherwise return
 323                                  * all zeroes.
 324                                  */
 325                                 if (!(limits->xcr0_allowed & (1ul << *ecx))) {
 326                                         regs[0] = 0;
 327                                         regs[1] = 0;
 328                                         regs[2] = 0;
 329                                         regs[3] = 0;
 330                                 }
 331                                 break;
 332                         }
 333                         break;
 334
 335                 case 0x40000000:
 336                         regs[0] = CPUID_VM_HIGH;
 337                         bcopy(bhyve_id, &regs[1], 4);
 338                         bcopy(bhyve_id + 4, &regs[2], 4);
 339                         bcopy(bhyve_id + 8, &regs[3], 4);
 340                         break;
 341
 342                 default:
 343                         /*
 344                          * The leaf value has already been clamped so
 345                          * simply pass this through, keeping count of
 346                          * how many unhandled leaf values have been seen.
 347                          */
 348                         atomic_add_long(&bhyve_xcpuids, 1);
 349                         cpuid_count(*eax, *ecx, regs);
 350                         break;
 351         }
 352
 353         *eax = regs[0];
 354         *ebx = regs[1];
 355         *ecx = regs[2];
 356         *edx = regs[3];
 357
 358         return (1);
 359 }