2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_platform.h"
33 #include <sys/types.h>
35 #include <sys/cpuset.h>
36 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/sched.h>
49 #include <machine/bus.h>
50 #include <machine/intr.h>
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
62 * Interrupt controller registers
65 #define SW_INT_VECTOR_REG 0x00
66 #define SW_INT_BASE_ADR_REG 0x04
67 #define SW_INT_PROTECTION_REG 0x08
68 #define SW_INT_NMI_CTRL_REG 0x0c
70 #define SW_INT_IRQ_PENDING_REG0 0x10
71 #define SW_INT_IRQ_PENDING_REG1 0x14
72 #define SW_INT_IRQ_PENDING_REG2 0x18
74 #define SW_INT_FIQ_PENDING_REG0 0x20
75 #define SW_INT_FIQ_PENDING_REG1 0x24
76 #define SW_INT_FIQ_PENDING_REG2 0x28
78 #define SW_INT_SELECT_REG0 0x30
79 #define SW_INT_SELECT_REG1 0x34
80 #define SW_INT_SELECT_REG2 0x38
82 #define SW_INT_ENABLE_REG0 0x40
83 #define SW_INT_ENABLE_REG1 0x44
84 #define SW_INT_ENABLE_REG2 0x48
86 #define SW_INT_MASK_REG0 0x50
87 #define SW_INT_MASK_REG1 0x54
88 #define SW_INT_MASK_REG2 0x58
90 #define SW_INT_IRQNO_ENMI 0
92 #define A10_INTR_MAX_NIRQS 81
94 #define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
95 #define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
96 #define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
97 #define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
98 #define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))
101 struct a10_intr_irqsrc {
102 struct intr_irqsrc isrc;
107 struct a10_aintc_softc {
109 struct resource * aintc_res;
110 bus_space_tag_t aintc_bst;
111 bus_space_handle_t aintc_bsh;
114 struct a10_intr_irqsrc isrcs[A10_INTR_MAX_NIRQS];
118 #define aintc_read_4(sc, reg) \
119 bus_space_read_4(sc->aintc_bst, sc->aintc_bsh, reg)
120 #define aintc_write_4(sc, reg, val) \
121 bus_space_write_4(sc->aintc_bst, sc->aintc_bsh, reg, val)
124 a10_intr_eoi(struct a10_aintc_softc *sc, u_int irq)
127 if (irq != SW_INT_IRQNO_ENMI)
129 mtx_lock_spin(&sc->mtx);
130 aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0),
131 (1 << SW_INT_IRQNO_ENMI));
132 mtx_unlock_spin(&sc->mtx);
136 a10_intr_unmask(struct a10_aintc_softc *sc, u_int irq)
138 uint32_t bit, block, value;
143 mtx_lock_spin(&sc->mtx);
144 value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
146 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);
148 value = aintc_read_4(sc, SW_INT_MASK_REG(block));
149 value &= ~(1 << bit);
150 aintc_write_4(sc, SW_INT_MASK_REG(block), value);
151 mtx_unlock_spin(&sc->mtx);
155 a10_intr_mask(struct a10_aintc_softc *sc, u_int irq)
157 uint32_t bit, block, value;
162 mtx_lock_spin(&sc->mtx);
163 value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
164 value &= ~(1 << bit);
165 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);
167 value = aintc_read_4(sc, SW_INT_MASK_REG(block));
169 aintc_write_4(sc, SW_INT_MASK_REG(block), value);
170 mtx_unlock_spin(&sc->mtx);
174 a10_pending_irq(struct a10_aintc_softc *sc)
179 for (i = 0; i < 3; i++) {
180 value = aintc_read_4(sc, SW_INT_IRQ_PENDING_REG(i));
183 for (b = 0; b < 32; b++)
184 if (value & (1 << b)) {
194 static struct a10_aintc_softc *a10_aintc_sc = NULL;
197 arm_get_next_irq(int last_irq)
199 return (a10_pending_irq(a10_aintc_sc));
203 arm_mask_irq(uintptr_t irq)
205 a10_intr_mask(a10_aintc_sc, irq);
209 arm_unmask_irq(uintptr_t irq)
211 a10_intr_unmask(a10_aintc_sc, irq);
212 a10_intr_eoi(a10_aintc_sc, irq);
220 struct a10_aintc_softc *sc = arg;
223 irq = a10_pending_irq(sc);
224 if (irq == -1 || irq > A10_INTR_MAX_NIRQS) {
225 device_printf(sc->sc_dev, "Spurious interrupt %d\n", irq);
226 return (FILTER_HANDLED);
230 if (irq > A10_INTR_MAX_NIRQS) {
231 device_printf(sc->sc_dev, "Spurious interrupt %d\n",
233 return (FILTER_HANDLED);
235 if (intr_isrc_dispatch(&sc->isrcs[irq].isrc,
236 curthread->td_intr_frame) != 0) {
237 a10_intr_mask(sc, irq);
238 a10_intr_eoi(sc, irq);
239 device_printf(sc->sc_dev,
240 "Stray interrupt %d disabled\n", irq);
243 arm_irq_memory_barrier(irq);
244 irq = a10_pending_irq(sc);
247 return (FILTER_HANDLED);
251 a10_intr_pic_attach(struct a10_aintc_softc *sc)
253 struct intr_pic *pic;
259 name = device_get_nameunit(sc->sc_dev);
260 for (irq = 0; irq < A10_INTR_MAX_NIRQS; irq++) {
261 sc->isrcs[irq].irq = irq;
263 error = intr_isrc_register(&sc->isrcs[irq].isrc,
264 sc->sc_dev, 0, "%s,%u", name, irq);
269 xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev));
270 pic = intr_pic_register(sc->sc_dev, xref);
274 return (intr_pic_claim_root(sc->sc_dev, xref, a10_intr, sc, 0));
278 a10_intr_enable_intr(device_t dev, struct intr_irqsrc *isrc)
280 struct a10_aintc_softc *sc;
281 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
283 sc = device_get_softc(dev);
284 arm_irq_memory_barrier(irq);
285 a10_intr_unmask(sc, irq);
289 a10_intr_disable_intr(device_t dev, struct intr_irqsrc *isrc)
291 struct a10_aintc_softc *sc;
292 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
294 sc = device_get_softc(dev);
295 a10_intr_mask(sc, irq);
299 a10_intr_map_intr(device_t dev, struct intr_map_data *data,
300 struct intr_irqsrc **isrcp)
302 struct intr_map_data_fdt *daf;
303 struct a10_aintc_softc *sc;
305 if (data->type != INTR_MAP_DATA_FDT)
308 daf = (struct intr_map_data_fdt *)data;
309 if (daf->ncells != 1 || daf->cells[0] >= A10_INTR_MAX_NIRQS)
312 sc = device_get_softc(dev);
313 *isrcp = &sc->isrcs[daf->cells[0]].isrc;
318 a10_intr_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
320 struct a10_aintc_softc *sc = device_get_softc(dev);
321 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
323 a10_intr_mask(sc, irq);
324 a10_intr_eoi(sc, irq);
328 a10_intr_post_ithread(device_t dev, struct intr_irqsrc *isrc)
331 a10_intr_enable_intr(dev, isrc);
335 a10_intr_post_filter(device_t dev, struct intr_irqsrc *isrc)
337 struct a10_aintc_softc *sc = device_get_softc(dev);
338 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
340 a10_intr_eoi(sc, irq);
346 a10_aintc_probe(device_t dev)
349 if (!ofw_bus_status_okay(dev))
352 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ic"))
354 device_set_desc(dev, "A10 AINTC Interrupt Controller");
355 return (BUS_PROBE_DEFAULT);
359 a10_aintc_attach(device_t dev)
361 struct a10_aintc_softc *sc = device_get_softc(dev);
373 sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
375 if (!sc->aintc_res) {
376 device_printf(dev, "could not allocate resource\n");
380 sc->aintc_bst = rman_get_bustag(sc->aintc_res);
381 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);
383 mtx_init(&sc->mtx, "A10 AINTC lock", "", MTX_SPIN);
385 /* Disable & clear all interrupts */
386 for (i = 0; i < 3; i++) {
387 aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0);
388 aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff);
390 /* enable protection mode*/
391 aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01);
393 /* config the external interrupt source type*/
394 aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00);
397 if (a10_intr_pic_attach(sc) != 0) {
398 device_printf(dev, "could not attach PIC\n");
406 bus_release_resource(dev, SYS_RES_MEMORY, rid,
411 static device_method_t a10_aintc_methods[] = {
412 DEVMETHOD(device_probe, a10_aintc_probe),
413 DEVMETHOD(device_attach, a10_aintc_attach),
415 /* Interrupt controller interface */
416 DEVMETHOD(pic_disable_intr, a10_intr_disable_intr),
417 DEVMETHOD(pic_enable_intr, a10_intr_enable_intr),
418 DEVMETHOD(pic_map_intr, a10_intr_map_intr),
419 DEVMETHOD(pic_post_filter, a10_intr_post_filter),
420 DEVMETHOD(pic_post_ithread, a10_intr_post_ithread),
421 DEVMETHOD(pic_pre_ithread, a10_intr_pre_ithread),
426 static driver_t a10_aintc_driver = {
429 sizeof(struct a10_aintc_softc),
432 static devclass_t a10_aintc_devclass;
434 EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0,
435 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST);