2 * Copyright (c) 2014-2015 M. Warner Losh <imp@freebsd.org>
3 * Copyright (c) 2015 Luiz Otavio O Souza <loos@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * The magic-bit-bang sequence used in this code may be based on a linux
28 * platform driver in the Allwinner SDK from Allwinner Technology Co., Ltd.
29 * www.allwinnertech.com, by Daniel Wang <danielwang@allwinnertech.com>
30 * though none of the original code was copied.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
45 #include <machine/bus.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/ahci/ahci.h>
50 #include <dev/extres/clk/clk.h>
53 * Allwinner a1x/a2x/a8x SATA attachment. This is just the AHCI register
54 * set with a few extra implementation-specific registers that need to
55 * be accounted for. There's only one PHY in the system, and it needs
56 * to be trained to bring the link up. In addition, there's some DMA
57 * specific things that need to be done as well. These things are also
58 * just about completely undocumented, except in ugly code in the Linux
59 * SDK Allwinner releases.
62 /* BITx -- Unknown bit that needs to be set/cleared at position x */
63 /* UFx -- Uknown multi-bit field frobbed during init */
64 #define AHCI_BISTAFR 0x00A0
65 #define AHCI_BISTCR 0x00A4
66 #define AHCI_BISTFCTR 0x00A8
67 #define AHCI_BISTSR 0x00AC
68 #define AHCI_BISTDECR 0x00B0
69 #define AHCI_DIAGNR 0x00B4
70 #define AHCI_DIAGNR1 0x00B8
71 #define AHCI_OOBR 0x00BC
72 #define AHCI_PHYCS0R 0x00C0
73 /* Bits 0..17 are a mystery */
74 #define PHYCS0R_BIT18 (1 << 18)
75 #define PHYCS0R_POWER_ENABLE (1 << 19)
76 #define PHYCS0R_UF1_MASK (7 << 20) /* Unknown Field 1 */
77 #define PHYCS0R_UF1_INIT (3 << 20)
78 #define PHYCS0R_BIT23 (1 << 23)
79 #define PHYCS0R_UF2_MASK (7 << 24) /* Uknown Field 2 */
80 #define PHYCS0R_UF2_INIT (5 << 24)
82 #define PHYCS0R_POWER_STATUS_MASK (7 << 28)
83 #define PHYCS0R_PS_GOOD (2 << 28)
85 #define AHCI_PHYCS1R 0x00C4
86 /* Bits 0..5 are a mystery */
87 #define PHYCS1R_UF1_MASK (3 << 6)
88 #define PHYCS1R_UF1_INIT (2 << 6)
89 #define PHYCS1R_UF2_MASK (0x1f << 8)
90 #define PHYCS1R_UF2_INIT (6 << 8)
91 /* Bits 13..14 are a mystery */
92 #define PHYCS1R_BIT15 (1 << 15)
93 #define PHYCS1R_UF3_MASK (3 << 16)
94 #define PHYCS1R_UF3_INIT (2 << 16)
96 #define PHYCS1R_HIGHZ (1 << 19)
97 /* Bits 20..27 mystery */
98 #define PHYCS1R_BIT28 (1 << 28)
99 /* Bits 29..31 mystery */
100 #define AHCI_PHYCS2R 0x00C8
101 /* bits 0..4 mystery */
102 #define PHYCS2R_UF1_MASK (0x1f << 5)
103 #define PHYCS2R_UF1_INIT (0x19 << 5)
104 /* Bits 10..23 mystery */
105 #define PHYCS2R_CALIBRATE (1 << 24)
106 /* Bits 25..31 mystery */
107 #define AHCI_TIMER1MS 0x00E0
108 #define AHCI_GPARAM1R 0x00E8
109 #define AHCI_GPARAM2R 0x00EC
110 #define AHCI_PPARAMR 0x00F0
111 #define AHCI_TESTR 0x00F4
112 #define AHCI_VERSIONR 0x00F8
113 #define AHCI_IDR 0x00FC
114 #define AHCI_RWCR 0x00FC
116 #define AHCI_P0DMACR 0x0070
117 #define AHCI_P0PHYCR 0x0078
118 #define AHCI_P0PHYSR 0x007C
120 #define PLL_FREQ 100000000
123 ahci_set(struct resource *m, bus_size_t off, uint32_t set)
125 uint32_t val = ATA_INL(m, off);
128 ATA_OUTL(m, off, val);
132 ahci_clr(struct resource *m, bus_size_t off, uint32_t clr)
134 uint32_t val = ATA_INL(m, off);
137 ATA_OUTL(m, off, val);
141 ahci_mask_set(struct resource *m, bus_size_t off, uint32_t mask, uint32_t set)
143 uint32_t val = ATA_INL(m, off);
147 ATA_OUTL(m, off, val);
151 * Should this be phy_reset or phy_init
153 #define PHY_RESET_TIMEOUT 1000
155 ahci_a10_phy_reset(device_t dev)
158 struct ahci_controller *ctlr = device_get_softc(dev);
161 * Here starts the magic -- most of the comments are based
162 * on guesswork, names of routines and printf error
163 * messages. The code works, but it will do that even if the
164 * comments are 100% BS.
168 * Lock out other access while we initialize. Or at least that
169 * seems to be the case based on Linux SDK #defines. Maybe this
170 * put things into reset?
172 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 0);
176 * Set bit 19 in PHYCS1R. Guessing this disables driving the PHY
177 * port for a bit while we reset things.
179 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
184 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
186 PHYCS0R_UF2_INIT | PHYCS0R_BIT23 | PHYCS0R_BIT18);
189 * Set three fields in PHYCS1R
191 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS1R,
192 ~(PHYCS1R_UF1_MASK | PHYCS1R_UF2_MASK | PHYCS1R_UF3_MASK),
193 PHYCS1R_UF1_INIT | PHYCS1R_UF2_INIT | PHYCS1R_UF3_INIT);
196 * Two more mystery bits in PHYCS1R. -- can these be combined above?
198 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_BIT15 | PHYCS1R_BIT28);
201 * Now clear that first mysery bit. Perhaps this starts
202 * driving the PHY again so we can power it up and start
203 * talking to the SATA drive, if any below.
205 ahci_clr(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
208 * Frob PHYCS0R again...
210 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
211 ~PHYCS0R_UF1_MASK, PHYCS0R_UF1_INIT);
214 * Frob PHYCS2R, because 25 means something?
216 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS2R, ~PHYCS2R_UF1_MASK,
219 DELAY(100); /* WAG */
222 * Turn on the power to the PHY and wait for it to report back
225 ahci_set(ctlr->r_mem, AHCI_PHYCS0R, PHYCS0R_POWER_ENABLE);
226 for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
227 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R);
228 if ((val & PHYCS0R_POWER_STATUS_MASK) == PHYCS0R_PS_GOOD)
232 if (to == 0 && bootverbose)
233 device_printf(dev, "PHY Power Failed PHYCS0R = %#x\n", val);
236 * Calibrate the clocks between the device and the host. This appears
237 * to be an automated process that clears the bit when it is done.
239 ahci_set(ctlr->r_mem, AHCI_PHYCS2R, PHYCS2R_CALIBRATE);
240 for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
241 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R);
242 if ((val & PHYCS2R_CALIBRATE) == 0)
246 if (to == 0 && bootverbose)
247 device_printf(dev, "PHY Cal Failed PHYCS2R %#x\n", val);
250 * OK, let things settle down a bit.
255 * Go back into normal mode now that we've calibrated the PHY.
257 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 7);
261 ahci_a10_ch_start(struct ahci_channel *ch)
266 * Magical values from Allwinner SDK, setup the DMA before start
267 * operations on this channel.
269 reg = ATA_INL(ch->r_mem, AHCI_P0DMACR);
272 ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg);
276 ahci_a10_ctlr_reset(device_t dev)
279 ahci_a10_phy_reset(dev);
281 return (ahci_ctlr_reset(dev));
285 ahci_a10_probe(device_t dev)
288 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ahci"))
290 device_set_desc(dev, "Allwinner Integrated AHCI controller");
292 return (BUS_PROBE_DEFAULT);
296 ahci_a10_attach(device_t dev)
299 struct ahci_controller *ctlr;
300 clk_t clk_pll, clk_gate;
302 ctlr = device_get_softc(dev);
303 clk_pll = clk_gate = NULL;
305 ctlr->quirks = AHCI_Q_NOPMP;
308 ctlr->subvendorid = 0;
309 ctlr->subdeviceid = 0;
311 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
312 &ctlr->r_rid, RF_ACTIVE)))
316 error = clk_get_by_ofw_index(dev, 0, 0, &clk_gate);
318 device_printf(dev, "Cannot get gate clock\n");
321 error = clk_get_by_ofw_index(dev, 0, 1, &clk_pll);
323 device_printf(dev, "Cannot get PLL clock\n");
326 error = clk_set_freq(clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN);
328 device_printf(dev, "Cannot set PLL frequency\n");
331 error = clk_enable(clk_pll);
333 device_printf(dev, "Cannot enable PLL\n");
336 error = clk_enable(clk_gate);
338 device_printf(dev, "Cannot enable clk gate\n");
342 /* Reset controller */
343 if ((error = ahci_a10_ctlr_reset(dev)) != 0)
347 * No MSI registers on this platform.
352 /* Channel start callback(). */
353 ctlr->ch_start = ahci_a10_ch_start;
356 * Note: ahci_attach will release ctlr->r_mem on errors automatically
358 return (ahci_attach(dev));
361 if (clk_gate != NULL)
362 clk_release(clk_gate);
364 clk_release(clk_pll);
365 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
370 ahci_a10_detach(device_t dev)
373 return (ahci_detach(dev));
376 static device_method_t ahci_ata_methods[] = {
377 DEVMETHOD(device_probe, ahci_a10_probe),
378 DEVMETHOD(device_attach, ahci_a10_attach),
379 DEVMETHOD(device_detach, ahci_a10_detach),
380 DEVMETHOD(bus_print_child, ahci_print_child),
381 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
382 DEVMETHOD(bus_release_resource, ahci_release_resource),
383 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
384 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
385 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
389 static driver_t ahci_ata_driver = {
392 sizeof(struct ahci_controller)
395 DRIVER_MODULE(a10_ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0);