2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define CCM_PLL1_CFG 0x0000
33 #define CCM_PLL1_TUN 0x0004
34 #define CCM_PLL2_CFG 0x0008
35 #define CCM_PLL2_TUN 0x000c
36 #define CCM_PLL3_CFG 0x0010
37 #define CCM_PLL3_TUN 0x0014
38 #define CCM_PLL4_CFG 0x0018
39 #define CCM_PLL4_TUN 0x001c
40 #define CCM_PLL5_CFG 0x0020
41 #define CCM_PLL5_TUN 0x0024
42 #define CCM_PLL6_CFG 0x0028
43 #define CCM_PLL6_TUN 0x002c
44 #define CCM_PLL7_CFG 0x0030
45 #define CCM_PLL7_TUN 0x0034
46 #define CCM_PLL1_TUN2 0x0038
47 #define CCM_PLL5_TUN2 0x003c
48 #define CCM_PLL_LOCK_DBG 0x004c
49 #define CCM_OSC24M_CFG 0x0050
50 #define CCM_CPU_AHB_APB0_CFG 0x0054
51 #define CCM_APB1_CLK_DIV 0x0058
52 #define CCM_AXI_GATING 0x005c
53 #define CCM_AHB_GATING0 0x0060
54 #define CCM_AHB_GATING1 0x0064
55 #define CCM_APB0_GATING 0x0068
56 #define CCM_APB1_GATING 0x006c
57 #define CCM_NAND_SCLK_CFG 0x0080
58 #define CCM_MS_SCLK_CFG 0x0084
59 #define CCM_MMC0_SCLK_CFG 0x0088
60 #define CCM_MMC1_SCLK_CFG 0x008c
61 #define CCM_MMC2_SCLK_CFG 0x0090
62 #define CCM_MMC3_SCLK_CFG 0x0094
63 #define CCM_TS_CLK 0x0098
64 #define CCM_SS_CLK 0x009c
65 #define CCM_SPI0_CLK 0x00a0
66 #define CCM_SPI1_CLK 0x00a4
67 #define CCM_SPI2_CLK 0x00a8
68 #define CCM_PATA_CLK 0x00ac
69 #define CCM_IR0_CLK 0x00b0
70 #define CCM_IR1_CLK 0x00b4
71 #define CCM_IIS_CLK 0x00b8
72 #define CCM_AC97_CLK 0x00bc
73 #define CCM_SPDIF_CLK 0x00c0
74 #define CCM_KEYPAD_CLK 0x00c4
75 #define CCM_SATA_CLK 0x00c8
76 #define CCM_USB_CLK 0x00cc
77 #define CCM_GPS_CLK 0x00d0
78 #define CCM_SPI3_CLK 0x00d4
79 #define CCM_DRAM_CLK 0x0100
80 #define CCM_BE0_SCLK 0x0104
81 #define CCM_BE1_SCLK 0x0108
82 #define CCM_FE0_CLK 0x010c
83 #define CCM_FE1_CLK 0x0110
84 #define CCM_MP_CLK 0x0114
85 #define CCM_LCD0_CH0_CLK 0x0118
86 #define CCM_LCD1_CH0_CLK 0x011c
87 #define CCM_CSI_ISP_CLK 0x0120
88 #define CCM_TVD_CLK 0x0128
89 #define CCM_LCD0_CH1_CLK 0x012c
90 #define CCM_LCD1_CH1_CLK 0x0130
91 #define CCM_CS0_CLK 0x0134
92 #define CCM_CS1_CLK 0x0138
93 #define CCM_VE_CLK 0x013c
94 #define CCM_AUDIO_CODEC_CLK 0x0140
95 #define CCM_AVS_CLK 0x0144
96 #define CCM_ACE_CLK 0x0148
97 #define CCM_LVDS_CLK 0x014c
98 #define CCM_HDMI_CLK 0x0150
99 #define CCM_MALI400_CLK 0x0154
100 #define CCM_GMAC_CLK 0x0164
102 #define CCM_GMAC_CLK_DELAY_SHIFT 10
103 #define CCM_GMAC_CLK_MODE_MASK 0x7
104 #define CCM_GMAC_MODE_RGMII (1 << 2)
105 #define CCM_GMAC_CLK_MII 0x0
106 #define CCM_GMAC_CLK_EXT_RGMII 0x1
107 #define CCM_GMAC_CLK_RGMII 0x2
110 #define CCM_APB0_GATING_ADDA (1 << 0)
112 /* AHB_GATING_REG0 */
113 #define CCM_AHB_GATING_USB0 (1 << 0)
114 #define CCM_AHB_GATING_EHCI0 (1 << 1)
115 #define CCM_AHB_GATING_OHCI0 (1 << 2)
116 #define CCM_AHB_GATING_EHCI1 (1 << 3)
117 #define CCM_AHB_GATING_OHCI1 (1 << 4)
118 #define CCM_AHB_GATING_DMA (1 << 6)
119 #define CCM_AHB_GATING_SDMMC0 (1 << 8)
120 #define CCM_AHB_GATING_EMAC (1 << 17)
121 #define CCM_AHB_GATING_SATA (1 << 25)
123 /* AHB_GATING_REG1 */
124 #define CCM_AHB_GATING_GMAC (1 << 17)
125 #define CCM_AHB_GATING_DE_BE1 (1 << 13)
126 #define CCM_AHB_GATING_DE_BE0 (1 << 12)
127 #define CCM_AHB_GATING_HDMI (1 << 11)
128 #define CCM_AHB_GATING_LCD1 (1 << 5)
129 #define CCM_AHB_GATING_LCD0 (1 << 4)
131 /* APB1_GATING_REG */
132 #define CCM_APB1_GATING_TWI (1 << 0)
135 #define CCM_USB_PHY (1 << 8)
136 #define CCM_SCLK_GATING_OHCI1 (1 << 7)
137 #define CCM_SCLK_GATING_OHCI0 (1 << 6)
138 #define CCM_USBPHY2_RESET (1 << 2)
139 #define CCM_USBPHY1_RESET (1 << 1)
140 #define CCM_USBPHY0_RESET (1 << 0)
142 #define CCM_PLL_CFG_ENABLE (1U << 31)
143 #define CCM_PLL_CFG_BYPASS (1U << 30)
144 #define CCM_PLL_CFG_PLL5 (1U << 25)
145 #define CCM_PLL_CFG_PLL6 (1U << 24)
146 #define CCM_PLL_CFG_FACTOR_N 0x1f00
147 #define CCM_PLL_CFG_FACTOR_N_SHIFT 8
148 #define CCM_PLL_CFG_FACTOR_K 0x30
149 #define CCM_PLL_CFG_FACTOR_K_SHIFT 4
150 #define CCM_PLL_CFG_FACTOR_M 0x3
152 #define CCM_PLL2_CFG_POSTDIV 0x3c000000
153 #define CCM_PLL2_CFG_POSTDIV_SHIFT 26
154 #define CCM_PLL2_CFG_PREDIV 0x1f
155 #define CCM_PLL2_CFG_PREDIV_SHIFT 0
157 #define CCM_PLL3_CFG_MODE_SEL_SHIFT 15
158 #define CCM_PLL3_CFG_MODE_SEL_FRACT (0 << CCM_PLL3_CFG_MODE_SEL_SHIFT)
159 #define CCM_PLL3_CFG_MODE_SEL_INT (1 << CCM_PLL3_CFG_MODE_SEL_SHIFT)
160 #define CCM_PLL3_CFG_FUNC_SET_SHIFT 14
161 #define CCM_PLL3_CFG_FUNC_SET_270MHZ (0 << CCM_PLL3_CFG_FUNC_SET_SHIFT)
162 #define CCM_PLL3_CFG_FUNC_SET_297MHZ (1 << CCM_PLL3_CFG_FUNC_SET_SHIFT)
163 #define CCM_PLL3_CFG_FACTOR_M 0x7f
165 #define CCM_PLL5_CFG_OUT_EXT_DIV_P 0x30000
166 #define CCM_PLL5_CFG_OUT_EXT_DIV_P_SHIFT 16
168 #define CCM_PLL6_CFG_SATA_CLKEN (1U << 14)
170 #define CCM_SD_CLK_SRC_SEL 0x3000000
171 #define CCM_SD_CLK_SRC_SEL_SHIFT 24
172 #define CCM_SD_CLK_SRC_SEL_OSC24M 0
173 #define CCM_SD_CLK_SRC_SEL_PLL6 1
174 #define CCM_SD_CLK_PHASE_CTR 0x700000
175 #define CCM_SD_CLK_PHASE_CTR_SHIFT 20
176 #define CCM_SD_CLK_DIV_RATIO_N 0x30000
177 #define CCM_SD_CLK_DIV_RATIO_N_SHIFT 16
178 #define CCM_SD_CLK_OPHASE_CTR 0x700
179 #define CCM_SD_CLK_OPHASE_CTR_SHIFT 8
180 #define CCM_SD_CLK_DIV_RATIO_M 0xf
182 #define CCM_AUDIO_CODEC_ENABLE (1U << 31)
184 #define CCM_LCD_CH0_SCLK_GATING (1U << 31)
185 #define CCM_LCD_CH0_RESET (1U << 30)
186 #define CCM_LCD_CH0_SRC_SEL 0x03000000
187 #define CCM_LCD_CH0_SRC_SEL_SHIFT 24
188 #define CCM_LCD_CH0_SRC_SEL_PLL3 0
189 #define CCM_LCD_CH0_SRC_SEL_PLL7 1
190 #define CCM_LCD_CH0_SRC_SEL_PLL3_2X 2
191 #define CCM_LCD_CH0_SRC_SEL_PLL6_2X 3
193 #define CCM_LCD_CH1_SCLK2_GATING (1U << 31)
194 #define CCM_LCD_CH1_SRC_SEL 0x03000000
195 #define CCM_LCD_CH1_SRC_SEL_SHIFT 24
196 #define CCM_LCD_CH1_SRC_SEL_PLL3 0
197 #define CCM_LCD_CH1_SRC_SEL_PLL7 1
198 #define CCM_LCD_CH1_SRC_SEL_PLL3_2X 2
199 #define CCM_LCD_CH1_SRC_SEL_PLL7_2X 3
200 #define CCM_LCD_CH1_SCLK1_GATING (1U << 15)
201 #define CCM_LCD_CH1_SCLK1_SRC_SEL_SHIFT 11
202 #define CCM_LCD_CH1_SCLK1_SRC_SEL_SCLK2 0
203 #define CCM_LCD_CH1_SCLK1_SRC_SEL_SCLK2_DIV2 1
204 #define CCM_LCD_CH1_CLK_DIV_RATIO_M 0xf
206 #define CCM_DRAM_CLK_BE1_CLK_ENABLE (1U << 27)
207 #define CCM_DRAM_CLK_BE0_CLK_ENABLE (1U << 26)
209 #define CCM_BE_CLK_SCLK_GATING (1U << 31)
210 #define CCM_BE_CLK_RESET (1U << 30)
211 #define CCM_BE_CLK_SRC_SEL 0x03000000
212 #define CCM_BE_CLK_SRC_SEL_SHIFT 24
213 #define CCM_BE_CLK_SRC_SEL_PLL3 0
214 #define CCM_BE_CLK_SRC_SEL_PLL7 1
215 #define CCM_BE_CLK_SRC_SEL_PLL5 2
216 #define CCM_BE_CLK_DIV_RATIO_M 0xf
218 #define CCM_HDMI_CLK_SCLK_GATING (1U << 31)
219 #define CCM_HDMI_CLK_SRC_SEL 0x03000000
220 #define CCM_HDMI_CLK_SRC_SEL_SHIFT 24
221 #define CCM_HDMI_CLK_SRC_SEL_PLL3 0
222 #define CCM_HDMI_CLK_SRC_SEL_PLL7 1
223 #define CCM_HDMI_CLK_SRC_SEL_PLL3_2X 2
224 #define CCM_HDMI_CLK_SRC_SEL_PLL7_2X 3
225 #define CCM_HDMI_CLK_DIV_RATIO_M 0xf
227 #define CCM_CLK_REF_FREQ 24000000U
229 int a10_clk_ehci_activate(void);
230 int a10_clk_ehci_deactivate(void);
231 int a10_clk_ohci_activate(void);
232 int a10_clk_ohci_deactivate(void);
233 int a10_clk_emac_activate(void);
234 int a10_clk_gmac_activate(phandle_t);
235 int a10_clk_ahci_activate(void);
236 int a10_clk_mmc_activate(int);
237 int a10_clk_mmc_cfg(int, int);
238 int a10_clk_i2c_activate(int);
239 int a10_clk_dmac_activate(void);
240 int a10_clk_codec_activate(unsigned int);
241 int a10_clk_debe_activate(void);
242 int a10_clk_lcd_activate(void);
243 int a10_clk_tcon_activate(unsigned int);
244 int a10_clk_tcon_get_config(int *, int *);
245 int a10_clk_hdmi_activate(void);
247 #endif /* _A10_CLK_H_ */