2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Allwinner A10 attachment driver for the USB Enhanced Host Controller.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/condvar.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
44 #include <machine/bus.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/usb/usb.h>
49 #include <dev/usb/usbdi.h>
51 #include <dev/usb/usb_core.h>
52 #include <dev/usb/usb_busdma.h>
53 #include <dev/usb/usb_process.h>
54 #include <dev/usb/usb_util.h>
56 #include <dev/usb/usb_controller.h>
57 #include <dev/usb/usb_bus.h>
58 #include <dev/usb/controller/ehci.h>
59 #include <dev/usb/controller/ehcireg.h>
61 #include <arm/allwinner/aw_machdep.h>
62 #include <dev/extres/clk/clk.h>
63 #include <dev/extres/hwreset/hwreset.h>
64 #include <dev/extres/phy/phy.h>
66 #define EHCI_HC_DEVSTR "Allwinner Integrated USB 2.0 controller"
68 #define SW_USB_PMU_IRQ_ENABLE 0x800
70 #define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4))
71 #define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5))
72 #define SW_SDRAM_BP_HPCR_ACCESS (1 << 0)
74 #define SW_ULPI_BYPASS (1 << 0)
75 #define SW_AHB_INCRX_ALIGN (1 << 8)
76 #define SW_AHB_INCR4 (1 << 9)
77 #define SW_AHB_INCR8 (1 << 10)
80 (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
82 #define A10_READ_4(sc, reg) \
83 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
85 #define A10_WRITE_4(sc, reg, data) \
86 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
88 static device_attach_t a10_ehci_attach;
89 static device_detach_t a10_ehci_detach;
91 struct aw_ehci_softc {
102 static const struct aw_ehci_conf a10_ehci_conf = {
106 static const struct aw_ehci_conf a31_ehci_conf = {
110 static struct ofw_compat_data compat_data[] = {
111 { "allwinner,sun4i-a10-ehci", (uintptr_t)&a10_ehci_conf },
112 { "allwinner,sun5i-a13-ehci", (uintptr_t)&a10_ehci_conf },
113 { "allwinner,sun6i-a31-ehci", (uintptr_t)&a31_ehci_conf },
114 { "allwinner,sun7i-a20-ehci", (uintptr_t)&a10_ehci_conf },
115 { "allwinner,sun8i-a83t-ehci", (uintptr_t)&a31_ehci_conf },
116 { "allwinner,sun8i-h3-ehci", (uintptr_t)&a31_ehci_conf },
117 { NULL, (uintptr_t)NULL }
121 a10_ehci_probe(device_t self)
124 if (!ofw_bus_status_okay(self))
127 if (ofw_bus_search_compatible(self, compat_data)->ocd_data == 0)
130 device_set_desc(self, EHCI_HC_DEVSTR);
132 return (BUS_PROBE_DEFAULT);
136 a10_ehci_attach(device_t self)
138 struct aw_ehci_softc *aw_sc = device_get_softc(self);
139 ehci_softc_t *sc = &aw_sc->sc;
140 const struct aw_ehci_conf *conf;
141 bus_space_handle_t bsh;
144 uint32_t reg_value = 0;
146 conf = USB_CONF(self);
148 /* initialise some bus fields */
149 sc->sc_bus.parent = self;
150 sc->sc_bus.devices = sc->sc_devices;
151 sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
152 sc->sc_bus.dma_bits = 32;
154 /* get all DMA memory */
155 if (usb_bus_mem_alloc_all(&sc->sc_bus,
156 USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
160 sc->sc_bus.usbrev = USB_REV_2_0;
163 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
164 if (!sc->sc_io_res) {
165 device_printf(self, "Could not map memory\n");
169 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
170 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
171 bsh = rman_get_bushandle(sc->sc_io_res);
173 sc->sc_io_size = rman_get_size(sc->sc_io_res);
175 if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00,
176 sc->sc_io_size, &sc->sc_io_hdl) != 0)
177 panic("%s: unable to subregion USB host registers",
178 device_get_name(self));
181 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
182 RF_SHAREABLE | RF_ACTIVE);
183 if (sc->sc_irq_res == NULL) {
184 device_printf(self, "Could not allocate irq\n");
187 sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
188 if (!sc->sc_bus.bdev) {
189 device_printf(self, "Could not add USB device\n");
192 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
193 device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
195 sprintf(sc->sc_vendor, "Allwinner");
197 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
198 NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
200 device_printf(self, "Could not setup irq, %d\n", err);
201 sc->sc_intr_hdl = NULL;
205 sc->sc_flags |= EHCI_SCFLG_DONTRESET;
207 /* De-assert reset */
208 if (hwreset_get_by_ofw_idx(self, 0, 0, &aw_sc->rst) == 0) {
209 err = hwreset_deassert(aw_sc->rst);
211 device_printf(self, "Could not de-assert reset\n");
216 /* Enable clock for USB */
217 err = clk_get_by_ofw_index(self, 0, 0, &aw_sc->clk);
219 device_printf(self, "Could not get clock\n");
222 err = clk_enable(aw_sc->clk);
224 device_printf(self, "Could not enable clock\n");
229 if (phy_get_by_ofw_name(self, 0, "usb", &aw_sc->phy) == 0) {
230 err = phy_enable(self, aw_sc->phy);
232 device_printf(self, "Could not enable phy\n");
238 reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
239 reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */
240 reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */
241 reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */
242 reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */
243 A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
246 if (conf->sdram_init) {
247 reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
248 reg_value |= SW_SDRAM_BP_HPCR_ACCESS;
249 A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
254 err = device_probe_and_attach(sc->sc_bus.bdev);
257 device_printf(self, "USB init failed err=%d\n", err);
263 a10_ehci_detach(self);
268 a10_ehci_detach(device_t self)
270 struct aw_ehci_softc *aw_sc = device_get_softc(self);
271 ehci_softc_t *sc = &aw_sc->sc;
272 const struct aw_ehci_conf *conf;
274 uint32_t reg_value = 0;
276 conf = USB_CONF(self);
278 /* during module unload there are lots of children leftover */
279 device_delete_children(self);
281 if (sc->sc_irq_res && sc->sc_intr_hdl) {
283 * only call ehci_detach() after ehci_init()
287 err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
290 /* XXX or should we panic? */
291 device_printf(self, "Could not tear down irq, %d\n",
293 sc->sc_intr_hdl = NULL;
296 if (sc->sc_irq_res) {
297 bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
298 sc->sc_irq_res = NULL;
301 bus_release_resource(self, SYS_RES_MEMORY, 0,
303 sc->sc_io_res = NULL;
305 usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
307 /* Disable configure port */
308 if (conf->sdram_init) {
309 reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
310 reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS;
311 A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
315 reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
316 reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */
317 reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */
318 reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */
319 reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */
320 A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
322 /* Disable clock for USB */
323 if (aw_sc->clk != NULL) {
324 clk_disable(aw_sc->clk);
325 clk_release(aw_sc->clk);
329 if (aw_sc->rst != NULL) {
330 hwreset_assert(aw_sc->rst);
331 hwreset_release(aw_sc->rst);
337 static device_method_t ehci_methods[] = {
338 /* Device interface */
339 DEVMETHOD(device_probe, a10_ehci_probe),
340 DEVMETHOD(device_attach, a10_ehci_attach),
341 DEVMETHOD(device_detach, a10_ehci_detach),
342 DEVMETHOD(device_suspend, bus_generic_suspend),
343 DEVMETHOD(device_resume, bus_generic_resume),
344 DEVMETHOD(device_shutdown, bus_generic_shutdown),
349 static driver_t ehci_driver = {
351 .methods = ehci_methods,
352 .size = sizeof(struct aw_ehci_softc),
355 static devclass_t ehci_devclass;
357 DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0);
358 MODULE_DEPEND(ehci, usb, 1, 1, 1);