2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner A10 attachment driver for the USB Enhanced Host Controller.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <sys/condvar.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
46 #include <machine/bus.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/usb/usb.h>
51 #include <dev/usb/usbdi.h>
53 #include <dev/usb/usb_core.h>
54 #include <dev/usb/usb_busdma.h>
55 #include <dev/usb/usb_process.h>
56 #include <dev/usb/usb_util.h>
58 #include <dev/usb/usb_controller.h>
59 #include <dev/usb/usb_bus.h>
60 #include <dev/usb/controller/ehci.h>
61 #include <dev/usb/controller/ehcireg.h>
63 #include <arm/allwinner/aw_machdep.h>
64 #include <dev/extres/clk/clk.h>
65 #include <dev/extres/hwreset/hwreset.h>
66 #include <dev/extres/phy/phy_usb.h>
68 #define EHCI_HC_DEVSTR "Allwinner Integrated USB 2.0 controller"
70 #define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4))
71 #define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5))
72 #define SW_SDRAM_BP_HPCR_ACCESS (1 << 0)
75 (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
77 #define A10_READ_4(sc, reg) \
78 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
80 #define A10_WRITE_4(sc, reg, data) \
81 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
83 static device_attach_t a10_ehci_attach;
84 static device_detach_t a10_ehci_detach;
87 TAILQ_ENTRY(clk_list) next;
92 TAILQ_ENTRY(hwrst_list) next;
96 struct aw_ehci_softc {
98 TAILQ_HEAD(, clk_list) clk_list;
99 TAILQ_HEAD(, hwrst_list) rst_list;
103 struct aw_ehci_conf {
107 static const struct aw_ehci_conf a10_ehci_conf = {
111 static const struct aw_ehci_conf a31_ehci_conf = {
115 static struct ofw_compat_data compat_data[] = {
116 { "allwinner,sun4i-a10-ehci", (uintptr_t)&a10_ehci_conf },
117 { "allwinner,sun5i-a13-ehci", (uintptr_t)&a10_ehci_conf },
118 { "allwinner,sun6i-a31-ehci", (uintptr_t)&a31_ehci_conf },
119 { "allwinner,sun7i-a20-ehci", (uintptr_t)&a10_ehci_conf },
120 { "allwinner,sun8i-a83t-ehci", (uintptr_t)&a31_ehci_conf },
121 { "allwinner,sun8i-h3-ehci", (uintptr_t)&a31_ehci_conf },
122 { "allwinner,sun50i-a64-ehci", (uintptr_t)&a31_ehci_conf },
123 { NULL, (uintptr_t)NULL }
127 a10_ehci_probe(device_t self)
130 if (!ofw_bus_status_okay(self))
133 if (ofw_bus_search_compatible(self, compat_data)->ocd_data == 0)
136 device_set_desc(self, EHCI_HC_DEVSTR);
138 return (BUS_PROBE_DEFAULT);
142 a10_ehci_attach(device_t self)
144 struct aw_ehci_softc *aw_sc = device_get_softc(self);
145 ehci_softc_t *sc = &aw_sc->sc;
146 const struct aw_ehci_conf *conf;
147 bus_space_handle_t bsh;
149 struct clk_list *clkp;
151 struct hwrst_list *rstp;
153 uint32_t reg_value = 0;
155 conf = USB_CONF(self);
157 /* initialise some bus fields */
158 sc->sc_bus.parent = self;
159 sc->sc_bus.devices = sc->sc_devices;
160 sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
161 sc->sc_bus.dma_bits = 32;
163 /* get all DMA memory */
164 if (usb_bus_mem_alloc_all(&sc->sc_bus,
165 USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
169 sc->sc_bus.usbrev = USB_REV_2_0;
172 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
173 if (!sc->sc_io_res) {
174 device_printf(self, "Could not map memory\n");
178 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
179 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
180 bsh = rman_get_bushandle(sc->sc_io_res);
182 sc->sc_io_size = rman_get_size(sc->sc_io_res);
184 if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00,
185 sc->sc_io_size, &sc->sc_io_hdl) != 0)
186 panic("%s: unable to subregion USB host registers",
187 device_get_name(self));
190 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
191 RF_SHAREABLE | RF_ACTIVE);
192 if (sc->sc_irq_res == NULL) {
193 device_printf(self, "Could not allocate irq\n");
196 sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
197 if (!sc->sc_bus.bdev) {
198 device_printf(self, "Could not add USB device\n");
201 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
202 device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
204 sprintf(sc->sc_vendor, "Allwinner");
206 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
207 NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
209 device_printf(self, "Could not setup irq, %d\n", err);
210 sc->sc_intr_hdl = NULL;
214 sc->sc_flags |= EHCI_SCFLG_DONTRESET;
216 /* Enable clock for USB */
217 TAILQ_INIT(&aw_sc->clk_list);
218 for (off = 0; clk_get_by_ofw_index(self, 0, off, &clk) == 0; off++) {
219 err = clk_enable(clk);
221 device_printf(self, "Could not enable clock %s\n",
225 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
227 TAILQ_INSERT_TAIL(&aw_sc->clk_list, clkp, next);
230 /* De-assert reset */
231 TAILQ_INIT(&aw_sc->rst_list);
232 for (off = 0; hwreset_get_by_ofw_idx(self, 0, off, &rst) == 0; off++) {
233 err = hwreset_deassert(rst);
235 device_printf(self, "Could not de-assert reset\n");
238 rstp = malloc(sizeof(*rstp), M_DEVBUF, M_WAITOK | M_ZERO);
240 TAILQ_INSERT_TAIL(&aw_sc->rst_list, rstp, next);
244 if (phy_get_by_ofw_name(self, 0, "usb", &aw_sc->phy) == 0) {
245 err = phy_usb_set_mode(aw_sc->phy, PHY_USB_MODE_HOST);
247 device_printf(self, "Could not set phy to host mode\n");
250 err = phy_enable(aw_sc->phy);
252 device_printf(self, "Could not enable phy\n");
258 if (conf->sdram_init) {
259 reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
260 reg_value |= SW_SDRAM_BP_HPCR_ACCESS;
261 A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
266 err = device_probe_and_attach(sc->sc_bus.bdev);
269 device_printf(self, "USB init failed err=%d\n", err);
275 a10_ehci_detach(self);
280 a10_ehci_detach(device_t self)
282 struct aw_ehci_softc *aw_sc = device_get_softc(self);
283 ehci_softc_t *sc = &aw_sc->sc;
284 const struct aw_ehci_conf *conf;
286 uint32_t reg_value = 0;
287 struct clk_list *clk, *clk_tmp;
288 struct hwrst_list *rst, *rst_tmp;
290 conf = USB_CONF(self);
292 /* during module unload there are lots of children leftover */
293 device_delete_children(self);
295 if (sc->sc_irq_res && sc->sc_intr_hdl) {
297 * only call ehci_detach() after ehci_init()
301 err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
304 /* XXX or should we panic? */
305 device_printf(self, "Could not tear down irq, %d\n",
307 sc->sc_intr_hdl = NULL;
310 if (sc->sc_irq_res) {
311 bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
312 sc->sc_irq_res = NULL;
315 bus_release_resource(self, SYS_RES_MEMORY, 0,
317 sc->sc_io_res = NULL;
319 usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
321 /* Disable configure port */
322 if (conf->sdram_init) {
323 reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
324 reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS;
325 A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
329 TAILQ_FOREACH_SAFE(clk, &aw_sc->clk_list, next, clk_tmp) {
330 err = clk_disable(clk->clk);
332 device_printf(self, "Could not disable clock %s\n",
333 clk_get_name(clk->clk));
334 err = clk_release(clk->clk);
336 device_printf(self, "Could not release clock %s\n",
337 clk_get_name(clk->clk));
338 TAILQ_REMOVE(&aw_sc->clk_list, clk, next);
343 TAILQ_FOREACH_SAFE(rst, &aw_sc->rst_list, next, rst_tmp) {
344 hwreset_assert(rst->rst);
345 hwreset_release(rst->rst);
346 TAILQ_REMOVE(&aw_sc->rst_list, rst, next);
353 static device_method_t ehci_methods[] = {
354 /* Device interface */
355 DEVMETHOD(device_probe, a10_ehci_probe),
356 DEVMETHOD(device_attach, a10_ehci_attach),
357 DEVMETHOD(device_detach, a10_ehci_detach),
358 DEVMETHOD(device_suspend, bus_generic_suspend),
359 DEVMETHOD(device_resume, bus_generic_resume),
360 DEVMETHOD(device_shutdown, bus_generic_shutdown),
365 static driver_t ehci_driver = {
367 .methods = ehci_methods,
368 .size = sizeof(struct aw_ehci_softc),
371 static devclass_t ehci_devclass;
373 DRIVER_MODULE(a10_ehci, simplebus, ehci_driver, ehci_devclass, 0, 0);
374 MODULE_DEPEND(a10_ehci, usb, 1, 1, 1);