2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (c) 2012 Luiz Otavio O Souza.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
40 #include <sys/mutex.h>
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/gpio/gpiobusvar.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
58 * A10 have 9 banks of gpio.
60 * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
61 * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
62 * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
65 #define A10_GPIO_PINS 288
66 #define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
67 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
69 #define A10_GPIO_NONE 0
70 #define A10_GPIO_PULLUP 1
71 #define A10_GPIO_PULLDOWN 2
73 #define A10_GPIO_INPUT 0
74 #define A10_GPIO_OUTPUT 1
76 struct a10_gpio_softc {
80 struct resource * sc_mem_res;
81 struct resource * sc_irq_res;
82 bus_space_tag_t sc_bst;
83 bus_space_handle_t sc_bsh;
86 struct gpio_pin sc_gpio_pins[A10_GPIO_PINS];
89 #define A10_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx)
90 #define A10_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx)
91 #define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
93 #define A10_GPIO_GP_CFG(_bank, _pin) 0x00 + ((_bank) * 0x24) + ((_pin)<<2)
94 #define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
95 #define A10_GPIO_GP_DRV(_bank, _pin) 0x14 + ((_bank) * 0x24) + ((_pin)<<2)
96 #define A10_GPIO_GP_PUL(_bank, _pin) 0x1c + ((_bank) * 0x24) + ((_pin)<<2)
98 #define A10_GPIO_GP_INT_CFG0 0x200
99 #define A10_GPIO_GP_INT_CFG1 0x204
100 #define A10_GPIO_GP_INT_CFG2 0x208
101 #define A10_GPIO_GP_INT_CFG3 0x20c
103 #define A10_GPIO_GP_INT_CTL 0x210
104 #define A10_GPIO_GP_INT_STA 0x214
105 #define A10_GPIO_GP_INT_DEB 0x218
107 static struct a10_gpio_softc *a10_gpio_sc;
109 #define A10_GPIO_WRITE(_sc, _off, _val) \
110 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
111 #define A10_GPIO_READ(_sc, _off) \
112 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
115 a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
117 uint32_t bank, func, offset;
120 pin = pin - 32 * bank;
122 offset = ((pin & 0x07) << 2);
125 func = (A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func)) >> offset) & 7;
132 a10_gpio_func_flag(uint32_t nfunc)
137 return (GPIO_PIN_INPUT);
138 case A10_GPIO_OUTPUT:
139 return (GPIO_PIN_OUTPUT);
145 a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
147 uint32_t bank, func, data, offset;
149 /* Must be called with lock held. */
150 A10_GPIO_LOCK_ASSERT(sc);
153 pin = pin - 32 * bank;
155 offset = ((pin & 0x07) << 2);
157 data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func));
158 data &= ~(7 << offset);
159 data |= (f << offset);
160 A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, func), data);
164 a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
166 uint32_t bank, offset, pull, val;
168 /* Must be called with lock held. */
169 A10_GPIO_LOCK_ASSERT(sc);
172 pin = pin - 32 * bank;
174 offset = ((pin & 0x0f) << 1);
176 val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pull));
177 val &= ~(0x03 << offset);
178 val |= (state << offset);
179 A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pull), val);
183 a10_gpio_pin_configure(struct a10_gpio_softc *sc, struct gpio_pin *pin,
190 * Manage input/output.
192 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
193 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
194 if (flags & GPIO_PIN_OUTPUT) {
195 pin->gp_flags |= GPIO_PIN_OUTPUT;
196 a10_gpio_set_function(sc, pin->gp_pin,
199 pin->gp_flags |= GPIO_PIN_INPUT;
200 a10_gpio_set_function(sc, pin->gp_pin,
205 /* Manage Pull-up/pull-down. */
206 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
207 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
208 if (flags & GPIO_PIN_PULLUP) {
209 pin->gp_flags |= GPIO_PIN_PULLUP;
210 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLUP);
212 pin->gp_flags |= GPIO_PIN_PULLDOWN;
213 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLDOWN);
216 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_NONE);
222 a10_gpio_get_bus(device_t dev)
224 struct a10_gpio_softc *sc;
226 sc = device_get_softc(dev);
228 return (sc->sc_busdev);
232 a10_gpio_pin_max(device_t dev, int *maxpin)
235 *maxpin = A10_GPIO_PINS - 1;
240 a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
242 struct a10_gpio_softc *sc = device_get_softc(dev);
245 for (i = 0; i < sc->sc_gpio_npins; i++) {
246 if (sc->sc_gpio_pins[i].gp_pin == pin)
250 if (i >= sc->sc_gpio_npins)
254 *caps = sc->sc_gpio_pins[i].gp_caps;
261 a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
263 struct a10_gpio_softc *sc = device_get_softc(dev);
266 for (i = 0; i < sc->sc_gpio_npins; i++) {
267 if (sc->sc_gpio_pins[i].gp_pin == pin)
271 if (i >= sc->sc_gpio_npins)
275 *flags = sc->sc_gpio_pins[i].gp_flags;
282 a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
284 struct a10_gpio_softc *sc = device_get_softc(dev);
287 for (i = 0; i < sc->sc_gpio_npins; i++) {
288 if (sc->sc_gpio_pins[i].gp_pin == pin)
292 if (i >= sc->sc_gpio_npins)
296 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
303 a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
305 struct a10_gpio_softc *sc = device_get_softc(dev);
308 for (i = 0; i < sc->sc_gpio_npins; i++) {
309 if (sc->sc_gpio_pins[i].gp_pin == pin)
313 if (i >= sc->sc_gpio_npins)
316 a10_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
322 a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
324 struct a10_gpio_softc *sc = device_get_softc(dev);
325 uint32_t bank, offset, data;
328 for (i = 0; i < sc->sc_gpio_npins; i++) {
329 if (sc->sc_gpio_pins[i].gp_pin == pin)
333 if (i >= sc->sc_gpio_npins)
337 pin = pin - 32 * bank;
341 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
343 data |= (1 << offset);
345 data &= ~(1 << offset);
346 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
353 a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
355 struct a10_gpio_softc *sc = device_get_softc(dev);
356 uint32_t bank, offset, reg_data;
359 for (i = 0; i < sc->sc_gpio_npins; i++) {
360 if (sc->sc_gpio_pins[i].gp_pin == pin)
364 if (i >= sc->sc_gpio_npins)
368 pin = pin - 32 * bank;
372 reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
374 *val = (reg_data & (1 << offset)) ? 1 : 0;
380 a10_gpio_pin_toggle(device_t dev, uint32_t pin)
382 struct a10_gpio_softc *sc = device_get_softc(dev);
383 uint32_t bank, data, offset;
386 for (i = 0; i < sc->sc_gpio_npins; i++) {
387 if (sc->sc_gpio_pins[i].gp_pin == pin)
391 if (i >= sc->sc_gpio_npins)
395 pin = pin - 32 * bank;
399 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
400 if (data & (1 << offset))
401 data &= ~(1 << offset);
403 data |= (1 << offset);
404 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
411 a10_gpio_probe(device_t dev)
414 if (!ofw_bus_status_okay(dev))
417 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-gpio"))
420 device_set_desc(dev, "Allwinner GPIO controller");
421 return (BUS_PROBE_DEFAULT);
425 a10_gpio_attach(device_t dev)
427 struct a10_gpio_softc *sc = device_get_softc(dev);
434 mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_DEF);
437 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
439 if (!sc->sc_mem_res) {
440 device_printf(dev, "cannot allocate memory window\n");
444 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
445 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
448 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
450 if (!sc->sc_irq_res) {
451 device_printf(dev, "cannot allocate interrupt\n");
456 gpio = ofw_bus_get_node(sc->sc_dev);
458 if (!OF_hasprop(gpio, "gpio-controller"))
459 /* Node is not a GPIO controller. */
462 /* Initialize the software controlled pins. */
463 for (i = 0; i < A10_GPIO_PINS; i++) {
464 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
466 func = a10_gpio_get_function(sc, i);
467 sc->sc_gpio_pins[i].gp_pin = i;
468 sc->sc_gpio_pins[i].gp_caps = A10_GPIO_DEFAULT_CAPS;
469 sc->sc_gpio_pins[i].gp_flags = a10_gpio_func_flag(func);
471 sc->sc_gpio_npins = i;
473 sc->sc_busdev = gpiobus_attach_bus(dev);
474 if (sc->sc_busdev == NULL)
481 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
483 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
484 mtx_destroy(&sc->sc_mtx);
490 a10_gpio_detach(device_t dev)
496 static device_method_t a10_gpio_methods[] = {
497 /* Device interface */
498 DEVMETHOD(device_probe, a10_gpio_probe),
499 DEVMETHOD(device_attach, a10_gpio_attach),
500 DEVMETHOD(device_detach, a10_gpio_detach),
503 DEVMETHOD(gpio_get_bus, a10_gpio_get_bus),
504 DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
505 DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
506 DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
507 DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
508 DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
509 DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
510 DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
511 DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
516 static devclass_t a10_gpio_devclass;
518 static driver_t a10_gpio_driver = {
521 sizeof(struct a10_gpio_softc),
524 DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0);
527 a10_emac_gpio_config(uint32_t pin)
529 struct a10_gpio_softc *sc = a10_gpio_sc;
534 /* Configure pin mux settings for MII. */
536 a10_gpio_set_function(sc, pin, A10_GPIO_PULLDOWN);