sys/arm/allwinner/a10_mmc.c

   1 /*-
   2  * Copyright (c) 2013 Alexander Fedorov
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/kernel.h>
  34 #include <sys/lock.h>
  35 #include <sys/malloc.h>
  36 #include <sys/module.h>
  37 #include <sys/mutex.h>
  38 #include <sys/resource.h>
  39 #include <sys/rman.h>
  40 #include <sys/sysctl.h>
  41
  42 #include <machine/bus.h>
  43
  44 #include <dev/ofw/ofw_bus.h>
  45 #include <dev/ofw/ofw_bus_subr.h>
  46
  47 #include <dev/mmc/bridge.h>
  48 #include <dev/mmc/mmcreg.h>
  49 #include <dev/mmc/mmcbrvar.h>
  50
  51 #include <arm/allwinner/aw_machdep.h>
  52 #include <arm/allwinner/a10_mmc.h>
  53 #include <dev/extres/clk/clk.h>
  54 #include <dev/extres/hwreset/hwreset.h>
  55
  56 #define A10_MMC_MEMRES          0
  57 #define A10_MMC_IRQRES          1
  58 #define A10_MMC_RESSZ           2
  59 #define A10_MMC_DMA_SEGS        16
  60 #define A10_MMC_DMA_MAX_SIZE    0x2000
  61 #define A10_MMC_DMA_FTRGLEVEL   0x20070008
  62
  63 #define CARD_ID_FREQUENCY       400000
  64
  65 static int a10_mmc_pio_mode = 0;
  66
  67 TUNABLE_INT("hw.a10.mmc.pio_mode", &a10_mmc_pio_mode);
  68
  69 static struct ofw_compat_data compat_data[] = {
  70         {"allwinner,sun4i-a10-mmc", 1},
  71         {"allwinner,sun5i-a13-mmc", 1},
  72         {NULL,             0}
  73 };
  74
  75 struct a10_mmc_softc {
  76         bus_space_handle_t      a10_bsh;
  77         bus_space_tag_t         a10_bst;
  78         device_t                a10_dev;
  79         clk_t                   a10_clk_ahb;
  80         clk_t                   a10_clk_mmc;
  81         hwreset_t               a10_rst_ahb;
  82         int                     a10_bus_busy;
  83         int                     a10_id;
  84         int                     a10_resid;
  85         int                     a10_timeout;
  86         struct callout          a10_timeoutc;
  87         struct mmc_host         a10_host;
  88         struct mmc_request *    a10_req;
  89         struct mtx              a10_mtx;
  90         struct resource *       a10_res[A10_MMC_RESSZ];
  91         uint32_t                a10_intr;
  92         uint32_t                a10_intr_wait;
  93         void *                  a10_intrhand;
  94         bus_size_t              a10_fifo_reg;
  95
  96         /* Fields required for DMA access. */
  97         bus_addr_t              a10_dma_desc_phys;
  98         bus_dmamap_t            a10_dma_map;
  99         bus_dma_tag_t           a10_dma_tag;
 100         void *                  a10_dma_desc;
 101         bus_dmamap_t            a10_dma_buf_map;
 102         bus_dma_tag_t           a10_dma_buf_tag;
 103         int                     a10_dma_inuse;
 104         int                     a10_dma_map_err;
 105 };
 106
 107 static struct resource_spec a10_mmc_res_spec[] = {
 108         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 109         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_SHAREABLE },
 110         { -1,                   0,      0 }
 111 };
 112
 113 static int a10_mmc_probe(device_t);
 114 static int a10_mmc_attach(device_t);
 115 static int a10_mmc_detach(device_t);
 116 static int a10_mmc_setup_dma(struct a10_mmc_softc *);
 117 static int a10_mmc_reset(struct a10_mmc_softc *);
 118 static void a10_mmc_intr(void *);
 119 static int a10_mmc_update_clock(struct a10_mmc_softc *);
 120
 121 static int a10_mmc_update_ios(device_t, device_t);
 122 static int a10_mmc_request(device_t, device_t, struct mmc_request *);
 123 static int a10_mmc_get_ro(device_t, device_t);
 124 static int a10_mmc_acquire_host(device_t, device_t);
 125 static int a10_mmc_release_host(device_t, device_t);
 126
 127 #define A10_MMC_LOCK(_sc)       mtx_lock(&(_sc)->a10_mtx)
 128 #define A10_MMC_UNLOCK(_sc)     mtx_unlock(&(_sc)->a10_mtx)
 129 #define A10_MMC_READ_4(_sc, _reg)                                       \
 130         bus_space_read_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg)
 131 #define A10_MMC_WRITE_4(_sc, _reg, _value)                              \
 132         bus_space_write_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value)
 133
 134 static int
 135 a10_mmc_probe(device_t dev)
 136 {
 137
 138         if (!ofw_bus_status_okay(dev))
 139                 return (ENXIO);
 140         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 141                 return (ENXIO);
 142
 143         device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
 144
 145         return (BUS_PROBE_DEFAULT);
 146 }
 147
 148 static int
 149 a10_mmc_attach(device_t dev)
 150 {
 151         device_t child;
 152         struct a10_mmc_softc *sc;
 153         struct sysctl_ctx_list *ctx;
 154         struct sysctl_oid_list *tree;
 155         uint32_t bus_width;
 156         phandle_t node;
 157         int error;
 158
 159         node = ofw_bus_get_node(dev);
 160         sc = device_get_softc(dev);
 161         sc->a10_dev = dev;
 162         sc->a10_req = NULL;
 163         sc->a10_id = device_get_unit(dev);
 164         if (sc->a10_id > 3) {
 165                 device_printf(dev, "only 4 hosts are supported (0-3)\n");
 166                 return (ENXIO);
 167         }
 168         if (bus_alloc_resources(dev, a10_mmc_res_spec, sc->a10_res) != 0) {
 169                 device_printf(dev, "cannot allocate device resources\n");
 170                 return (ENXIO);
 171         }
 172         sc->a10_bst = rman_get_bustag(sc->a10_res[A10_MMC_MEMRES]);
 173         sc->a10_bsh = rman_get_bushandle(sc->a10_res[A10_MMC_MEMRES]);
 174         if (bus_setup_intr(dev, sc->a10_res[A10_MMC_IRQRES],
 175             INTR_TYPE_MISC | INTR_MPSAFE, NULL, a10_mmc_intr, sc,
 176             &sc->a10_intrhand)) {
 177                 bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res);
 178                 device_printf(dev, "cannot setup interrupt handler\n");
 179                 return (ENXIO);
 180         }
 181         mtx_init(&sc->a10_mtx, device_get_nameunit(sc->a10_dev), "a10_mmc",
 182             MTX_DEF);
 183         callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0);
 184
 185 #if defined(__arm__)
 186         /*
 187          * Later chips use a different FIFO offset. Unfortunately the FDT
 188          * uses the same compatible string for old and new implementations.
 189          */
 190         switch (allwinner_soc_family()) {
 191         case ALLWINNERSOC_SUN4I:
 192         case ALLWINNERSOC_SUN5I:
 193         case ALLWINNERSOC_SUN7I:
 194                 sc->a10_fifo_reg = A10_MMC_FIFO;
 195                 break;
 196         default:
 197                 sc->a10_fifo_reg = A31_MMC_FIFO;
 198                 break;
 199         }
 200 #else /* __aarch64__ */
 201         sc->a10_fifo_reg = A31_MMC_FIFO;
 202 #endif
 203
 204         /* De-assert reset */
 205         if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->a10_rst_ahb) == 0) {
 206                 error = hwreset_deassert(sc->a10_rst_ahb);
 207                 if (error != 0) {
 208                         device_printf(dev, "cannot de-assert reset\n");
 209                         return (error);
 210                 }
 211         }
 212
 213         /* Activate the module clock. */
 214         error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->a10_clk_ahb);
 215         if (error != 0) {
 216                 device_printf(dev, "cannot get ahb clock\n");
 217                 goto fail;
 218         }
 219         error = clk_enable(sc->a10_clk_ahb);
 220         if (error != 0) {
 221                 device_printf(dev, "cannot enable ahb clock\n");
 222                 goto fail;
 223         }
 224         error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->a10_clk_mmc);
 225         if (error != 0) {
 226                 device_printf(dev, "cannot get mmc clock\n");
 227                 goto fail;
 228         }
 229         error = clk_set_freq(sc->a10_clk_mmc, CARD_ID_FREQUENCY,
 230             CLK_SET_ROUND_DOWN);
 231         if (error != 0) {
 232                 device_printf(dev, "cannot init mmc clock\n");
 233                 goto fail;
 234         }
 235         error = clk_enable(sc->a10_clk_mmc);
 236         if (error != 0) {
 237                 device_printf(dev, "cannot enable mmc clock\n");
 238                 goto fail;
 239         }
 240
 241         sc->a10_timeout = 10;
 242         ctx = device_get_sysctl_ctx(dev);
 243         tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
 244         SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
 245             &sc->a10_timeout, 0, "Request timeout in seconds");
 246
 247         /* Reset controller. */
 248         if (a10_mmc_reset(sc) != 0) {
 249                 device_printf(dev, "cannot reset the controller\n");
 250                 goto fail;
 251         }
 252
 253         if (a10_mmc_pio_mode == 0 && a10_mmc_setup_dma(sc) != 0) {
 254                 device_printf(sc->a10_dev, "Couldn't setup DMA!\n");
 255                 a10_mmc_pio_mode = 1;
 256         }
 257         if (bootverbose)
 258                 device_printf(sc->a10_dev, "DMA status: %s\n",
 259                     a10_mmc_pio_mode ? "disabled" : "enabled");
 260
 261         if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
 262                 bus_width = 4;
 263
 264         sc->a10_host.f_min = 400000;
 265         sc->a10_host.f_max = 50000000;
 266         sc->a10_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
 267         sc->a10_host.mode = mode_sd;
 268         sc->a10_host.caps = MMC_CAP_HSPEED;
 269         if (bus_width >= 4)
 270                 sc->a10_host.caps |= MMC_CAP_4_BIT_DATA;
 271         if (bus_width >= 8)
 272                 sc->a10_host.caps |= MMC_CAP_8_BIT_DATA;
 273
 274         child = device_add_child(dev, "mmc", -1);
 275         if (child == NULL) {
 276                 device_printf(dev, "attaching MMC bus failed!\n");
 277                 goto fail;
 278         }
 279         if (device_probe_and_attach(child) != 0) {
 280                 device_printf(dev, "attaching MMC child failed!\n");
 281                 device_delete_child(dev, child);
 282                 goto fail;
 283         }
 284
 285         return (0);
 286
 287 fail:
 288         callout_drain(&sc->a10_timeoutc);
 289         mtx_destroy(&sc->a10_mtx);
 290         bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], sc->a10_intrhand);
 291         bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res);
 292
 293         return (ENXIO);
 294 }
 295
 296 static int
 297 a10_mmc_detach(device_t dev)
 298 {
 299
 300         return (EBUSY);
 301 }
 302
 303 static void
 304 a10_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
 305 {
 306         struct a10_mmc_softc *sc;
 307
 308         sc = (struct a10_mmc_softc *)arg;
 309         if (err) {
 310                 sc->a10_dma_map_err = err;
 311                 return;
 312         }
 313         sc->a10_dma_desc_phys = segs[0].ds_addr;
 314 }
 315
 316 static int
 317 a10_mmc_setup_dma(struct a10_mmc_softc *sc)
 318 {
 319         int dma_desc_size, error;
 320
 321         /* Allocate the DMA descriptor memory. */
 322         dma_desc_size = sizeof(struct a10_mmc_dma_desc) * A10_MMC_DMA_SEGS;
 323         error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
 324             A10_MMC_DMA_ALIGN, 0,
 325             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
 326             dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->a10_dma_tag);
 327         if (error)
 328                 return (error);
 329         error = bus_dmamem_alloc(sc->a10_dma_tag, &sc->a10_dma_desc,
 330             BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->a10_dma_map);
 331         if (error)
 332                 return (error);
 333
 334         error = bus_dmamap_load(sc->a10_dma_tag, sc->a10_dma_map,
 335             sc->a10_dma_desc, dma_desc_size, a10_dma_desc_cb, sc, 0);
 336         if (error)
 337                 return (error);
 338         if (sc->a10_dma_map_err)
 339                 return (sc->a10_dma_map_err);
 340
 341         /* Create the DMA map for data transfers. */
 342         error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
 343             A10_MMC_DMA_ALIGN, 0,
 344             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
 345             A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS, A10_MMC_DMA_SEGS,
 346             A10_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
 347             &sc->a10_dma_buf_tag);
 348         if (error)
 349                 return (error);
 350         error = bus_dmamap_create(sc->a10_dma_buf_tag, 0,
 351             &sc->a10_dma_buf_map);
 352         if (error)
 353                 return (error);
 354
 355         return (0);
 356 }
 357
 358 static void
 359 a10_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
 360 {
 361         int i;
 362         struct a10_mmc_dma_desc *dma_desc;
 363         struct a10_mmc_softc *sc;
 364
 365         sc = (struct a10_mmc_softc *)arg;
 366         sc->a10_dma_map_err = err;
 367
 368         if (err)
 369                 return;
 370
 371         dma_desc = sc->a10_dma_desc;
 372         /* Note nsegs is guaranteed to be zero if err is non-zero. */
 373         for (i = 0; i < nsegs; i++) {
 374                 dma_desc[i].buf_size = segs[i].ds_len;
 375                 dma_desc[i].buf_addr = segs[i].ds_addr;
 376                 dma_desc[i].config = A10_MMC_DMA_CONFIG_CH |
 377                     A10_MMC_DMA_CONFIG_OWN;
 378                 if (i == 0)
 379                         dma_desc[i].config |= A10_MMC_DMA_CONFIG_FD;
 380                 if (i < (nsegs - 1)) {
 381                         dma_desc[i].config |= A10_MMC_DMA_CONFIG_DIC;
 382                         dma_desc[i].next = sc->a10_dma_desc_phys +
 383                             ((i + 1) * sizeof(struct a10_mmc_dma_desc));
 384                 } else {
 385                         dma_desc[i].config |= A10_MMC_DMA_CONFIG_LD |
 386                             A10_MMC_DMA_CONFIG_ER;
 387                         dma_desc[i].next = 0;
 388                 }
 389         }
 390 }
 391
 392 static int
 393 a10_mmc_prepare_dma(struct a10_mmc_softc *sc)
 394 {
 395         bus_dmasync_op_t sync_op;
 396         int error;
 397         struct mmc_command *cmd;
 398         uint32_t val;
 399
 400         cmd = sc->a10_req->cmd;
 401         if (cmd->data->len > A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS)
 402                 return (EFBIG);
 403         error = bus_dmamap_load(sc->a10_dma_buf_tag, sc->a10_dma_buf_map,
 404             cmd->data->data, cmd->data->len, a10_dma_cb, sc, BUS_DMA_NOWAIT);
 405         if (error)
 406                 return (error);
 407         if (sc->a10_dma_map_err)
 408                 return (sc->a10_dma_map_err);
 409
 410         sc->a10_dma_inuse = 1;
 411         if (cmd->data->flags & MMC_DATA_WRITE)
 412                 sync_op = BUS_DMASYNC_PREWRITE;
 413         else
 414                 sync_op = BUS_DMASYNC_PREREAD;
 415         bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, sync_op);
 416         bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE);
 417
 418         val = A10_MMC_READ_4(sc, A10_MMC_IMASK);
 419         val &= ~(A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ);
 420         A10_MMC_WRITE_4(sc, A10_MMC_IMASK, val);
 421         val = A10_MMC_READ_4(sc, A10_MMC_GCTRL);
 422         val &= ~A10_MMC_ACCESS_BY_AHB;
 423         val |= A10_MMC_DMA_ENABLE;
 424         A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, val);
 425         val |= A10_MMC_DMA_RESET;
 426         A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, val);
 427         A10_MMC_WRITE_4(sc, A10_MMC_DMAC, A10_MMC_IDMAC_SOFT_RST);
 428         A10_MMC_WRITE_4(sc, A10_MMC_DMAC,
 429             A10_MMC_IDMAC_IDMA_ON | A10_MMC_IDMAC_FIX_BURST);
 430         val = A10_MMC_READ_4(sc, A10_MMC_IDIE);
 431         val &= ~(A10_MMC_IDMAC_RECEIVE_INT | A10_MMC_IDMAC_TRANSMIT_INT);
 432         if (cmd->data->flags & MMC_DATA_WRITE)
 433                 val |= A10_MMC_IDMAC_TRANSMIT_INT;
 434         else
 435                 val |= A10_MMC_IDMAC_RECEIVE_INT;
 436         A10_MMC_WRITE_4(sc, A10_MMC_IDIE, val);
 437         A10_MMC_WRITE_4(sc, A10_MMC_DLBA, sc->a10_dma_desc_phys);
 438         A10_MMC_WRITE_4(sc, A10_MMC_FTRGL, A10_MMC_DMA_FTRGLEVEL);
 439
 440         return (0);
 441 }
 442
 443 static int
 444 a10_mmc_reset(struct a10_mmc_softc *sc)
 445 {
 446         int timeout;
 447
 448         A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,
 449             A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_RESET);
 450         timeout = 1000;
 451         while (--timeout > 0) {
 452                 if ((A10_MMC_READ_4(sc, A10_MMC_GCTRL) & A10_MMC_RESET) == 0)
 453                         break;
 454                 DELAY(100);
 455         }
 456         if (timeout == 0)
 457                 return (ETIMEDOUT);
 458
 459         /* Set the timeout. */
 460         A10_MMC_WRITE_4(sc, A10_MMC_TIMEOUT, 0xffffffff);
 461
 462         /* Clear pending interrupts. */
 463         A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff);
 464         A10_MMC_WRITE_4(sc, A10_MMC_IDST, 0xffffffff);
 465         /* Unmask interrupts. */
 466         A10_MMC_WRITE_4(sc, A10_MMC_IMASK,
 467             A10_MMC_CMD_DONE | A10_MMC_INT_ERR_BIT |
 468             A10_MMC_DATA_OVER | A10_MMC_AUTOCMD_DONE);
 469         /* Enable interrupts and AHB access. */
 470         A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,
 471             A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE);
 472
 473         return (0);
 474 }
 475
 476 static void
 477 a10_mmc_req_done(struct a10_mmc_softc *sc)
 478 {
 479         struct mmc_command *cmd;
 480         struct mmc_request *req;
 481
 482         cmd = sc->a10_req->cmd;
 483         if (cmd->error != MMC_ERR_NONE) {
 484                 /* Reset the controller. */
 485                 a10_mmc_reset(sc);
 486                 a10_mmc_update_clock(sc);
 487         }
 488         if (sc->a10_dma_inuse == 0) {
 489                 /* Reset the FIFO. */
 490                 A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,
 491                     A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_FIFO_RESET);
 492         }
 493
 494         req = sc->a10_req;
 495         callout_stop(&sc->a10_timeoutc);
 496         sc->a10_req = NULL;
 497         sc->a10_intr = 0;
 498         sc->a10_resid = 0;
 499         sc->a10_dma_inuse = 0;
 500         sc->a10_dma_map_err = 0;
 501         sc->a10_intr_wait = 0;
 502         req->done(req);
 503 }
 504
 505 static void
 506 a10_mmc_req_ok(struct a10_mmc_softc *sc)
 507 {
 508         int timeout;
 509         struct mmc_command *cmd;
 510         uint32_t status;
 511
 512         timeout = 1000;
 513         while (--timeout > 0) {
 514                 status = A10_MMC_READ_4(sc, A10_MMC_STAS);
 515                 if ((status & A10_MMC_CARD_DATA_BUSY) == 0)
 516                         break;
 517                 DELAY(1000);
 518         }
 519         cmd = sc->a10_req->cmd;
 520         if (timeout == 0) {
 521                 cmd->error = MMC_ERR_FAILED;
 522                 a10_mmc_req_done(sc);
 523                 return;
 524         }
 525         if (cmd->flags & MMC_RSP_PRESENT) {
 526                 if (cmd->flags & MMC_RSP_136) {
 527                         cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP3);
 528                         cmd->resp[1] = A10_MMC_READ_4(sc, A10_MMC_RESP2);
 529                         cmd->resp[2] = A10_MMC_READ_4(sc, A10_MMC_RESP1);
 530                         cmd->resp[3] = A10_MMC_READ_4(sc, A10_MMC_RESP0);
 531                 } else
 532                         cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP0);
 533         }
 534         /* All data has been transferred ? */
 535         if (cmd->data != NULL && (sc->a10_resid << 2) < cmd->data->len)
 536                 cmd->error = MMC_ERR_FAILED;
 537         a10_mmc_req_done(sc);
 538 }
 539
 540 static void
 541 a10_mmc_timeout(void *arg)
 542 {
 543         struct a10_mmc_softc *sc;
 544
 545         sc = (struct a10_mmc_softc *)arg;
 546         if (sc->a10_req != NULL) {
 547                 device_printf(sc->a10_dev, "controller timeout\n");
 548                 sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
 549                 a10_mmc_req_done(sc);
 550         } else
 551                 device_printf(sc->a10_dev,
 552                     "Spurious timeout - no active request\n");
 553 }
 554
 555 static int
 556 a10_mmc_pio_transfer(struct a10_mmc_softc *sc, struct mmc_data *data)
 557 {
 558         int i, write;
 559         uint32_t bit, *buf;
 560
 561         buf = (uint32_t *)data->data;
 562         write = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
 563         bit = write ? A10_MMC_FIFO_FULL : A10_MMC_FIFO_EMPTY;
 564         for (i = sc->a10_resid; i < (data->len >> 2); i++) {
 565                 if ((A10_MMC_READ_4(sc, A10_MMC_STAS) & bit))
 566                         return (1);
 567                 if (write)
 568                         A10_MMC_WRITE_4(sc, sc->a10_fifo_reg, buf[i]);
 569                 else
 570                         buf[i] = A10_MMC_READ_4(sc, sc->a10_fifo_reg);
 571                 sc->a10_resid = i + 1;
 572         }
 573
 574         return (0);
 575 }
 576
 577 static void
 578 a10_mmc_intr(void *arg)
 579 {
 580         bus_dmasync_op_t sync_op;
 581         struct a10_mmc_softc *sc;
 582         struct mmc_data *data;
 583         uint32_t idst, imask, rint;
 584
 585         sc = (struct a10_mmc_softc *)arg;
 586         A10_MMC_LOCK(sc);
 587         rint = A10_MMC_READ_4(sc, A10_MMC_RINTR);
 588         idst = A10_MMC_READ_4(sc, A10_MMC_IDST);
 589         imask = A10_MMC_READ_4(sc, A10_MMC_IMASK);
 590         if (idst == 0 && imask == 0 && rint == 0) {
 591                 A10_MMC_UNLOCK(sc);
 592                 return;
 593         }
 594 #ifdef DEBUG
 595         device_printf(sc->a10_dev, "idst: %#x, imask: %#x, rint: %#x\n",
 596             idst, imask, rint);
 597 #endif
 598         if (sc->a10_req == NULL) {
 599                 device_printf(sc->a10_dev,
 600                     "Spurious interrupt - no active request, rint: 0x%08X\n",
 601                     rint);
 602                 goto end;
 603         }
 604         if (rint & A10_MMC_INT_ERR_BIT) {
 605                 device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint);
 606                 if (rint & A10_MMC_RESP_TIMEOUT)
 607                         sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
 608                 else
 609                         sc->a10_req->cmd->error = MMC_ERR_FAILED;
 610                 a10_mmc_req_done(sc);
 611                 goto end;
 612         }
 613         if (idst & A10_MMC_IDMAC_ERROR) {
 614                 device_printf(sc->a10_dev, "error idst: 0x%08x\n", idst);
 615                 sc->a10_req->cmd->error = MMC_ERR_FAILED;
 616                 a10_mmc_req_done(sc);
 617                 goto end;
 618         }
 619
 620         sc->a10_intr |= rint;
 621         data = sc->a10_req->cmd->data;
 622         if (data != NULL && sc->a10_dma_inuse == 1 &&
 623             (idst & A10_MMC_IDMAC_COMPLETE)) {
 624                 if (data->flags & MMC_DATA_WRITE)
 625                         sync_op = BUS_DMASYNC_POSTWRITE;
 626                 else
 627                         sync_op = BUS_DMASYNC_POSTREAD;
 628                 bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map,
 629                     sync_op);
 630                 bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map,
 631                     BUS_DMASYNC_POSTWRITE);
 632                 bus_dmamap_unload(sc->a10_dma_buf_tag, sc->a10_dma_buf_map);
 633                 sc->a10_resid = data->len >> 2;
 634         } else if (data != NULL && sc->a10_dma_inuse == 0 &&
 635             (rint & (A10_MMC_DATA_OVER | A10_MMC_RX_DATA_REQ |
 636             A10_MMC_TX_DATA_REQ)) != 0)
 637                 a10_mmc_pio_transfer(sc, data);
 638         if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)
 639                 a10_mmc_req_ok(sc);
 640
 641 end:
 642         A10_MMC_WRITE_4(sc, A10_MMC_IDST, idst);
 643         A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint);
 644         A10_MMC_UNLOCK(sc);
 645 }
 646
 647 static int
 648 a10_mmc_request(device_t bus, device_t child, struct mmc_request *req)
 649 {
 650         int blksz;
 651         struct a10_mmc_softc *sc;
 652         struct mmc_command *cmd;
 653         uint32_t cmdreg, val;
 654
 655         sc = device_get_softc(bus);
 656         A10_MMC_LOCK(sc);
 657         if (sc->a10_req) {
 658                 A10_MMC_UNLOCK(sc);
 659                 return (EBUSY);
 660         }
 661         sc->a10_req = req;
 662         cmd = req->cmd;
 663         cmdreg = A10_MMC_START;
 664         if (cmd->opcode == MMC_GO_IDLE_STATE)
 665                 cmdreg |= A10_MMC_SEND_INIT_SEQ;
 666         if (cmd->flags & MMC_RSP_PRESENT)
 667                 cmdreg |= A10_MMC_RESP_EXP;
 668         if (cmd->flags & MMC_RSP_136)
 669                 cmdreg |= A10_MMC_LONG_RESP;
 670         if (cmd->flags & MMC_RSP_CRC)
 671                 cmdreg |= A10_MMC_CHECK_RESP_CRC;
 672
 673         sc->a10_intr = 0;
 674         sc->a10_resid = 0;
 675         sc->a10_intr_wait = A10_MMC_CMD_DONE;
 676         cmd->error = MMC_ERR_NONE;
 677         if (cmd->data != NULL) {
 678                 sc->a10_intr_wait |= A10_MMC_DATA_OVER;
 679                 cmdreg |= A10_MMC_DATA_EXP | A10_MMC_WAIT_PREOVER;
 680                 if (cmd->data->flags & MMC_DATA_MULTI) {
 681                         cmdreg |= A10_MMC_SEND_AUTOSTOP;
 682                         sc->a10_intr_wait |= A10_MMC_AUTOCMD_DONE;
 683                 }
 684                 if (cmd->data->flags & MMC_DATA_WRITE)
 685                         cmdreg |= A10_MMC_WRITE;
 686                 blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
 687                 A10_MMC_WRITE_4(sc, A10_MMC_BLKSZ, blksz);
 688                 A10_MMC_WRITE_4(sc, A10_MMC_BCNTR, cmd->data->len);
 689
 690                 if (a10_mmc_pio_mode == 0)
 691                         a10_mmc_prepare_dma(sc);
 692                 /* Enable PIO access if sc->a10_dma_inuse is not set. */
 693                 if (sc->a10_dma_inuse == 0) {
 694                         val = A10_MMC_READ_4(sc, A10_MMC_GCTRL);
 695                         val &= ~A10_MMC_DMA_ENABLE;
 696                         val |= A10_MMC_ACCESS_BY_AHB;
 697                         A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, val);
 698                         val = A10_MMC_READ_4(sc, A10_MMC_IMASK);
 699                         val |= A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ;
 700                         A10_MMC_WRITE_4(sc, A10_MMC_IMASK, val);
 701                 }
 702         }
 703
 704         A10_MMC_WRITE_4(sc, A10_MMC_CARG, cmd->arg);
 705         A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg | cmd->opcode);
 706         callout_reset(&sc->a10_timeoutc, sc->a10_timeout * hz,
 707             a10_mmc_timeout, sc);
 708         A10_MMC_UNLOCK(sc);
 709
 710         return (0);
 711 }
 712
 713 static int
 714 a10_mmc_read_ivar(device_t bus, device_t child, int which,
 715     uintptr_t *result)
 716 {
 717         struct a10_mmc_softc *sc;
 718
 719         sc = device_get_softc(bus);
 720         switch (which) {
 721         default:
 722                 return (EINVAL);
 723         case MMCBR_IVAR_BUS_MODE:
 724                 *(int *)result = sc->a10_host.ios.bus_mode;
 725                 break;
 726         case MMCBR_IVAR_BUS_WIDTH:
 727                 *(int *)result = sc->a10_host.ios.bus_width;
 728                 break;
 729         case MMCBR_IVAR_CHIP_SELECT:
 730                 *(int *)result = sc->a10_host.ios.chip_select;
 731                 break;
 732         case MMCBR_IVAR_CLOCK:
 733                 *(int *)result = sc->a10_host.ios.clock;
 734                 break;
 735         case MMCBR_IVAR_F_MIN:
 736                 *(int *)result = sc->a10_host.f_min;
 737                 break;
 738         case MMCBR_IVAR_F_MAX:
 739                 *(int *)result = sc->a10_host.f_max;
 740                 break;
 741         case MMCBR_IVAR_HOST_OCR:
 742                 *(int *)result = sc->a10_host.host_ocr;
 743                 break;
 744         case MMCBR_IVAR_MODE:
 745                 *(int *)result = sc->a10_host.mode;
 746                 break;
 747         case MMCBR_IVAR_OCR:
 748                 *(int *)result = sc->a10_host.ocr;
 749                 break;
 750         case MMCBR_IVAR_POWER_MODE:
 751                 *(int *)result = sc->a10_host.ios.power_mode;
 752                 break;
 753         case MMCBR_IVAR_VDD:
 754                 *(int *)result = sc->a10_host.ios.vdd;
 755                 break;
 756         case MMCBR_IVAR_CAPS:
 757                 *(int *)result = sc->a10_host.caps;
 758                 break;
 759         case MMCBR_IVAR_MAX_DATA:
 760                 *(int *)result = 65535;
 761                 break;
 762         }
 763
 764         return (0);
 765 }
 766
 767 static int
 768 a10_mmc_write_ivar(device_t bus, device_t child, int which,
 769     uintptr_t value)
 770 {
 771         struct a10_mmc_softc *sc;
 772
 773         sc = device_get_softc(bus);
 774         switch (which) {
 775         default:
 776                 return (EINVAL);
 777         case MMCBR_IVAR_BUS_MODE:
 778                 sc->a10_host.ios.bus_mode = value;
 779                 break;
 780         case MMCBR_IVAR_BUS_WIDTH:
 781                 sc->a10_host.ios.bus_width = value;
 782                 break;
 783         case MMCBR_IVAR_CHIP_SELECT:
 784                 sc->a10_host.ios.chip_select = value;
 785                 break;
 786         case MMCBR_IVAR_CLOCK:
 787                 sc->a10_host.ios.clock = value;
 788                 break;
 789         case MMCBR_IVAR_MODE:
 790                 sc->a10_host.mode = value;
 791                 break;
 792         case MMCBR_IVAR_OCR:
 793                 sc->a10_host.ocr = value;
 794                 break;
 795         case MMCBR_IVAR_POWER_MODE:
 796                 sc->a10_host.ios.power_mode = value;
 797                 break;
 798         case MMCBR_IVAR_VDD:
 799                 sc->a10_host.ios.vdd = value;
 800                 break;
 801         /* These are read-only */
 802         case MMCBR_IVAR_CAPS:
 803         case MMCBR_IVAR_HOST_OCR:
 804         case MMCBR_IVAR_F_MIN:
 805         case MMCBR_IVAR_F_MAX:
 806         case MMCBR_IVAR_MAX_DATA:
 807                 return (EINVAL);
 808         }
 809
 810         return (0);
 811 }
 812
 813 static int
 814 a10_mmc_update_clock(struct a10_mmc_softc *sc)
 815 {
 816         uint32_t cmdreg;
 817         int retry;
 818
 819         cmdreg = A10_MMC_START | A10_MMC_UPCLK_ONLY |
 820             A10_MMC_WAIT_PREOVER;
 821         A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg);
 822         retry = 0xfffff;
 823         while (--retry > 0) {
 824                 if ((A10_MMC_READ_4(sc, A10_MMC_CMDR) & A10_MMC_START) == 0) {
 825                         A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff);
 826                         return (0);
 827                 }
 828                 DELAY(10);
 829         }
 830         A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff);
 831         device_printf(sc->a10_dev, "timeout updating clock\n");
 832
 833         return (ETIMEDOUT);
 834 }
 835
 836 static int
 837 a10_mmc_update_ios(device_t bus, device_t child)
 838 {
 839         int error;
 840         struct a10_mmc_softc *sc;
 841         struct mmc_ios *ios;
 842         uint32_t clkcr;
 843
 844         sc = device_get_softc(bus);
 845         clkcr = A10_MMC_READ_4(sc, A10_MMC_CLKCR);
 846         if (clkcr & A10_MMC_CARD_CLK_ON) {
 847                 /* Disable clock. */
 848                 clkcr &= ~A10_MMC_CARD_CLK_ON;
 849                 A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr);
 850                 error = a10_mmc_update_clock(sc);
 851                 if (error != 0)
 852                         return (error);
 853         }
 854
 855         ios = &sc->a10_host.ios;
 856         if (ios->clock) {
 857                 /* Reset the divider. */
 858                 clkcr &= ~A10_MMC_CLKCR_DIV;
 859                 A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr);
 860                 error = a10_mmc_update_clock(sc);
 861                 if (error != 0)
 862                         return (error);
 863
 864                 /* Set the MMC clock. */
 865                 error = clk_set_freq(sc->a10_clk_mmc, ios->clock,
 866                     CLK_SET_ROUND_DOWN);
 867                 if (error != 0) {
 868                         device_printf(sc->a10_dev,
 869                             "failed to set frequency to %u Hz: %d\n",
 870                             ios->clock, error);
 871                         return (error);
 872                 }
 873
 874                 /* Enable clock. */
 875                 clkcr |= A10_MMC_CARD_CLK_ON;
 876                 A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr);
 877                 error = a10_mmc_update_clock(sc);
 878                 if (error != 0)
 879                         return (error);
 880         }
 881
 882         /* Set the bus width. */
 883         switch (ios->bus_width) {
 884         case bus_width_1:
 885                 A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH1);
 886                 break;
 887         case bus_width_4:
 888                 A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH4);
 889                 break;
 890         case bus_width_8:
 891                 A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH8);
 892                 break;
 893         }
 894
 895         return (0);
 896 }
 897
 898 static int
 899 a10_mmc_get_ro(device_t bus, device_t child)
 900 {
 901
 902         return (0);
 903 }
 904
 905 static int
 906 a10_mmc_acquire_host(device_t bus, device_t child)
 907 {
 908         struct a10_mmc_softc *sc;
 909         int error;
 910
 911         sc = device_get_softc(bus);
 912         A10_MMC_LOCK(sc);
 913         while (sc->a10_bus_busy) {
 914                 error = msleep(sc, &sc->a10_mtx, PCATCH, "mmchw", 0);
 915                 if (error != 0) {
 916                         A10_MMC_UNLOCK(sc);
 917                         return (error);
 918                 }
 919         }
 920         sc->a10_bus_busy++;
 921         A10_MMC_UNLOCK(sc);
 922
 923         return (0);
 924 }
 925
 926 static int
 927 a10_mmc_release_host(device_t bus, device_t child)
 928 {
 929         struct a10_mmc_softc *sc;
 930
 931         sc = device_get_softc(bus);
 932         A10_MMC_LOCK(sc);
 933         sc->a10_bus_busy--;
 934         wakeup(sc);
 935         A10_MMC_UNLOCK(sc);
 936
 937         return (0);
 938 }
 939
 940 static device_method_t a10_mmc_methods[] = {
 941         /* Device interface */
 942         DEVMETHOD(device_probe,         a10_mmc_probe),
 943         DEVMETHOD(device_attach,        a10_mmc_attach),
 944         DEVMETHOD(device_detach,        a10_mmc_detach),
 945
 946         /* Bus interface */
 947         DEVMETHOD(bus_read_ivar,        a10_mmc_read_ivar),
 948         DEVMETHOD(bus_write_ivar,       a10_mmc_write_ivar),
 949         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 950
 951         /* MMC bridge interface */
 952         DEVMETHOD(mmcbr_update_ios,     a10_mmc_update_ios),
 953         DEVMETHOD(mmcbr_request,        a10_mmc_request),
 954         DEVMETHOD(mmcbr_get_ro,         a10_mmc_get_ro),
 955         DEVMETHOD(mmcbr_acquire_host,   a10_mmc_acquire_host),
 956         DEVMETHOD(mmcbr_release_host,   a10_mmc_release_host),
 957
 958         DEVMETHOD_END
 959 };
 960
 961 static devclass_t a10_mmc_devclass;
 962
 963 static driver_t a10_mmc_driver = {
 964         "a10_mmc",
 965         a10_mmc_methods,
 966         sizeof(struct a10_mmc_softc),
 967 };
 968
 969 DRIVER_MODULE(a10_mmc, simplebus, a10_mmc_driver, a10_mmc_devclass, 0, 0);
 970 DRIVER_MODULE(mmc, a10_mmc, mmc_driver, mmc_devclass, NULL, NULL);
 971 MODULE_DEPEND(a10_mmc, mmc, 1, 1, 1);