2 * Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define A10_MMC_GCTRL 0x00 /* Global Control Register */
33 #define A10_MMC_CLKCR 0x04 /* Clock Control Register */
34 #define A10_MMC_TIMEOUT 0x08 /* Timeout Register */
35 #define A10_MMC_WIDTH 0x0C /* Bus Width Register */
36 #define A10_MMC_BLKSZ 0x10 /* Block Size Register */
37 #define A10_MMC_BCNTR 0x14 /* Byte Count Register */
38 #define A10_MMC_CMDR 0x18 /* Command Register */
39 #define A10_MMC_CARG 0x1C /* Argument Register */
40 #define A10_MMC_RESP0 0x20 /* Response Register 0 */
41 #define A10_MMC_RESP1 0x24 /* Response Register 1 */
42 #define A10_MMC_RESP2 0x28 /* Response Register 2 */
43 #define A10_MMC_RESP3 0x2C /* Response Register 3 */
44 #define A10_MMC_IMASK 0x30 /* Interrupt Mask Register */
45 #define A10_MMC_MISTA 0x34 /* Masked Interrupt Status Register */
46 #define A10_MMC_RINTR 0x38 /* Raw Interrupt Status Register */
47 #define A10_MMC_STAS 0x3C /* Status Register */
48 #define A10_MMC_FTRGL 0x40 /* FIFO Threshold Watermark Register */
49 #define A10_MMC_FUNS 0x44 /* Function Select Register */
50 #define A10_MMC_CBCR 0x48 /* CIU Byte Count Register */
51 #define A10_MMC_BBCR 0x4C /* BIU Byte Count Register */
52 #define A10_MMC_DBGC 0x50 /* Debug Enable Register */
53 #define A10_MMC_DMAC 0x80 /* IDMAC Control Register */
54 #define A10_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */
55 #define A10_MMC_IDST 0x88 /* IDMAC Status Register */
56 #define A10_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */
57 #define A10_MMC_CHDA 0x90
58 #define A10_MMC_CBDA 0x94
59 #define A10_MMC_FIFO 0x100 /* FIFO Access Address */
62 #define A10_MMC_SOFT_RESET (1U << 0)
63 #define A10_MMC_FIFO_RESET (1U << 1)
64 #define A10_MMC_DMA_RESET (1U << 2)
65 #define A10_MMC_INT_ENABLE (1U << 4)
66 #define A10_MMC_DMA_ENABLE (1U << 5)
67 #define A10_MMC_DEBOUNCE_ENABLE (1U << 8)
68 #define A10_MMC_DDR_MODE (1U << 10)
69 #define A10_MMC_ACCESS_BY_AHB (1U << 31)
70 #define A10_MMC_RESET \
71 (A10_MMC_SOFT_RESET | A10_MMC_FIFO_RESET | A10_MMC_DMA_RESET)
74 #define A10_MMC_CARD_CLK_ON (1U << 16)
75 #define A10_MMC_LOW_POWER_ON (1U << 17)
76 #define A10_MMC_CLKCR_DIV 0xff
79 #define A10_MMC_WIDTH1 0
80 #define A10_MMC_WIDTH4 1
81 #define A10_MMC_WIDTH8 2
84 #define A10_MMC_RESP_EXP (1U << 6)
85 #define A10_MMC_LONG_RESP (1U << 7)
86 #define A10_MMC_CHECK_RESP_CRC (1U << 8)
87 #define A10_MMC_DATA_EXP (1U << 9)
88 #define A10_MMC_WRITE (1U << 10)
89 #define A10_MMC_SEQ_MODE (1U << 11)
90 #define A10_MMC_SEND_AUTOSTOP (1U << 12)
91 #define A10_MMC_WAIT_PREOVER (1U << 13)
92 #define A10_MMC_STOP_ABORT_CMD (1U << 14)
93 #define A10_MMC_SEND_INIT_SEQ (1U << 15)
94 #define A10_MMC_UPCLK_ONLY (1U << 21)
95 #define A10_MMC_RDCEATADEV (1U << 22)
96 #define A10_MMC_CCS_EXP (1U << 23)
97 #define A10_MMC_ENB_BOOT (1U << 24)
98 #define A10_MMC_ALT_BOOT_OPT (1U << 25)
99 #define A10_MMC_BOOT_ACK_EXP (1U << 26)
100 #define A10_MMC_DISABLE_BOOT (1U << 27)
101 #define A10_MMC_VOL_SWITCH (1U << 28)
102 #define A10_MMC_START (1U << 31)
104 /* A10_MMC_IMASK and A10_MMC_RINTR */
105 #define A10_MMC_RESP_ERR (1U << 1)
106 #define A10_MMC_CMD_DONE (1U << 2)
107 #define A10_MMC_DATA_OVER (1U << 3)
108 #define A10_MMC_TX_DATA_REQ (1U << 4)
109 #define A10_MMC_RX_DATA_REQ (1U << 5)
110 #define A10_MMC_RESP_CRC_ERR (1U << 6)
111 #define A10_MMC_DATA_CRC_ERR (1U << 7)
112 #define A10_MMC_RESP_TIMEOUT (1U << 8)
113 #define A10_MMC_ACK_RECV (1U << 8)
114 #define A10_MMC_DATA_TIMEOUT (1U << 9)
115 #define A10_MMC_BOOT_START (1U << 9)
116 #define A10_MMC_DATA_STARVE (1U << 10)
117 #define A10_MMC_VOL_CHG_DONE (1U << 10)
118 #define A10_MMC_FIFO_RUN_ERR (1U << 11)
119 #define A10_MMC_HARDW_LOCKED (1U << 12)
120 #define A10_MMC_START_BIT_ERR (1U << 13)
121 #define A10_MMC_AUTOCMD_DONE (1U << 14)
122 #define A10_MMC_END_BIT_ERR (1U << 15)
123 #define A10_MMC_SDIO_INT (1U << 16)
124 #define A10_MMC_CARD_INSERT (1U << 30)
125 #define A10_MMC_CARD_REMOVE (1U << 31)
126 #define A10_MMC_INT_ERR_BIT \
127 (A10_MMC_RESP_ERR | A10_MMC_RESP_CRC_ERR | \
128 A10_MMC_DATA_CRC_ERR | A10_MMC_RESP_TIMEOUT | \
129 A10_MMC_FIFO_RUN_ERR | A10_MMC_HARDW_LOCKED | \
130 A10_MMC_START_BIT_ERR | A10_MMC_END_BIT_ERR)
133 #define A10_MMC_RX_WLFLAG (1U << 0)
134 #define A10_MMC_TX_WLFLAG (1U << 1)
135 #define A10_MMC_FIFO_EMPTY (1U << 2)
136 #define A10_MMC_FIFO_FULL (1U << 3)
137 #define A10_MMC_CARD_PRESENT (1U << 8)
138 #define A10_MMC_CARD_DATA_BUSY (1U << 9)
139 #define A10_MMC_DATA_FSM_BUSY (1U << 10)
140 #define A10_MMC_DMA_REQ (1U << 31)
141 #define A10_MMC_FIFO_SIZE 16
144 #define A10_MMC_CE_ATA_ON (0xceaaU << 16)
145 #define A10_MMC_SEND_IRQ_RESP (1U << 0)
146 #define A10_MMC_SDIO_RD_WAIT (1U << 1)
147 #define A10_MMC_ABT_RD_DATA (1U << 2)
148 #define A10_MMC_SEND_CC_SD (1U << 8)
149 #define A10_MMC_SEND_AUTOSTOP_CC_SD (1U << 9)
150 #define A10_MMC_CE_ATA_DEV_INT_ENB (1U << 10)
152 /* IDMA CONTROLLER BUS MOD BIT FIELD */
153 #define A10_MMC_IDMAC_SOFT_RST (1U << 0)
154 #define A10_MMC_IDMAC_FIX_BURST (1U << 1)
155 #define A10_MMC_IDMAC_IDMA_ON (1U << 7)
156 #define A10_MMC_IDMAC_REFETCH_DES (1U << 31)
159 #define A10_MMC_IDMAC_TRANSMIT_INT (1U << 0)
160 #define A10_MMC_IDMAC_RECEIVE_INT (1U << 1)
161 #define A10_MMC_IDMAC_FATAL_BUS_ERR (1U << 2)
162 #define A10_MMC_IDMAC_DES_INVALID (1U << 4)
163 #define A10_MMC_IDMAC_CARD_ERR_SUM (1U << 5)
164 #define A10_MMC_IDMAC_NORMAL_INT_SUM (1U << 8)
165 #define A10_MMC_IDMAC_ABNORMAL_INT_SUM (1U << 9)
166 #define A10_MMC_IDMAC_HOST_ABT_INTX (1U << 10)
167 #define A10_MMC_IDMAC_HOST_ABT_INRX (1U << 10)
168 #define A10_MMC_IDMAC_IDLE (0U << 13)
169 #define A10_MMC_IDMAC_SUSPEND (1U << 13)
170 #define A10_MMC_IDMAC_DESC_RD (2U << 13)
171 #define A10_MMC_IDMAC_DESC_CHECK (3U << 13)
172 #define A10_MMC_IDMAC_RD_REQ_WAIT (4U << 13)
173 #define A10_MMC_IDMAC_WR_REQ_WAIT (5U << 13)
174 #define A10_MMC_IDMAC_RD (6U << 13)
175 #define A10_MMC_IDMAC_WR (7U << 13)
176 #define A10_MMC_IDMAC_DESC_CLOSE (8U << 13)
177 #define A10_MMC_IDMAC_ERROR \
178 (A10_MMC_IDMAC_FATAL_BUS_ERR | A10_MMC_IDMAC_CARD_ERR_SUM | \
179 A10_MMC_IDMAC_DES_INVALID | A10_MMC_IDMAC_ABNORMAL_INT_SUM)
180 #define A10_MMC_IDMAC_COMPLETE \
181 (A10_MMC_IDMAC_TRANSMIT_INT | A10_MMC_IDMAC_RECEIVE_INT)
183 /* The DMA descriptor table. */
184 struct a10_mmc_dma_desc {
186 #define A10_MMC_DMA_CONFIG_DIC (1U << 1)
187 #define A10_MMC_DMA_CONFIG_LD (1U << 2)
188 #define A10_MMC_DMA_CONFIG_FD (1U << 3)
189 #define A10_MMC_DMA_CONFIG_CH (1U << 4)
190 #define A10_MMC_DMA_CONFIG_ER (1U << 5)
191 #define A10_MMC_DMA_CONFIG_CES (1U << 30)
192 #define A10_MMC_DMA_CONFIG_OWN (1U << 31)
198 #endif /* _A10_MMC_H_ */