sys/arm/allwinner/a10_timer.c

   1 /*-
   2  * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/kernel.h>
  34 #include <sys/module.h>
  35 #include <sys/malloc.h>
  36 #include <sys/rman.h>
  37 #include <sys/timeet.h>
  38 #include <sys/timetc.h>
  39 #include <sys/watchdog.h>
  40 #include <machine/bus.h>
  41 #include <machine/intr.h>
  42 #include <machine/machdep.h>
  43
  44 #include <dev/ofw/openfirm.h>
  45 #include <dev/ofw/ofw_bus.h>
  46 #include <dev/ofw/ofw_bus_subr.h>
  47
  48 #include <dev/extres/clk/clk.h>
  49
  50 #if defined(__aarch64__)
  51 #include "opt_soc.h"
  52 #else
  53 #include <arm/allwinner/aw_machdep.h>
  54 #endif
  55
  56 /**
  57  * Timer registers addr
  58  *
  59  */
  60 #define TIMER_IRQ_EN_REG        0x00
  61 #define  TIMER_IRQ_ENABLE(x)    (1 << x)
  62
  63 #define TIMER_IRQ_STA_REG       0x04
  64 #define  TIMER_IRQ_PENDING(x)   (1 << x)
  65
  66 /*
  67  * On A10, A13, A20 and A31/A31s 6 timers are available
  68  */
  69 #define TIMER_CTRL_REG(x)               (0x10 + 0x10 * x)
  70 #define  TIMER_CTRL_START               (1 << 0)
  71 #define  TIMER_CTRL_AUTORELOAD          (1 << 1)
  72 #define  TIMER_CTRL_CLKSRC_MASK         (3 << 2)
  73 #define  TIMER_CTRL_OSC24M              (1 << 2)
  74 #define  TIMER_CTRL_PRESCALAR_MASK      (0x7 << 4)
  75 #define  TIMER_CTRL_PRESCALAR(x)        ((x - 1) << 4)
  76 #define  TIMER_CTRL_MODE_MASK           (1 << 7)
  77 #define  TIMER_CTRL_MODE_SINGLE         (1 << 7)
  78 #define  TIMER_CTRL_MODE_CONTINUOUS     (0 << 7)
  79 #define TIMER_INTV_REG(x)               (0x14 + 0x10 * x)
  80 #define TIMER_CURV_REG(x)               (0x18 + 0x10 * x)
  81
  82 /* 64 bit counter, available in A10 and A13 */
  83 #define CNT64_CTRL_REG          0xa0
  84 #define  CNT64_CTRL_RL_EN       0x02 /* read latch enable */
  85 #define CNT64_LO_REG    0xa4
  86 #define CNT64_HI_REG    0xa8
  87
  88 #define SYS_TIMER_CLKSRC        24000000 /* clock source */
  89
  90 enum a10_timer_type {
  91         A10_TIMER = 1,
  92         A23_TIMER,
  93 };
  94
  95 struct a10_timer_softc {
  96         device_t        sc_dev;
  97         struct resource *res[2];
  98         void            *sc_ih;         /* interrupt handler */
  99         uint32_t        sc_period;
 100         uint64_t        timer0_freq;
 101         struct eventtimer       et;
 102         enum a10_timer_type     type;
 103 };
 104
 105 #define timer_read_4(sc, reg)   \
 106         bus_read_4(sc->res[A10_TIMER_MEMRES], reg)
 107 #define timer_write_4(sc, reg, val)     \
 108         bus_write_4(sc->res[A10_TIMER_MEMRES], reg, val)
 109
 110 static u_int    a10_timer_get_timecount(struct timecounter *);
 111 #if defined(__arm__)
 112 static int      a10_timer_timer_start(struct eventtimer *,
 113     sbintime_t first, sbintime_t period);
 114 static int      a10_timer_timer_stop(struct eventtimer *);
 115 #endif
 116
 117 static uint64_t timer_read_counter64(struct a10_timer_softc *sc);
 118 #if defined(__arm__)
 119 static void a10_timer_eventtimer_setup(struct a10_timer_softc *sc);
 120 #endif
 121
 122 static void a23_timer_timecounter_setup(struct a10_timer_softc *sc);
 123 static u_int a23_timer_get_timecount(struct timecounter *tc);
 124
 125 static int a10_timer_irq(void *);
 126 static int a10_timer_probe(device_t);
 127 static int a10_timer_attach(device_t);
 128
 129 #if defined(__arm__)
 130 static delay_func a10_timer_delay;
 131 #endif
 132
 133 static struct timecounter a10_timer_timecounter = {
 134         .tc_name           = "a10_timer timer0",
 135         .tc_get_timecount  = a10_timer_get_timecount,
 136         .tc_counter_mask   = ~0u,
 137         .tc_frequency      = 0,
 138         .tc_quality        = 1000,
 139 };
 140
 141 static struct timecounter a23_timer_timecounter = {
 142         .tc_name           = "a10_timer timer0",
 143         .tc_get_timecount  = a23_timer_get_timecount,
 144         .tc_counter_mask   = ~0u,
 145         .tc_frequency      = 0,
 146         /* We want it to be selected over the arm generic timecounter */
 147         .tc_quality        = 2000,
 148 };
 149
 150 #define A10_TIMER_MEMRES                0
 151 #define A10_TIMER_IRQRES                1
 152
 153 static struct resource_spec a10_timer_spec[] = {
 154         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 155         { SYS_RES_IRQ,          0,      RF_ACTIVE },
 156         { -1, 0 }
 157 };
 158
 159 static struct ofw_compat_data compat_data[] = {
 160         {"allwinner,sun4i-a10-timer", A10_TIMER},
 161         {"allwinner,sun8i-a23-timer", A23_TIMER},
 162         {NULL, 0},
 163 };
 164
 165 static int
 166 a10_timer_probe(device_t dev)
 167 {
 168         struct a10_timer_softc *sc;
 169 #if defined(__arm__)
 170         u_int soc_family;
 171 #endif
 172
 173         sc = device_get_softc(dev);
 174
 175         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 176                 return (ENXIO);
 177
 178 #if defined(__arm__)
 179         /* For SoC >= A10 we have the ARM Timecounter/Eventtimer */
 180         soc_family = allwinner_soc_family();
 181         if (soc_family != ALLWINNERSOC_SUN4I &&
 182             soc_family != ALLWINNERSOC_SUN5I)
 183                 return (ENXIO);
 184 #endif
 185
 186         device_set_desc(dev, "Allwinner timer");
 187         return (BUS_PROBE_DEFAULT);
 188 }
 189
 190 static int
 191 a10_timer_attach(device_t dev)
 192 {
 193         struct a10_timer_softc *sc;
 194         clk_t clk;
 195         int err;
 196
 197         sc = device_get_softc(dev);
 198         sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
 199
 200         if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
 201                 device_printf(dev, "could not allocate resources\n");
 202                 return (ENXIO);
 203         }
 204
 205         sc->sc_dev = dev;
 206
 207         /* Setup and enable the timer interrupt */
 208         err = bus_setup_intr(dev, sc->res[A10_TIMER_IRQRES], INTR_TYPE_CLK,
 209             a10_timer_irq, NULL, sc, &sc->sc_ih);
 210         if (err != 0) {
 211                 bus_release_resources(dev, a10_timer_spec, sc->res);
 212                 device_printf(dev, "Unable to setup the clock irq handler, "
 213                     "err = %d\n", err);
 214                 return (ENXIO);
 215         }
 216
 217         if (clk_get_by_ofw_index(dev, 0, 0, &clk) != 0)
 218                 sc->timer0_freq = SYS_TIMER_CLKSRC;
 219         else {
 220                 if (clk_get_freq(clk, &sc->timer0_freq) != 0) {
 221                         device_printf(dev, "Cannot get clock source frequency\n");
 222                         return (ENXIO);
 223                 }
 224         }
 225
 226 #if defined(__arm__)
 227         a10_timer_eventtimer_setup(sc);
 228         arm_set_delay(a10_timer_delay, sc);
 229         a10_timer_timecounter.tc_priv = sc;
 230         a10_timer_timecounter.tc_frequency = sc->timer0_freq;
 231         tc_init(&a10_timer_timecounter);
 232 #elif defined(__aarch64__)
 233         a23_timer_timecounter_setup(sc);
 234 #endif
 235
 236         if (bootverbose) {
 237                 device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
 238
 239                 device_printf(sc->sc_dev, "event timer clock frequency %ju\n",
 240                     sc->timer0_freq);
 241                 device_printf(sc->sc_dev, "timecounter clock frequency %jd\n",
 242                     a10_timer_timecounter.tc_frequency);
 243         }
 244
 245         return (0);
 246 }
 247
 248 static int
 249 a10_timer_irq(void *arg)
 250 {
 251         struct a10_timer_softc *sc;
 252         uint32_t val;
 253
 254         sc = (struct a10_timer_softc *)arg;
 255
 256         /* Clear interrupt pending bit. */
 257         timer_write_4(sc, TIMER_IRQ_STA_REG, TIMER_IRQ_PENDING(0));
 258
 259         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 260
 261         /*
 262          * Disabled autoreload and sc_period > 0 means
 263          * timer_start was called with non NULL first value.
 264          * Now we will set periodic timer with the given period
 265          * value.
 266          */
 267         if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
 268                 /* Update timer */
 269                 timer_write_4(sc, TIMER_CURV_REG(0), sc->sc_period);
 270
 271                 /* Make periodic and enable */
 272                 val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
 273                 timer_write_4(sc, TIMER_CTRL_REG(0), val);
 274         }
 275
 276         if (sc->et.et_active)
 277                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 278
 279         return (FILTER_HANDLED);
 280 }
 281
 282 /*
 283  * Event timer function for A10 and A13
 284  */
 285
 286 #if defined(__arm__)
 287 static void
 288 a10_timer_eventtimer_setup(struct a10_timer_softc *sc)
 289 {
 290         uint32_t val;
 291
 292         /* Set clock source to OSC24M, 1 pre-division, continuous mode */
 293         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 294         val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
 295         val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
 296         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 297
 298         /* Enable timer0 */
 299         val = timer_read_4(sc, TIMER_IRQ_EN_REG);
 300         val |= TIMER_IRQ_ENABLE(0);
 301         timer_write_4(sc, TIMER_IRQ_EN_REG, val);
 302
 303         /* Set desired frequency in event timer and timecounter */
 304         sc->et.et_frequency = sc->timer0_freq;
 305         sc->et.et_name = "a10_timer Eventtimer";
 306         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
 307         sc->et.et_quality = 1000;
 308         sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
 309         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 310         sc->et.et_start = a10_timer_timer_start;
 311         sc->et.et_stop = a10_timer_timer_stop;
 312         sc->et.et_priv = sc;
 313         et_register(&sc->et);
 314 }
 315
 316 static int
 317 a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
 318     sbintime_t period)
 319 {
 320         struct a10_timer_softc *sc;
 321         uint32_t count;
 322         uint32_t val;
 323
 324         sc = (struct a10_timer_softc *)et->et_priv;
 325
 326         if (period != 0)
 327                 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
 328         else
 329                 sc->sc_period = 0;
 330         if (first != 0)
 331                 count = ((uint32_t)et->et_frequency * first) >> 32;
 332         else
 333                 count = sc->sc_period;
 334
 335         /* Update timer values */
 336         timer_write_4(sc, TIMER_INTV_REG(0), sc->sc_period);
 337         timer_write_4(sc, TIMER_CURV_REG(0), count);
 338
 339         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 340         if (period != 0) {
 341                 /* periodic */
 342                 val |= TIMER_CTRL_AUTORELOAD;
 343         } else {
 344                 /* oneshot */
 345                 val &= ~TIMER_CTRL_AUTORELOAD;
 346         }
 347         /* Enable timer0 */
 348         val |= TIMER_IRQ_ENABLE(0);
 349         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 350
 351         return (0);
 352 }
 353
 354 static int
 355 a10_timer_timer_stop(struct eventtimer *et)
 356 {
 357         struct a10_timer_softc *sc;
 358         uint32_t val;
 359
 360         sc = (struct a10_timer_softc *)et->et_priv;
 361
 362         /* Disable timer0 */
 363         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 364         val &= ~TIMER_CTRL_START;
 365         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 366
 367         sc->sc_period = 0;
 368
 369         return (0);
 370 }
 371 #endif
 372
 373 /*
 374  * Timecounter functions for A23 and above
 375  */
 376
 377 static void
 378 a23_timer_timecounter_setup(struct a10_timer_softc *sc)
 379 {
 380         uint32_t val;
 381
 382         /* Set clock source to OSC24M, 1 pre-division, continuous mode */
 383         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 384         val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
 385         val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
 386         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 387
 388         /* Set reload value */
 389         timer_write_4(sc, TIMER_INTV_REG(0), ~0);
 390         val = timer_read_4(sc, TIMER_INTV_REG(0));
 391
 392         /* Enable timer0 */
 393         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 394         val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
 395         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 396
 397         val = timer_read_4(sc, TIMER_CURV_REG(0));
 398
 399         a23_timer_timecounter.tc_priv = sc;
 400         a23_timer_timecounter.tc_frequency = sc->timer0_freq;
 401         tc_init(&a23_timer_timecounter);
 402 }
 403
 404 static u_int
 405 a23_timer_get_timecount(struct timecounter *tc)
 406 {
 407         struct a10_timer_softc *sc;
 408         uint32_t val;
 409
 410         sc = (struct a10_timer_softc *)tc->tc_priv;
 411         if (sc == NULL)
 412                 return (0);
 413
 414         val = timer_read_4(sc, TIMER_CURV_REG(0));
 415         /* Counter count backwards */
 416         return (~0u - val);
 417 }
 418
 419 /*
 420  * Timecounter functions for A10 and A13, using the 64 bits counter
 421  */
 422
 423 static uint64_t
 424 timer_read_counter64(struct a10_timer_softc *sc)
 425 {
 426         uint32_t lo, hi;
 427
 428         /* Latch counter, wait for it to be ready to read. */
 429         timer_write_4(sc, CNT64_CTRL_REG, CNT64_CTRL_RL_EN);
 430         while (timer_read_4(sc, CNT64_CTRL_REG) & CNT64_CTRL_RL_EN)
 431                 continue;
 432
 433         hi = timer_read_4(sc, CNT64_HI_REG);
 434         lo = timer_read_4(sc, CNT64_LO_REG);
 435
 436         return (((uint64_t)hi << 32) | lo);
 437 }
 438
 439 #if defined(__arm__)
 440 static void
 441 a10_timer_delay(int usec, void *arg)
 442 {
 443         struct a10_timer_softc *sc = arg;
 444         uint64_t end, now;
 445
 446         now = timer_read_counter64(sc);
 447         end = now + (sc->timer0_freq / 1000000) * (usec + 1);
 448
 449         while (now < end)
 450                 now = timer_read_counter64(sc);
 451 }
 452 #endif
 453
 454 static u_int
 455 a10_timer_get_timecount(struct timecounter *tc)
 456 {
 457
 458         if (tc->tc_priv == NULL)
 459                 return (0);
 460
 461         return ((u_int)timer_read_counter64(tc->tc_priv));
 462 }
 463
 464 static device_method_t a10_timer_methods[] = {
 465         DEVMETHOD(device_probe,         a10_timer_probe),
 466         DEVMETHOD(device_attach,        a10_timer_attach),
 467
 468         DEVMETHOD_END
 469 };
 470
 471 static driver_t a10_timer_driver = {
 472         "a10_timer",
 473         a10_timer_methods,
 474         sizeof(struct a10_timer_softc),
 475 };
 476
 477 static devclass_t a10_timer_devclass;
 478
 479 EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0,
 480     BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);