sys/arm/allwinner/a10_timer.c

   1 /*-
   2  * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/kernel.h>
  34 #include <sys/module.h>
  35 #include <sys/malloc.h>
  36 #include <sys/rman.h>
  37 #include <sys/timeet.h>
  38 #include <sys/timetc.h>
  39 #include <sys/watchdog.h>
  40 #include <machine/bus.h>
  41 #include <machine/intr.h>
  42 #include <machine/machdep.h>
  43
  44 #include <dev/ofw/openfirm.h>
  45 #include <dev/ofw/ofw_bus.h>
  46 #include <dev/ofw/ofw_bus_subr.h>
  47
  48 #include <dev/extres/clk/clk.h>
  49
  50 #if defined(__aarch64__)
  51 #include "opt_soc.h"
  52 #else
  53 #include <arm/allwinner/aw_machdep.h>
  54 #endif
  55
  56 /**
  57  * Timer registers addr
  58  *
  59  */
  60 #define TIMER_IRQ_EN_REG        0x00
  61 #define  TIMER_IRQ_ENABLE(x)    (1 << x)
  62
  63 #define TIMER_IRQ_STA_REG       0x04
  64 #define  TIMER_IRQ_PENDING(x)   (1 << x)
  65
  66 /*
  67  * On A10, A13, A20 and A31/A31s 6 timers are available
  68  */
  69 #define TIMER_CTRL_REG(x)               (0x10 + 0x10 * x)
  70 #define  TIMER_CTRL_START               (1 << 0)
  71 #define  TIMER_CTRL_AUTORELOAD          (1 << 1)
  72 #define  TIMER_CTRL_CLKSRC_MASK         (3 << 2)
  73 #define  TIMER_CTRL_OSC24M              (1 << 2)
  74 #define  TIMER_CTRL_PRESCALAR_MASK      (0x7 << 4)
  75 #define  TIMER_CTRL_PRESCALAR(x)        ((x - 1) << 4)
  76 #define  TIMER_CTRL_MODE_MASK           (1 << 7)
  77 #define  TIMER_CTRL_MODE_SINGLE         (1 << 7)
  78 #define  TIMER_CTRL_MODE_CONTINUOUS     (0 << 7)
  79 #define TIMER_INTV_REG(x)               (0x14 + 0x10 * x)
  80 #define TIMER_CURV_REG(x)               (0x18 + 0x10 * x)
  81
  82 /* 64 bit counter, available in A10 and A13 */
  83 #define CNT64_CTRL_REG          0xa0
  84 #define  CNT64_CTRL_RL_EN       0x02 /* read latch enable */
  85 #define CNT64_LO_REG    0xa4
  86 #define CNT64_HI_REG    0xa8
  87
  88 #define SYS_TIMER_CLKSRC        24000000 /* clock source */
  89
  90 enum a10_timer_type {
  91         A10_TIMER = 1,
  92         A23_TIMER,
  93 };
  94
  95 struct a10_timer_softc {
  96         device_t        sc_dev;
  97         struct resource *res[2];
  98         void            *sc_ih;         /* interrupt handler */
  99         uint32_t        sc_period;
 100         uint64_t        timer0_freq;
 101         struct eventtimer       et;
 102         enum a10_timer_type     type;
 103 };
 104
 105 #define timer_read_4(sc, reg)   \
 106         bus_read_4(sc->res[A10_TIMER_MEMRES], reg)
 107 #define timer_write_4(sc, reg, val)     \
 108         bus_write_4(sc->res[A10_TIMER_MEMRES], reg, val)
 109
 110 static u_int    a10_timer_get_timecount(struct timecounter *);
 111 static int      a10_timer_timer_start(struct eventtimer *,
 112     sbintime_t first, sbintime_t period);
 113 static int      a10_timer_timer_stop(struct eventtimer *);
 114
 115 static uint64_t timer_read_counter64(struct a10_timer_softc *sc);
 116 static void a10_timer_eventtimer_setup(struct a10_timer_softc *sc);
 117
 118 static void a23_timer_timecounter_setup(struct a10_timer_softc *sc);
 119 static u_int a23_timer_get_timecount(struct timecounter *tc);
 120
 121 static int a10_timer_irq(void *);
 122 static int a10_timer_probe(device_t);
 123 static int a10_timer_attach(device_t);
 124
 125 #if defined(__arm__)
 126 static delay_func a10_timer_delay;
 127 #endif
 128
 129 static struct timecounter a10_timer_timecounter = {
 130         .tc_name           = "a10_timer timer0",
 131         .tc_get_timecount  = a10_timer_get_timecount,
 132         .tc_counter_mask   = ~0u,
 133         .tc_frequency      = 0,
 134         .tc_quality        = 1000,
 135 };
 136
 137 static struct timecounter a23_timer_timecounter = {
 138         .tc_name           = "a10_timer timer0",
 139         .tc_get_timecount  = a23_timer_get_timecount,
 140         .tc_counter_mask   = ~0u,
 141         .tc_frequency      = 0,
 142         /* We want it to be selected over the arm generic timecounter */
 143         .tc_quality        = 2000,
 144 };
 145
 146 #define A10_TIMER_MEMRES                0
 147 #define A10_TIMER_IRQRES                1
 148
 149 static struct resource_spec a10_timer_spec[] = {
 150         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 151         { SYS_RES_IRQ,          0,      RF_ACTIVE },
 152         { -1, 0 }
 153 };
 154
 155 static struct ofw_compat_data compat_data[] = {
 156         {"allwinner,sun4i-a10-timer", A10_TIMER},
 157         {"allwinner,sun8i-a23-timer", A23_TIMER},
 158         {NULL, 0},
 159 };
 160
 161 static int
 162 a10_timer_probe(device_t dev)
 163 {
 164         struct a10_timer_softc *sc;
 165 #if defined(__arm__)
 166         u_int soc_family;
 167 #endif
 168
 169         sc = device_get_softc(dev);
 170
 171         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 172                 return (ENXIO);
 173
 174 #if defined(__arm__)
 175         /* For SoC >= A10 we have the ARM Timecounter/Eventtimer */
 176         soc_family = allwinner_soc_family();
 177         if (soc_family != ALLWINNERSOC_SUN4I &&
 178             soc_family != ALLWINNERSOC_SUN5I)
 179                 return (ENXIO);
 180 #endif
 181
 182         device_set_desc(dev, "Allwinner timer");
 183         return (BUS_PROBE_DEFAULT);
 184 }
 185
 186 static int
 187 a10_timer_attach(device_t dev)
 188 {
 189         struct a10_timer_softc *sc;
 190         clk_t clk;
 191         int err;
 192
 193         sc = device_get_softc(dev);
 194         sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
 195
 196         if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
 197                 device_printf(dev, "could not allocate resources\n");
 198                 return (ENXIO);
 199         }
 200
 201         sc->sc_dev = dev;
 202
 203         /* Setup and enable the timer interrupt */
 204         err = bus_setup_intr(dev, sc->res[A10_TIMER_IRQRES], INTR_TYPE_CLK,
 205             a10_timer_irq, NULL, sc, &sc->sc_ih);
 206         if (err != 0) {
 207                 bus_release_resources(dev, a10_timer_spec, sc->res);
 208                 device_printf(dev, "Unable to setup the clock irq handler, "
 209                     "err = %d\n", err);
 210                 return (ENXIO);
 211         }
 212
 213         if (clk_get_by_ofw_index(dev, 0, 0, &clk) != 0)
 214                 sc->timer0_freq = SYS_TIMER_CLKSRC;
 215         else {
 216                 if (clk_get_freq(clk, &sc->timer0_freq) != 0) {
 217                         device_printf(dev, "Cannot get clock source frequency\n");
 218                         return (ENXIO);
 219                 }
 220         }
 221
 222 #if defined(__arm__)
 223         a10_timer_eventtimer_setup(sc);
 224         arm_set_delay(a10_timer_delay, sc);
 225         a10_timer_timecounter.tc_priv = sc;
 226         a10_timer_timecounter.tc_frequency = sc->timer0_freq;
 227         tc_init(&a10_timer_timecounter);
 228 #elif defined(__aarch64__)
 229         a23_timer_timecounter_setup(sc);
 230 #endif
 231
 232         if (bootverbose) {
 233                 device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
 234
 235                 device_printf(sc->sc_dev, "event timer clock frequency %ju\n",
 236                     sc->timer0_freq);
 237                 device_printf(sc->sc_dev, "timecounter clock frequency %jd\n",
 238                     a10_timer_timecounter.tc_frequency);
 239         }
 240
 241         return (0);
 242 }
 243
 244 static int
 245 a10_timer_irq(void *arg)
 246 {
 247         struct a10_timer_softc *sc;
 248         uint32_t val;
 249
 250         sc = (struct a10_timer_softc *)arg;
 251
 252         /* Clear interrupt pending bit. */
 253         timer_write_4(sc, TIMER_IRQ_STA_REG, TIMER_IRQ_PENDING(0));
 254
 255         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 256
 257         /*
 258          * Disabled autoreload and sc_period > 0 means
 259          * timer_start was called with non NULL first value.
 260          * Now we will set periodic timer with the given period
 261          * value.
 262          */
 263         if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
 264                 /* Update timer */
 265                 timer_write_4(sc, TIMER_CURV_REG(0), sc->sc_period);
 266
 267                 /* Make periodic and enable */
 268                 val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
 269                 timer_write_4(sc, TIMER_CTRL_REG(0), val);
 270         }
 271
 272         if (sc->et.et_active)
 273                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 274
 275         return (FILTER_HANDLED);
 276 }
 277
 278 /*
 279  * Event timer function for A10 and A13
 280  */
 281
 282 static void
 283 a10_timer_eventtimer_setup(struct a10_timer_softc *sc)
 284 {
 285         uint32_t val;
 286
 287         /* Set clock source to OSC24M, 1 pre-division, continuous mode */
 288         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 289         val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
 290         val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
 291         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 292
 293         /* Enable timer0 */
 294         val = timer_read_4(sc, TIMER_IRQ_EN_REG);
 295         val |= TIMER_IRQ_ENABLE(0);
 296         timer_write_4(sc, TIMER_IRQ_EN_REG, val);
 297
 298         /* Set desired frequency in event timer and timecounter */
 299         sc->et.et_frequency = sc->timer0_freq;
 300         sc->et.et_name = "a10_timer Eventtimer";
 301         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
 302         sc->et.et_quality = 1000;
 303         sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
 304         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 305         sc->et.et_start = a10_timer_timer_start;
 306         sc->et.et_stop = a10_timer_timer_stop;
 307         sc->et.et_priv = sc;
 308         et_register(&sc->et);
 309 }
 310
 311 static int
 312 a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
 313     sbintime_t period)
 314 {
 315         struct a10_timer_softc *sc;
 316         uint32_t count;
 317         uint32_t val;
 318
 319         sc = (struct a10_timer_softc *)et->et_priv;
 320
 321         if (period != 0)
 322                 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
 323         else
 324                 sc->sc_period = 0;
 325         if (first != 0)
 326                 count = ((uint32_t)et->et_frequency * first) >> 32;
 327         else
 328                 count = sc->sc_period;
 329
 330         /* Update timer values */
 331         timer_write_4(sc, TIMER_INTV_REG(0), sc->sc_period);
 332         timer_write_4(sc, TIMER_CURV_REG(0), count);
 333
 334         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 335         if (period != 0) {
 336                 /* periodic */
 337                 val |= TIMER_CTRL_AUTORELOAD;
 338         } else {
 339                 /* oneshot */
 340                 val &= ~TIMER_CTRL_AUTORELOAD;
 341         }
 342         /* Enable timer0 */
 343         val |= TIMER_IRQ_ENABLE(0);
 344         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 345
 346         return (0);
 347 }
 348
 349 static int
 350 a10_timer_timer_stop(struct eventtimer *et)
 351 {
 352         struct a10_timer_softc *sc;
 353         uint32_t val;
 354
 355         sc = (struct a10_timer_softc *)et->et_priv;
 356
 357         /* Disable timer0 */
 358         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 359         val &= ~TIMER_CTRL_START;
 360         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 361
 362         sc->sc_period = 0;
 363
 364         return (0);
 365 }
 366
 367 /*
 368  * Timecounter functions for A23 and above
 369  */
 370
 371 static void
 372 a23_timer_timecounter_setup(struct a10_timer_softc *sc)
 373 {
 374         uint32_t val;
 375
 376         /* Set clock source to OSC24M, 1 pre-division, continuous mode */
 377         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 378         val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
 379         val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
 380         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 381
 382         /* Set reload value */
 383         timer_write_4(sc, TIMER_INTV_REG(0), ~0);
 384         val = timer_read_4(sc, TIMER_INTV_REG(0));
 385
 386         /* Enable timer0 */
 387         val = timer_read_4(sc, TIMER_CTRL_REG(0));
 388         val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
 389         timer_write_4(sc, TIMER_CTRL_REG(0), val);
 390
 391         val = timer_read_4(sc, TIMER_CURV_REG(0));
 392
 393         a23_timer_timecounter.tc_priv = sc;
 394         a23_timer_timecounter.tc_frequency = sc->timer0_freq;
 395         tc_init(&a23_timer_timecounter);
 396 }
 397
 398 static u_int
 399 a23_timer_get_timecount(struct timecounter *tc)
 400 {
 401         struct a10_timer_softc *sc;
 402         uint32_t val;
 403
 404         sc = (struct a10_timer_softc *)tc->tc_priv;
 405         if (sc == NULL)
 406                 return (0);
 407
 408         val = timer_read_4(sc, TIMER_CURV_REG(0));
 409         /* Counter count backwards */
 410         return (~0u - val);
 411 }
 412
 413 /*
 414  * Timecounter functions for A10 and A13, using the 64 bits counter
 415  */
 416
 417 static uint64_t
 418 timer_read_counter64(struct a10_timer_softc *sc)
 419 {
 420         uint32_t lo, hi;
 421
 422         /* Latch counter, wait for it to be ready to read. */
 423         timer_write_4(sc, CNT64_CTRL_REG, CNT64_CTRL_RL_EN);
 424         while (timer_read_4(sc, CNT64_CTRL_REG) & CNT64_CTRL_RL_EN)
 425                 continue;
 426
 427         hi = timer_read_4(sc, CNT64_HI_REG);
 428         lo = timer_read_4(sc, CNT64_LO_REG);
 429
 430         return (((uint64_t)hi << 32) | lo);
 431 }
 432
 433 #if defined(__arm__)
 434 static void
 435 a10_timer_delay(int usec, void *arg)
 436 {
 437         struct a10_timer_softc *sc = arg;
 438         uint64_t end, now;
 439
 440         now = timer_read_counter64(sc);
 441         end = now + (sc->timer0_freq / 1000000) * (usec + 1);
 442
 443         while (now < end)
 444                 now = timer_read_counter64(sc);
 445 }
 446 #endif
 447
 448 static u_int
 449 a10_timer_get_timecount(struct timecounter *tc)
 450 {
 451
 452         if (tc->tc_priv == NULL)
 453                 return (0);
 454
 455         return ((u_int)timer_read_counter64(tc->tc_priv));
 456 }
 457
 458 static device_method_t a10_timer_methods[] = {
 459         DEVMETHOD(device_probe,         a10_timer_probe),
 460         DEVMETHOD(device_attach,        a10_timer_attach),
 461
 462         DEVMETHOD_END
 463 };
 464
 465 static driver_t a10_timer_driver = {
 466         "a10_timer",
 467         a10_timer_methods,
 468         sizeof(struct a10_timer_softc),
 469 };
 470
 471 static devclass_t a10_timer_devclass;
 472
 473 EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0,
 474     BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);