2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
37 #include <sys/timeet.h>
38 #include <sys/timetc.h>
39 #include <sys/watchdog.h>
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
42 #include <machine/intr.h>
43 #include <machine/machdep.h>
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <machine/bus.h>
53 #include <arm/allwinner/aw_machdep.h>
56 * Timer registers addr
59 #define SW_TIMER_IRQ_EN_REG 0x00
60 #define SW_TIMER_IRQ_STA_REG 0x04
61 #define SW_TIMER0_CTRL_REG 0x10
62 #define SW_TIMER0_INT_VALUE_REG 0x14
63 #define SW_TIMER0_CUR_VALUE_REG 0x18
65 #define SW_COUNTER64LO_REG 0xa4
66 #define SW_COUNTER64HI_REG 0xa8
67 #define CNT64_CTRL_REG 0xa0
69 #define CNT64_RL_EN 0x02 /* read latch enable */
71 #define TIMER_ENABLE (1<<0)
72 #define TIMER_AUTORELOAD (1<<1)
73 #define TIMER_OSC24M (1<<2) /* oscillator = 24mhz */
74 #define TIMER_PRESCALAR (0<<4) /* prescalar = 1 */
76 #define SYS_TIMER_CLKSRC 24000000 /* clock source */
78 struct a10_timer_softc {
80 struct resource *res[2];
81 bus_space_tag_t sc_bst;
82 bus_space_handle_t sc_bsh;
83 void *sc_ih; /* interrupt handler */
89 int a10_timer_get_timerfreq(struct a10_timer_softc *);
91 #define timer_read_4(sc, reg) \
92 bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
93 #define timer_write_4(sc, reg, val) \
94 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
96 static u_int a10_timer_get_timecount(struct timecounter *);
97 static int a10_timer_timer_start(struct eventtimer *,
98 sbintime_t first, sbintime_t period);
99 static int a10_timer_timer_stop(struct eventtimer *);
101 static uint64_t timer_read_counter64(void);
103 static int a10_timer_hardclock(void *);
104 static int a10_timer_probe(device_t);
105 static int a10_timer_attach(device_t);
107 static delay_func a10_timer_delay;
109 static struct timecounter a10_timer_timecounter = {
110 .tc_name = "a10_timer timer0",
111 .tc_get_timecount = a10_timer_get_timecount,
112 .tc_counter_mask = ~0u,
117 struct a10_timer_softc *a10_timer_sc = NULL;
119 static struct resource_spec a10_timer_spec[] = {
120 { SYS_RES_MEMORY, 0, RF_ACTIVE },
121 { SYS_RES_IRQ, 0, RF_ACTIVE },
126 timer_read_counter64(void)
130 /* Latch counter, wait for it to be ready to read. */
131 timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
132 while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
135 hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
136 lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
138 return (((uint64_t)hi << 32) | lo);
142 a10_timer_probe(device_t dev)
144 struct a10_timer_softc *sc;
147 sc = device_get_softc(dev);
149 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-timer"))
152 soc_family = allwinner_soc_family();
153 if (soc_family != ALLWINNERSOC_SUN4I &&
154 soc_family != ALLWINNERSOC_SUN5I)
157 device_set_desc(dev, "Allwinner A10/A20 timer");
158 return (BUS_PROBE_DEFAULT);
162 a10_timer_attach(device_t dev)
164 struct a10_timer_softc *sc;
168 sc = device_get_softc(dev);
170 if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
171 device_printf(dev, "could not allocate resources\n");
176 sc->sc_bst = rman_get_bustag(sc->res[0]);
177 sc->sc_bsh = rman_get_bushandle(sc->res[0]);
179 /* Setup and enable the timer interrupt */
180 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
181 NULL, sc, &sc->sc_ih);
183 bus_release_resources(dev, a10_timer_spec, sc->res);
184 device_printf(dev, "Unable to setup the clock irq handler, "
189 /* Set clock source to OSC24M, 16 pre-division */
190 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
191 val |= TIMER_PRESCALAR | TIMER_OSC24M;
192 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
195 val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
197 timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
199 sc->timer0_freq = SYS_TIMER_CLKSRC;
201 /* Set desired frequency in event timer and timecounter */
202 sc->et.et_frequency = sc->timer0_freq;
203 sc->et.et_name = "a10_timer Eventtimer";
204 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
205 sc->et.et_quality = 1000;
206 sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
207 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
208 sc->et.et_start = a10_timer_timer_start;
209 sc->et.et_stop = a10_timer_timer_stop;
211 et_register(&sc->et);
213 if (device_get_unit(dev) == 0) {
214 arm_set_delay(a10_timer_delay, sc);
218 a10_timer_timecounter.tc_frequency = sc->timer0_freq;
219 tc_init(&a10_timer_timecounter);
222 device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
224 device_printf(sc->sc_dev, "event timer clock frequency %u\n",
226 device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
227 a10_timer_timecounter.tc_frequency);
234 a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
237 struct a10_timer_softc *sc;
241 sc = (struct a10_timer_softc *)et->et_priv;
244 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
248 count = ((uint32_t)et->et_frequency * first) >> 32;
250 count = sc->sc_period;
252 /* Update timer values */
253 timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
254 timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
256 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
259 val |= TIMER_AUTORELOAD;
262 val &= ~TIMER_AUTORELOAD;
266 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
272 a10_timer_timer_stop(struct eventtimer *et)
274 struct a10_timer_softc *sc;
277 sc = (struct a10_timer_softc *)et->et_priv;
280 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
281 val &= ~TIMER_ENABLE;
282 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
290 a10_timer_get_timerfreq(struct a10_timer_softc *sc)
292 return (sc->timer0_freq);
296 a10_timer_hardclock(void *arg)
298 struct a10_timer_softc *sc;
301 sc = (struct a10_timer_softc *)arg;
303 /* Clear interrupt pending bit. */
304 timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
306 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
308 * Disabled autoreload and sc_period > 0 means
309 * timer_start was called with non NULL first value.
310 * Now we will set periodic timer with the given period
313 if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
315 timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
317 /* Make periodic and enable */
318 val |= TIMER_AUTORELOAD | TIMER_ENABLE;
319 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
322 if (sc->et.et_active)
323 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
325 return (FILTER_HANDLED);
329 a10_timer_get_timecount(struct timecounter *tc)
332 if (a10_timer_sc == NULL)
335 return ((u_int)timer_read_counter64());
338 static device_method_t a10_timer_methods[] = {
339 DEVMETHOD(device_probe, a10_timer_probe),
340 DEVMETHOD(device_attach, a10_timer_attach),
345 static driver_t a10_timer_driver = {
348 sizeof(struct a10_timer_softc),
351 static devclass_t a10_timer_devclass;
353 EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0,
354 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
357 a10_timer_delay(int usec, void *arg)
359 struct a10_timer_softc *sc = arg;
362 now = timer_read_counter64();
363 end = now + (sc->timer0_freq / 1000000) * (usec + 1);
366 now = timer_read_counter64();