2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
38 #include <sys/resource.h>
39 #include <machine/bus.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
45 #include <dev/extres/clk/clk.h>
46 #include <dev/extres/hwreset/hwreset.h>
48 #include <dev/gpio/gpiobusvar.h>
51 #include <dev/sound/pcm/sound.h>
52 #include <dev/sound/fdt/audio_dai.h>
53 #include "audio_dai_if.h"
55 #define SYSCLK_CTL 0x00c
56 #define AIF1CLK_ENA (1 << 11)
57 #define AIF1CLK_SRC_MASK (3 << 8)
58 #define AIF1CLK_SRC_PLL (2 << 8)
59 #define SYSCLK_ENA (1 << 3)
60 #define SYSCLK_SRC (1 << 0)
62 #define MOD_CLK_ENA 0x010
63 #define MOD_RST_CTL 0x014
64 #define MOD_AIF1 (1 << 15)
65 #define MOD_ADC (1 << 3)
66 #define MOD_DAC (1 << 2)
68 #define SYS_SR_CTRL 0x018
69 #define AIF1_FS_MASK (0xf << 12)
70 #define AIF_FS_48KHZ (8 << 12)
72 #define AIF1CLK_CTRL 0x040
73 #define AIF1_MSTR_MOD (1 << 15)
74 #define AIF1_BCLK_INV (1 << 14)
75 #define AIF1_LRCK_INV (1 << 13)
76 #define AIF1_BCLK_DIV_MASK (0xf << 9)
77 #define AIF1_BCLK_DIV_16 (6 << 9)
78 #define AIF1_LRCK_DIV_MASK (7 << 6)
79 #define AIF1_LRCK_DIV_16 (0 << 6)
80 #define AIF1_LRCK_DIV_64 (2 << 6)
81 #define AIF1_WORD_SIZ_MASK (3 << 4)
82 #define AIF1_WORD_SIZ_16 (1 << 4)
83 #define AIF1_DATA_FMT_MASK (3 << 2)
84 #define AIF1_DATA_FMT_I2S (0 << 2)
85 #define AIF1_DATA_FMT_LJ (1 << 2)
86 #define AIF1_DATA_FMT_RJ (2 << 2)
87 #define AIF1_DATA_FMT_DSP (3 << 2)
89 #define AIF1_ADCDAT_CTRL 0x044
90 #define AIF1_ADC0L_ENA (1 << 15)
91 #define AIF1_ADC0R_ENA (1 << 14)
93 #define AIF1_DACDAT_CTRL 0x048
94 #define AIF1_DAC0L_ENA (1 << 15)
95 #define AIF1_DAC0R_ENA (1 << 14)
97 #define AIF1_MXR_SRC 0x04c
98 #define AIF1L_MXR_SRC_MASK (0xf << 12)
99 #define AIF1L_MXR_SRC_AIF1 (0x8 << 12)
100 #define AIF1L_MXR_SRC_ADC (0x2 << 12)
101 #define AIF1R_MXR_SRC_MASK (0xf << 8)
102 #define AIF1R_MXR_SRC_AIF1 (0x8 << 8)
103 #define AIF1R_MXR_SRC_ADC (0x2 << 8)
105 #define ADC_DIG_CTRL 0x100
106 #define ADC_DIG_CTRL_ENAD (1 << 15)
108 #define HMIC_CTRL1 0x110
109 #define HMIC_CTRL1_N_MASK (0xf << 8)
110 #define HMIC_CTRL1_N(n) (((n) & 0xf) << 8)
111 #define HMIC_CTRL1_JACK_IN_IRQ_EN (1 << 4)
112 #define HMIC_CTRL1_JACK_OUT_IRQ_EN (1 << 3)
113 #define HMIC_CTRL1_MIC_DET_IRQ_EN (1 << 0)
115 #define HMIC_CTRL2 0x114
116 #define HMIC_CTRL2_MDATA_THRES __BITS(12,8)
118 #define HMIC_STS 0x118
119 #define HMIC_STS_MIC_PRESENT (1 << 6)
120 #define HMIC_STS_JACK_DET_OIRQ (1 << 4)
121 #define HMIC_STS_JACK_DET_IIRQ (1 << 3)
122 #define HMIC_STS_MIC_DET_ST (1 << 0)
124 #define DAC_DIG_CTRL 0x120
125 #define DAC_DIG_CTRL_ENDA (1 << 15)
127 #define DAC_MXR_SRC 0x130
128 #define DACL_MXR_SRC_MASK (0xf << 12)
129 #define DACL_MXR_SRC_AIF1_DAC0L (0x8 << 12)
130 #define DACR_MXR_SRC_MASK (0xf << 8)
131 #define DACR_MXR_SRC_AIF1_DAC0R (0x8 << 8)
133 static struct ofw_compat_data compat_data[] = {
134 { "allwinner,sun8i-a33-codec", 1},
138 static struct resource_spec sun8i_codec_spec[] = {
139 { SYS_RES_MEMORY, 0, RF_ACTIVE },
140 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
144 struct sun8i_codec_softc {
146 struct resource *res[2];
153 #define CODEC_LOCK(sc) mtx_lock(&(sc)->mtx)
154 #define CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
155 #define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
156 #define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
158 static int sun8i_codec_probe(device_t dev);
159 static int sun8i_codec_attach(device_t dev);
160 static int sun8i_codec_detach(device_t dev);
163 sun8i_codec_probe(device_t dev)
165 if (!ofw_bus_status_okay(dev))
168 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
171 device_set_desc(dev, "Allwinner Codec");
172 return (BUS_PROBE_DEFAULT);
176 sun8i_codec_attach(device_t dev)
178 struct sun8i_codec_softc *sc;
181 struct gpiobus_pin *pa_pin;
184 sc = device_get_softc(dev);
186 node = ofw_bus_get_node(dev);
188 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
190 if (bus_alloc_resources(dev, sun8i_codec_spec, sc->res) != 0) {
191 device_printf(dev, "cannot allocate resources for device\n");
196 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod);
198 device_printf(dev, "cannot get \"mod\" clock\n");
202 error = clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_gate);
204 device_printf(dev, "cannot get \"bus\" clock\n");
208 error = clk_enable(sc->clk_gate);
210 device_printf(dev, "cannot enable \"bus\" clock\n");
215 val = CODEC_READ(sc, SYSCLK_CTL);
217 val &= ~AIF1CLK_SRC_MASK;
218 val |= AIF1CLK_SRC_PLL;
221 CODEC_WRITE(sc, SYSCLK_CTL, val);
222 CODEC_WRITE(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC);
223 CODEC_WRITE(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC);
225 /* Enable digital parts */
226 CODEC_WRITE(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA);
227 CODEC_WRITE(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD);
229 /* Set AIF1 to 48 kHz */
230 val = CODEC_READ(sc, SYS_SR_CTRL);
231 val &= ~AIF1_FS_MASK;
233 CODEC_WRITE(sc, SYS_SR_CTRL, val);
235 /* Set AIF1 to 16-bit */
236 val = CODEC_READ(sc, AIF1CLK_CTRL);
237 val &= ~AIF1_WORD_SIZ_MASK;
238 val |= AIF1_WORD_SIZ_16;
239 CODEC_WRITE(sc, AIF1CLK_CTRL, val);
241 /* Enable AIF1 DAC timelot 0 */
242 val = CODEC_READ(sc, AIF1_DACDAT_CTRL);
243 val |= AIF1_DAC0L_ENA;
244 val |= AIF1_DAC0R_ENA;
245 CODEC_WRITE(sc, AIF1_DACDAT_CTRL, val);
247 /* Enable AIF1 ADC timelot 0 */
248 val = CODEC_READ(sc, AIF1_ADCDAT_CTRL);
249 val |= AIF1_ADC0L_ENA;
250 val |= AIF1_ADC0R_ENA;
251 CODEC_WRITE(sc, AIF1_ADCDAT_CTRL, val);
253 /* DAC mixer source select */
254 val = CODEC_READ(sc, DAC_MXR_SRC);
255 val &= ~DACL_MXR_SRC_MASK;
256 val |= DACL_MXR_SRC_AIF1_DAC0L;
257 val &= ~DACR_MXR_SRC_MASK;
258 val |= DACR_MXR_SRC_AIF1_DAC0R;
259 CODEC_WRITE(sc, DAC_MXR_SRC, val);
261 /* ADC mixer source select */
262 val = CODEC_READ(sc, AIF1_MXR_SRC);
263 val &= ~AIF1L_MXR_SRC_MASK;
264 val |= AIF1L_MXR_SRC_ADC;
265 val &= ~AIF1R_MXR_SRC_MASK;
266 val |= AIF1R_MXR_SRC_ADC;
267 CODEC_WRITE(sc, AIF1_MXR_SRC, val);
269 /* Enable PA power */
271 if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios",
273 error = gpio_pin_set_active(pa_pin, 1);
275 device_printf(dev, "failed to unmute PA\n");
278 OF_device_register_xref(OF_xref_from_node(node), dev);
283 sun8i_codec_detach(dev);
288 sun8i_codec_detach(device_t dev)
290 struct sun8i_codec_softc *sc;
292 sc = device_get_softc(dev);
295 clk_release(sc->clk_gate);
298 clk_release(sc->clk_mod);
300 if (sc->intrhand != NULL)
301 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
303 bus_release_resources(dev, sun8i_codec_spec, sc->res);
304 mtx_destroy(&sc->mtx);
310 sun8i_codec_dai_init(device_t dev, uint32_t format)
312 struct sun8i_codec_softc *sc;
316 sc = device_get_softc(dev);
318 fmt = AUDIO_DAI_FORMAT_FORMAT(format);
319 pol = AUDIO_DAI_FORMAT_POLARITY(format);
320 clk = AUDIO_DAI_FORMAT_CLOCK(format);
322 val = CODEC_READ(sc, AIF1CLK_CTRL);
324 val &= ~AIF1_DATA_FMT_MASK;
326 case AUDIO_DAI_FORMAT_I2S:
327 val |= AIF1_DATA_FMT_I2S;
329 case AUDIO_DAI_FORMAT_RJ:
330 val |= AIF1_DATA_FMT_RJ;
332 case AUDIO_DAI_FORMAT_LJ:
333 val |= AIF1_DATA_FMT_LJ;
335 case AUDIO_DAI_FORMAT_DSPA:
336 case AUDIO_DAI_FORMAT_DSPB:
337 val |= AIF1_DATA_FMT_DSP;
343 val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV);
344 /* Codec LRCK polarity is inverted (datasheet is wrong) */
345 if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol))
346 val |= AIF1_LRCK_INV;
347 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol))
348 val |= AIF1_BCLK_INV;
351 case AUDIO_DAI_CLOCK_CBM_CFM:
352 val &= ~AIF1_MSTR_MOD; /* codec is master */
354 case AUDIO_DAI_CLOCK_CBS_CFS:
355 val |= AIF1_MSTR_MOD; /* codec is slave */
361 val &= ~AIF1_LRCK_DIV_MASK;
362 val |= AIF1_LRCK_DIV_64;
364 val &= ~AIF1_BCLK_DIV_MASK;
365 val |= AIF1_BCLK_DIV_16;
367 CODEC_WRITE(sc, AIF1CLK_CTRL, val);
373 sun8i_codec_dai_trigger(device_t dev, int go, int pcm_dir)
380 sun8i_codec_dai_setup_mixer(device_t dev, device_t pcmdev)
383 /* Do nothing for now */
388 static device_method_t sun8i_codec_methods[] = {
389 /* Device interface */
390 DEVMETHOD(device_probe, sun8i_codec_probe),
391 DEVMETHOD(device_attach, sun8i_codec_attach),
392 DEVMETHOD(device_detach, sun8i_codec_detach),
394 DEVMETHOD(audio_dai_init, sun8i_codec_dai_init),
395 DEVMETHOD(audio_dai_setup_mixer, sun8i_codec_dai_setup_mixer),
396 DEVMETHOD(audio_dai_trigger, sun8i_codec_dai_trigger),
401 static driver_t sun8i_codec_driver = {
404 sizeof(struct sun8i_codec_softc),
407 DRIVER_MODULE(sun8i_codec, simplebus, sun8i_codec_driver, 0, 0);
408 SIMPLEBUS_PNP_INFO(compat_data);