2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
37 #include <machine/bus.h>
38 #include <machine/intr.h>
40 #include <dev/fdt/fdt_common.h>
41 #include <dev/ofw/openfirm.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 * Interrupt controller registers
49 #define SW_INT_VECTOR_REG 0x00
50 #define SW_INT_BASE_ADR_REG 0x04
51 #define SW_INT_PROTECTION_REG 0x08
52 #define SW_INT_NMI_CTRL_REG 0x0c
54 #define SW_INT_IRQ_PENDING_REG0 0x10
55 #define SW_INT_IRQ_PENDING_REG1 0x14
56 #define SW_INT_IRQ_PENDING_REG2 0x18
58 #define SW_INT_FIQ_PENDING_REG0 0x20
59 #define SW_INT_FIQ_PENDING_REG1 0x24
60 #define SW_INT_FIQ_PENDING_REG2 0x28
62 #define SW_INT_SELECT_REG0 0x30
63 #define SW_INT_SELECT_REG1 0x34
64 #define SW_INT_SELECT_REG2 0x38
66 #define SW_INT_ENABLE_REG0 0x40
67 #define SW_INT_ENABLE_REG1 0x44
68 #define SW_INT_ENABLE_REG2 0x48
70 #define SW_INT_MASK_REG0 0x50
71 #define SW_INT_MASK_REG1 0x54
72 #define SW_INT_MASK_REG2 0x58
74 #define SW_INT_IRQNO_ENMI 0
76 #define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
77 #define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
78 #define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
79 #define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
80 #define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))
82 static struct ofw_compat_data compat_data[] = {
83 {"allwinner,sun4i-a10-ic", 1},
84 {"allwinner,sun7i-a20-sc-nmi", 1},
88 struct a10_aintc_softc {
90 struct resource * aintc_res;
91 bus_space_tag_t aintc_bst;
92 bus_space_handle_t aintc_bsh;
96 static struct a10_aintc_softc *a10_aintc_sc = NULL;
98 #define aintc_read_4(reg) \
99 bus_space_read_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg)
100 #define aintc_write_4(reg, val) \
101 bus_space_write_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg, val)
104 a10_aintc_probe(device_t dev)
107 if (!ofw_bus_status_okay(dev))
110 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
112 device_set_desc(dev, "A10 AINTC Interrupt Controller");
113 return (BUS_PROBE_DEFAULT);
117 a10_aintc_attach(device_t dev)
119 struct a10_aintc_softc *sc = device_get_softc(dev);
128 sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
129 if (!sc->aintc_res) {
130 device_printf(dev, "could not allocate resource\n");
134 sc->aintc_bst = rman_get_bustag(sc->aintc_res);
135 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);
139 /* Disable & clear all interrupts */
140 for (i = 0; i < 3; i++) {
141 aintc_write_4(SW_INT_ENABLE_REG(i), 0);
142 aintc_write_4(SW_INT_MASK_REG(i), 0xffffffff);
144 /* enable protection mode*/
145 aintc_write_4(SW_INT_PROTECTION_REG, 0x01);
147 /* config the external interrupt source type*/
148 aintc_write_4(SW_INT_NMI_CTRL_REG, 0x00);
153 static device_method_t a10_aintc_methods[] = {
154 DEVMETHOD(device_probe, a10_aintc_probe),
155 DEVMETHOD(device_attach, a10_aintc_attach),
159 static driver_t a10_aintc_driver = {
162 sizeof(struct a10_aintc_softc),
165 static devclass_t a10_aintc_devclass;
167 EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0,
168 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST);
171 arm_get_next_irq(int last_irq)
176 for (i = 0; i < 3; i++) {
177 value = aintc_read_4(SW_INT_IRQ_PENDING_REG(i));
178 for (b = 0; b < 32; b++)
179 if (value & (1 << b)) {
188 arm_mask_irq(uintptr_t nb)
190 uint32_t bit, block, value;
195 value = aintc_read_4(SW_INT_ENABLE_REG(block));
196 value &= ~(1 << bit);
197 aintc_write_4(SW_INT_ENABLE_REG(block), value);
199 value = aintc_read_4(SW_INT_MASK_REG(block));
201 aintc_write_4(SW_INT_MASK_REG(block), value);
205 arm_unmask_irq(uintptr_t nb)
207 uint32_t bit, block, value;
212 value = aintc_read_4(SW_INT_ENABLE_REG(block));
214 aintc_write_4(SW_INT_ENABLE_REG(block), value);
216 value = aintc_read_4(SW_INT_MASK_REG(block));
217 value &= ~(1 << bit);
218 aintc_write_4(SW_INT_MASK_REG(block), value);
220 if(nb == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */
221 aintc_write_4(SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI));