2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
37 #include <machine/bus.h>
38 #include <machine/intr.h>
40 #include <dev/fdt/fdt_common.h>
41 #include <dev/ofw/openfirm.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 * Interrupt controller registers
49 #define SW_INT_VECTOR_REG 0x00
50 #define SW_INT_BASE_ADR_REG 0x04
51 #define SW_INT_PROTECTION_REG 0x08
52 #define SW_INT_NMI_CTRL_REG 0x0c
54 #define SW_INT_IRQ_PENDING_REG0 0x10
55 #define SW_INT_IRQ_PENDING_REG1 0x14
56 #define SW_INT_IRQ_PENDING_REG2 0x18
58 #define SW_INT_FIQ_PENDING_REG0 0x20
59 #define SW_INT_FIQ_PENDING_REG1 0x24
60 #define SW_INT_FIQ_PENDING_REG2 0x28
62 #define SW_INT_SELECT_REG0 0x30
63 #define SW_INT_SELECT_REG1 0x34
64 #define SW_INT_SELECT_REG2 0x38
66 #define SW_INT_ENABLE_REG0 0x40
67 #define SW_INT_ENABLE_REG1 0x44
68 #define SW_INT_ENABLE_REG2 0x48
70 #define SW_INT_MASK_REG0 0x50
71 #define SW_INT_MASK_REG1 0x54
72 #define SW_INT_MASK_REG2 0x58
74 #define SW_INT_IRQNO_ENMI 0
76 #define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
77 #define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
78 #define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
79 #define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
80 #define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))
82 struct a10_aintc_softc {
84 struct resource * aintc_res;
85 bus_space_tag_t aintc_bst;
86 bus_space_handle_t aintc_bsh;
90 static struct a10_aintc_softc *a10_aintc_sc = NULL;
92 #define aintc_read_4(reg) \
93 bus_space_read_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg)
94 #define aintc_write_4(reg, val) \
95 bus_space_write_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg, val)
98 a10_aintc_probe(device_t dev)
100 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-ic"))
102 device_set_desc(dev, "A10 AINTC Interrupt Controller");
103 return (BUS_PROBE_DEFAULT);
107 a10_aintc_attach(device_t dev)
109 struct a10_aintc_softc *sc = device_get_softc(dev);
118 sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
119 if (!sc->aintc_res) {
120 device_printf(dev, "could not allocate resource\n");
124 sc->aintc_bst = rman_get_bustag(sc->aintc_res);
125 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);
129 /* Disable & clear all interrupts */
130 for (i = 0; i < 3; i++) {
131 aintc_write_4(SW_INT_ENABLE_REG(i), 0);
132 aintc_write_4(SW_INT_MASK_REG(i), 0xffffffff);
134 /* enable protection mode*/
135 aintc_write_4(SW_INT_PROTECTION_REG, 0x01);
137 /* config the external interrupt source type*/
138 aintc_write_4(SW_INT_NMI_CTRL_REG, 0x00);
143 static device_method_t a10_aintc_methods[] = {
144 DEVMETHOD(device_probe, a10_aintc_probe),
145 DEVMETHOD(device_attach, a10_aintc_attach),
149 static driver_t a10_aintc_driver = {
152 sizeof(struct a10_aintc_softc),
155 static devclass_t a10_aintc_devclass;
157 DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0);
160 arm_get_next_irq(int last_irq)
165 for (i = 0; i < 3; i++) {
166 value = aintc_read_4(SW_INT_IRQ_PENDING_REG(i));
167 for (b = 0; b < 32; b++)
168 if (value & (1 << b)) {
177 arm_mask_irq(uintptr_t nb)
179 uint32_t bit, block, value;
184 value = aintc_read_4(SW_INT_ENABLE_REG(block));
185 value &= ~(1 << bit);
186 aintc_write_4(SW_INT_ENABLE_REG(block), value);
188 value = aintc_read_4(SW_INT_MASK_REG(block));
190 aintc_write_4(SW_INT_MASK_REG(block), value);
194 arm_unmask_irq(uintptr_t nb)
196 uint32_t bit, block, value;
201 value = aintc_read_4(SW_INT_ENABLE_REG(block));
203 aintc_write_4(SW_INT_ENABLE_REG(block), value);
205 value = aintc_read_4(SW_INT_MASK_REG(block));
206 value &= ~(1 << bit);
207 aintc_write_4(SW_INT_MASK_REG(block), value);
209 if(nb == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */
210 aintc_write_4(SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI));