2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Allwinner Consumer IR controller
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
40 #include <sys/sysctl.h>
41 #include <machine/bus.h>
43 #include <dev/ofw/openfirm.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/extres/clk/clk.h>
47 #include <dev/extres/hwreset/hwreset.h>
49 #include <dev/evdev/input.h>
50 #include <dev/evdev/evdev.h>
52 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))
53 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))
56 #define AW_IR_CTL 0x00
58 #define AW_IR_CTL_GEN (1 << 0)
60 #define AW_IR_CTL_RXEN (1 << 1)
62 #define AW_IR_CTL_MD (1 << 4) | (1 << 5)
65 #define AW_IR_RXCTL 0x10
66 /* Pulse Polarity Invert flag */
67 #define AW_IR_RXCTL_RPPI (1 << 2)
70 #define AW_IR_RXFIFO 0x20
72 /* RX Interrupt Control */
73 #define AW_IR_RXINT 0x2C
74 /* RX FIFO Overflow */
75 #define AW_IR_RXINT_ROI_EN (1 << 0)
77 #define AW_IR_RXINT_RPEI_EN (1 << 1)
78 /* RX FIFO Data Available */
79 #define AW_IR_RXINT_RAI_EN (1 << 4)
80 /* RX FIFO available byte level */
81 #define AW_IR_RXINT_RAL(val) ((val) << 8)
83 /* RX Interrupt Status Reg */
84 #define AW_IR_RXSTA 0x30
85 /* RX FIFO Get Available Counter */
86 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1))
87 /* Clear all interrupt status */
88 #define AW_IR_RXSTA_CLEARALL 0xff
90 /* IR Sample Configure Reg */
91 #define AW_IR_CIR 0x34
94 * Frequency sample: 23437.5Hz (Cycle: 42.7us)
95 * Pulse of NEC Remote > 560us
97 /* Filter Threshold = 8 * 42.7 = ~341us < 500us */
98 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2)
99 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */
100 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8)
102 /* Bit 15 - value (pulse/space) */
103 #define VAL_MASK 0x80
104 /* Bits 0:14 - sample duration */
105 #define PERIOD_MASK 0x7f
107 /* Clock rate for IR0 or IR1 clock in CIR mode */
108 #define AW_IR_BASE_CLK 3000000
109 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */
110 #define AW_IR_SAMPLE_64 (0 << 0)
111 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */
112 #define AW_IR_SAMPLE_128 (1 << 0)
114 #define AW_IR_ERROR_CODE 0xffffffff
115 #define AW_IR_REPEAT_CODE 0x0
117 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */
118 #define AW_IR_L1_MIN 80
119 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */
120 #define AW_IR_L0_MIN 40
121 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */
122 #define AW_IR_PMAX 26
123 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */
124 #define AW_IR_DMID 26
125 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */
126 #define AW_IR_DMAX 53
128 /* Active Thresholds */
129 #define AW_IR_ACTIVE_T_VAL AW_IR_L1_MIN
130 #define AW_IR_ACTIVE_T (((AW_IR_ACTIVE_T_VAL - 1) & 0xff) << 16)
131 #define AW_IR_ACTIVE_T_C_VAL 0
132 #define AW_IR_ACTIVE_T_C ((AW_IR_ACTIVE_T_C_VAL & 0xff) << 23)
135 #define CODE_MASK 0x00ff00ff
136 #define INV_CODE_MASK 0xff00ff00
137 #define VALID_CODE_MASK 0x00ff0000
145 #define AW_IR_RAW_BUF_SIZE 128
147 SYSCTL_NODE(_hw, OID_AUTO, aw_cir, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
150 static int aw_cir_debug = 0;
151 SYSCTL_INT(_hw_aw_cir, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_cir_debug, 0,
156 struct resource *res[2];
159 int dcnt; /* Packet Count */
160 unsigned char buf[AW_IR_RAW_BUF_SIZE];
161 struct evdev_dev *sc_evdev;
164 static struct resource_spec aw_ir_spec[] = {
165 { SYS_RES_MEMORY, 0, RF_ACTIVE },
166 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
170 static struct ofw_compat_data compat_data[] = {
171 { "allwinner,sun4i-a10-ir", A10_IR },
172 { "allwinner,sun5i-a13-ir", A13_IR },
173 { "allwinner,sun6i-a31-ir", A31_IR },
178 aw_ir_buf_reset(struct aw_ir_softc *sc)
185 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data)
188 if (sc->dcnt < AW_IR_RAW_BUF_SIZE)
189 sc->buf[sc->dcnt++] = data;
192 device_printf(sc->dev, "IR RX Buffer Full!\n");
196 aw_ir_buf_full(struct aw_ir_softc *sc)
199 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE);
203 aw_ir_read_data(struct aw_ir_softc *sc)
206 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff);
210 aw_ir_decode_packets(struct aw_ir_softc *sc)
212 unsigned int len, code;
213 unsigned int active_delay;
214 unsigned char val, last;
217 if (bootverbose && __predict_false(aw_cir_debug) != 0)
218 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt);
220 /* Find Lead 1 (bit separator) */
221 active_delay = AW_IR_ACTIVE_T_VAL *
222 (AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1);
224 if (bootverbose && __predict_false(aw_cir_debug) != 0)
225 device_printf(sc->dev, "Initial len: %d\n", len);
226 for (i = 0; i < sc->dcnt; i++) {
229 len += (val & PERIOD_MASK) + 1;
231 if (len > AW_IR_L1_MIN)
236 if (bootverbose && __predict_false(aw_cir_debug) != 0)
237 device_printf(sc->dev, "len = %d\n", len);
238 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) {
239 if (bootverbose && __predict_false(aw_cir_debug) != 0)
240 device_printf(sc->dev, "Bit separator error\n");
244 /* Find Lead 0 (bit length) */
246 for (; i < sc->dcnt; i++) {
248 if (val & VAL_MASK) {
249 if(len > AW_IR_L0_MIN)
253 len += (val & PERIOD_MASK) + 1;
255 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) {
256 if (bootverbose && __predict_false(aw_cir_debug) != 0)
257 device_printf(sc->dev, "Bit length error\n");
266 for (; i < sc->dcnt; i++) {
270 len += (val & PERIOD_MASK) + 1;
272 if (len > AW_IR_PMAX) {
274 device_printf(sc->dev,
275 "Pulse error, len=%d\n",
280 len = (val & PERIOD_MASK) + 1;
283 if (val & VAL_MASK) {
284 if (len > AW_IR_DMAX) {
286 device_printf(sc->dev,
287 "Distance error, len=%d\n",
291 if (len > AW_IR_DMID) {
293 code |= 1 << bitcount;
297 break; /* Finish decoding */
300 len = (val & PERIOD_MASK) + 1;
302 len += (val & PERIOD_MASK) + 1;
309 return (AW_IR_ERROR_CODE);
313 aw_ir_validate_code(unsigned long code)
315 unsigned long v1, v2;
317 /* Don't check address */
318 v1 = code & CODE_MASK;
319 v2 = (code & INV_CODE_MASK) >> 8;
321 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK)
322 return (0); /* valid */
324 return (1); /* invalid */
328 aw_ir_intr(void *arg)
330 struct aw_ir_softc *sc;
333 unsigned long ir_code;
336 sc = (struct aw_ir_softc *)arg;
338 /* Read RX interrupt status */
339 val = READ(sc, AW_IR_RXSTA);
340 if (bootverbose && __predict_false(aw_cir_debug) != 0)
341 device_printf(sc->dev, "RX interrupt status: %x\n", val);
343 /* Clean all pending interrupt statuses */
344 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL);
346 /* When Rx FIFO Data available or Packet end */
347 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) {
348 if (bootverbose && __predict_false(aw_cir_debug) != 0)
349 device_printf(sc->dev,
350 "RX FIFO Data available or Packet end\n");
351 /* Get available message count in RX FIFO */
352 dcnt = AW_IR_RXSTA_COUNTER(val);
354 for (i = 0; i < dcnt; i++) {
355 if (aw_ir_buf_full(sc)) {
357 device_printf(sc->dev,
358 "raw buffer full\n");
361 aw_ir_buf_write(sc, aw_ir_read_data(sc));
365 if (val & AW_IR_RXINT_RPEI_EN) {
367 if (bootverbose && __predict_false(aw_cir_debug) != 0)
368 device_printf(sc->dev, "RX Packet end\n");
369 ir_code = aw_ir_decode_packets(sc);
370 stat = aw_ir_validate_code(ir_code);
372 evdev_push_event(sc->sc_evdev,
373 EV_MSC, MSC_SCAN, ir_code);
374 evdev_sync(sc->sc_evdev);
376 if (bootverbose && __predict_false(aw_cir_debug) != 0) {
377 device_printf(sc->dev, "Final IR code: %lx\n",
379 device_printf(sc->dev, "IR code status: %d\n",
384 if (val & AW_IR_RXINT_ROI_EN) {
385 /* RX FIFO overflow */
387 device_printf(sc->dev, "RX FIFO overflow\n");
388 /* Flush raw buffer */
394 aw_ir_probe(device_t dev)
397 if (!ofw_bus_status_okay(dev))
400 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
403 device_set_desc(dev, "Allwinner CIR controller");
404 return (BUS_PROBE_DEFAULT);
408 aw_ir_attach(device_t dev)
410 struct aw_ir_softc *sc;
412 clk_t clk_ir, clk_gate;
416 clk_ir = clk_gate = NULL;
419 sc = device_get_softc(dev);
422 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) {
423 device_printf(dev, "could not allocate memory resource\n");
427 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
437 /* De-assert reset */
438 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) {
439 err = hwreset_deassert(rst_apb);
441 device_printf(dev, "cannot de-assert reset\n");
449 /* Get clocks and enable them */
450 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate);
452 device_printf(dev, "Cannot get gate clock\n");
455 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir);
457 device_printf(dev, "Cannot get IR clock\n");
461 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0);
463 device_printf(dev, "cannot set IR clock rate\n");
467 err = clk_enable(clk_gate);
469 device_printf(dev, "Cannot enable clk gate\n");
472 err = clk_enable(clk_ir);
474 device_printf(dev, "Cannot enable IR clock\n");
478 if (bus_setup_intr(dev, sc->res[1],
479 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc,
481 bus_release_resources(dev, aw_ir_spec, sc->res);
482 device_printf(dev, "cannot setup interrupt handler\n");
487 /* Enable CIR Mode */
488 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD);
491 * Set clock sample, filter, idle thresholds.
492 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us)
494 val = AW_IR_SAMPLE_128;
495 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL);
496 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C);
497 WRITE(sc, AW_IR_CIR, val);
499 /* Invert Input Signal */
500 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI);
502 /* Clear All RX Interrupt Status */
503 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL);
506 * Enable RX interrupt in case of overflow, packet end
507 * and FIFO available.
508 * RX FIFO Threshold = FIFO size / 2
510 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN |
511 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1));
513 /* Enable IR Module */
514 val = READ(sc, AW_IR_CTL);
515 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN);
517 sc->sc_evdev = evdev_alloc();
518 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev));
519 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev));
520 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0);
521 evdev_support_event(sc->sc_evdev, EV_SYN);
522 evdev_support_event(sc->sc_evdev, EV_MSC);
523 evdev_support_msc(sc->sc_evdev, MSC_SCAN);
525 err = evdev_register(sc->sc_evdev);
528 "failed to register evdev: error=%d\n", err);
534 if (clk_gate != NULL)
535 clk_release(clk_gate);
539 hwreset_release(rst_apb);
540 evdev_free(sc->sc_evdev);
541 sc->sc_evdev = NULL; /* Avoid double free */
543 bus_release_resources(dev, aw_ir_spec, sc->res);
547 static device_method_t aw_ir_methods[] = {
548 DEVMETHOD(device_probe, aw_ir_probe),
549 DEVMETHOD(device_attach, aw_ir_attach),
554 static driver_t aw_ir_driver = {
557 sizeof(struct aw_ir_softc),
560 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, 0, 0);
561 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1);