2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner GMAC clock
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk_mux.h>
49 #include <dev/extres/clk/clk_gate.h>
51 #include "clkdev_if.h"
53 #define GMAC_CLK_PIT (0x1 << 2)
54 #define GMAC_CLK_PIT_SHIFT 2
55 #define GMAC_CLK_PIT_MII 0
56 #define GMAC_CLK_PIT_RGMII 1
57 #define GMAC_CLK_SRC (0x3 << 0)
58 #define GMAC_CLK_SRC_SHIFT 0
59 #define GMAC_CLK_SRC_MII 0
60 #define GMAC_CLK_SRC_EXT_RGMII 1
61 #define GMAC_CLK_SRC_RGMII 2
63 #define EMAC_TXC_DIV_CFG (1 << 15)
64 #define EMAC_TXC_DIV_CFG_SHIFT 15
65 #define EMAC_TXC_DIV_CFG_125MHZ 0
66 #define EMAC_TXC_DIV_CFG_25MHZ 1
67 #define EMAC_PHY_SELECT (1 << 16)
68 #define EMAC_PHY_SELECT_SHIFT 16
69 #define EMAC_PHY_SELECT_INT 0
70 #define EMAC_PHY_SELECT_EXT 1
71 #define EMAC_ETXDC (0x7 << 10)
72 #define EMAC_ETXDC_SHIFT 10
73 #define EMAC_ERXDC (0x1f << 5)
74 #define EMAC_ERXDC_SHIFT 5
77 #define CLK_IDX_RGMII 1
78 #define CLK_IDX_COUNT 2
80 static struct ofw_compat_data compat_data[] = {
81 { "allwinner,sun7i-a20-gmac-clk", 1 },
85 struct aw_gmacclk_sc {
93 #define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
94 #define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
95 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
96 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
99 aw_gmacclk_init(struct clknode *clk, device_t dev)
101 struct aw_gmacclk_sc *sc;
104 sc = clknode_get_softc(clk);
107 GMACCLK_READ(sc, &val);
110 switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) {
111 case GMAC_CLK_SRC_MII:
114 case GMAC_CLK_SRC_RGMII:
115 index = CLK_IDX_RGMII;
121 clknode_init_parent_idx(clk, index);
126 aw_gmacclk_set_mux(struct clknode *clk, int index)
128 struct aw_gmacclk_sc *sc;
129 uint32_t val, clk_src, pit, txc_div;
132 sc = clknode_get_softc(clk);
137 clk_src = GMAC_CLK_SRC_MII;
138 pit = GMAC_CLK_PIT_MII;
139 txc_div = EMAC_TXC_DIV_CFG_25MHZ;
142 clk_src = GMAC_CLK_SRC_RGMII;
143 pit = GMAC_CLK_PIT_RGMII;
144 txc_div = EMAC_TXC_DIV_CFG_125MHZ;
151 GMACCLK_READ(sc, &val);
152 val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT);
153 val |= (clk_src << GMAC_CLK_SRC_SHIFT);
154 val |= (pit << GMAC_CLK_PIT_SHIFT);
155 GMACCLK_WRITE(sc, val);
161 static clknode_method_t aw_gmacclk_clknode_methods[] = {
162 /* Device interface */
163 CLKNODEMETHOD(clknode_init, aw_gmacclk_init),
164 CLKNODEMETHOD(clknode_set_mux, aw_gmacclk_set_mux),
167 DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class,
168 aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class);
171 aw_gmacclk_probe(device_t dev)
173 if (!ofw_bus_status_okay(dev))
176 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
179 device_set_desc(dev, "Allwinner GMAC Clock");
180 return (BUS_PROBE_DEFAULT);
184 aw_gmacclk_attach(device_t dev)
186 struct clknode_init_def def;
187 struct aw_gmacclk_sc *sc;
188 struct clkdom *clkdom;
194 int error, ncells, i;
196 node = ofw_bus_get_node(dev);
198 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
199 device_printf(dev, "cannot parse 'reg' property\n");
203 error = ofw_bus_parse_xref_list_get_length(node, "clocks",
204 "#clock-cells", &ncells);
205 if (error != 0 || ncells != CLK_IDX_COUNT) {
206 device_printf(dev, "couldn't find parent clocks\n");
210 clkdom = clkdom_create(dev);
212 memset(&def, 0, sizeof(def));
213 error = clk_parse_ofw_clk_name(dev, node, &def.name);
215 device_printf(dev, "cannot parse clock name\n");
220 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
221 for (i = 0; i < ncells; i++) {
222 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
224 device_printf(dev, "cannot get clock %d\n", error);
227 def.parent_names[i] = clk_get_name(clk_parent);
228 clk_release(clk_parent);
230 def.parent_cnt = ncells;
232 clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def);
234 device_printf(dev, "cannot create clknode\n");
239 sc = clknode_get_softc(clk);
241 sc->clkdev = device_get_parent(dev);
242 sc->tx_delay = sc->rx_delay = -1;
243 OF_getencprop(node, "tx-delay", &sc->tx_delay, sizeof(sc->tx_delay));
244 OF_getencprop(node, "rx-delay", &sc->rx_delay, sizeof(sc->rx_delay));
246 clknode_register(clkdom, clk);
248 if (clkdom_finit(clkdom) != 0) {
249 device_printf(dev, "cannot finalize clkdom initialization\n");
263 static device_method_t aw_gmacclk_methods[] = {
264 /* Device interface */
265 DEVMETHOD(device_probe, aw_gmacclk_probe),
266 DEVMETHOD(device_attach, aw_gmacclk_attach),
271 static driver_t aw_gmacclk_driver = {
277 static devclass_t aw_gmacclk_devclass;
279 EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver,
280 aw_gmacclk_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);