2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Allwinner GMAC clock
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <machine/bus.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45 #include <dev/ofw/ofw_subr.h>
47 #include <dev/extres/clk/clk_mux.h>
48 #include <dev/extres/clk/clk_gate.h>
50 #include "clkdev_if.h"
52 #define GMAC_CLK_PIT (0x1 << 2)
53 #define GMAC_CLK_PIT_SHIFT 2
54 #define GMAC_CLK_PIT_MII 0
55 #define GMAC_CLK_PIT_RGMII 1
56 #define GMAC_CLK_SRC (0x3 << 0)
57 #define GMAC_CLK_SRC_SHIFT 0
58 #define GMAC_CLK_SRC_MII 0
59 #define GMAC_CLK_SRC_EXT_RGMII 1
60 #define GMAC_CLK_SRC_RGMII 2
62 #define EMAC_TXC_DIV_CFG (1 << 15)
63 #define EMAC_TXC_DIV_CFG_SHIFT 15
64 #define EMAC_TXC_DIV_CFG_125MHZ 0
65 #define EMAC_TXC_DIV_CFG_25MHZ 1
66 #define EMAC_PHY_SELECT (1 << 16)
67 #define EMAC_PHY_SELECT_SHIFT 16
68 #define EMAC_PHY_SELECT_INT 0
69 #define EMAC_PHY_SELECT_EXT 1
70 #define EMAC_ETXDC (0x7 << 10)
71 #define EMAC_ETXDC_SHIFT 10
72 #define EMAC_ERXDC (0x1f << 5)
73 #define EMAC_ERXDC_SHIFT 5
76 #define CLK_IDX_RGMII 1
77 #define CLK_IDX_COUNT 2
79 static struct ofw_compat_data compat_data[] = {
80 { "allwinner,sun7i-a20-gmac-clk", 1 },
84 struct aw_gmacclk_sc {
92 #define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
93 #define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
94 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
95 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
98 aw_gmacclk_init(struct clknode *clk, device_t dev)
100 struct aw_gmacclk_sc *sc;
103 sc = clknode_get_softc(clk);
106 GMACCLK_READ(sc, &val);
109 switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) {
110 case GMAC_CLK_SRC_MII:
113 case GMAC_CLK_SRC_RGMII:
114 index = CLK_IDX_RGMII;
120 clknode_init_parent_idx(clk, index);
125 aw_gmacclk_set_mux(struct clknode *clk, int index)
127 struct aw_gmacclk_sc *sc;
128 uint32_t val, clk_src, pit;
130 sc = clknode_get_softc(clk);
134 clk_src = GMAC_CLK_SRC_MII;
135 pit = GMAC_CLK_PIT_MII;
138 clk_src = GMAC_CLK_SRC_RGMII;
139 pit = GMAC_CLK_PIT_RGMII;
146 GMACCLK_READ(sc, &val);
147 val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT);
148 val |= (clk_src << GMAC_CLK_SRC_SHIFT);
149 val |= (pit << GMAC_CLK_PIT_SHIFT);
150 GMACCLK_WRITE(sc, val);
156 static clknode_method_t aw_gmacclk_clknode_methods[] = {
157 /* Device interface */
158 CLKNODEMETHOD(clknode_init, aw_gmacclk_init),
159 CLKNODEMETHOD(clknode_set_mux, aw_gmacclk_set_mux),
162 DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class,
163 aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class);
166 aw_gmacclk_probe(device_t dev)
168 if (!ofw_bus_status_okay(dev))
171 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
174 device_set_desc(dev, "Allwinner GMAC Clock");
175 return (BUS_PROBE_DEFAULT);
179 aw_gmacclk_attach(device_t dev)
181 struct clknode_init_def def;
182 struct aw_gmacclk_sc *sc;
183 struct clkdom *clkdom;
189 int error, ncells, i;
191 node = ofw_bus_get_node(dev);
193 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
194 device_printf(dev, "cannot parse 'reg' property\n");
198 error = ofw_bus_parse_xref_list_get_length(node, "clocks",
199 "#clock-cells", &ncells);
200 if (error != 0 || ncells != CLK_IDX_COUNT) {
201 device_printf(dev, "couldn't find parent clocks\n");
205 clkdom = clkdom_create(dev);
207 memset(&def, 0, sizeof(def));
208 error = clk_parse_ofw_clk_name(dev, node, &def.name);
210 device_printf(dev, "cannot parse clock name\n");
215 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
216 for (i = 0; i < ncells; i++) {
217 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
219 device_printf(dev, "cannot get clock %d\n", error);
222 def.parent_names[i] = clk_get_name(clk_parent);
223 clk_release(clk_parent);
225 def.parent_cnt = ncells;
227 clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def);
229 device_printf(dev, "cannot create clknode\n");
234 sc = clknode_get_softc(clk);
236 sc->clkdev = device_get_parent(dev);
237 sc->tx_delay = sc->rx_delay = -1;
238 OF_getencprop(node, "tx-delay", &sc->tx_delay, sizeof(sc->tx_delay));
239 OF_getencprop(node, "rx-delay", &sc->rx_delay, sizeof(sc->rx_delay));
241 clknode_register(clkdom, clk);
243 if (clkdom_finit(clkdom) != 0) {
244 device_printf(dev, "cannot finalize clkdom initialization\n");
258 static device_method_t aw_gmacclk_methods[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe, aw_gmacclk_probe),
261 DEVMETHOD(device_attach, aw_gmacclk_attach),
266 static driver_t aw_gmacclk_driver = {
272 EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver, 0, 0,
273 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);