2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6 * Copyright (c) 2012 Luiz Otavio O Souza.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
42 #include <sys/mutex.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/fdt/fdt_pinctrl.h>
54 #include <arm/allwinner/aw_machdep.h>
55 #include <arm/allwinner/allwinner_pinctrl.h>
56 #include <dev/extres/clk/clk.h>
57 #include <dev/extres/hwreset/hwreset.h>
59 #if defined(__aarch64__)
65 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
66 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
68 #define AW_GPIO_NONE 0
69 #define AW_GPIO_PULLUP 1
70 #define AW_GPIO_PULLDOWN 2
72 #define AW_GPIO_INPUT 0
73 #define AW_GPIO_OUTPUT 1
75 #define AW_GPIO_DRV_MASK 0x3
76 #define AW_GPIO_PUD_MASK 0x3
79 #define AW_R_PINCTRL 2
81 /* Defined in aw_padconf.c */
82 #ifdef SOC_ALLWINNER_A10
83 extern const struct allwinner_padconf a10_padconf;
86 /* Defined in a13_padconf.c */
87 #ifdef SOC_ALLWINNER_A13
88 extern const struct allwinner_padconf a13_padconf;
91 /* Defined in a20_padconf.c */
92 #ifdef SOC_ALLWINNER_A20
93 extern const struct allwinner_padconf a20_padconf;
96 /* Defined in a31_padconf.c */
97 #ifdef SOC_ALLWINNER_A31
98 extern const struct allwinner_padconf a31_padconf;
101 /* Defined in a31s_padconf.c */
102 #ifdef SOC_ALLWINNER_A31S
103 extern const struct allwinner_padconf a31s_padconf;
106 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
107 extern const struct allwinner_padconf a31_r_padconf;
110 /* Defined in a33_padconf.c */
111 #ifdef SOC_ALLWINNER_A33
112 extern const struct allwinner_padconf a33_padconf;
115 /* Defined in h3_padconf.c */
116 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
117 extern const struct allwinner_padconf h3_padconf;
118 extern const struct allwinner_padconf h3_r_padconf;
121 /* Defined in a83t_padconf.c */
122 #ifdef SOC_ALLWINNER_A83T
123 extern const struct allwinner_padconf a83t_padconf;
124 extern const struct allwinner_padconf a83t_r_padconf;
127 /* Defined in a64_padconf.c */
128 #ifdef SOC_ALLWINNER_A64
129 extern const struct allwinner_padconf a64_padconf;
130 extern const struct allwinner_padconf a64_r_padconf;
133 static struct ofw_compat_data compat_data[] = {
134 #ifdef SOC_ALLWINNER_A10
135 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf},
137 #ifdef SOC_ALLWINNER_A13
138 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_padconf},
140 #ifdef SOC_ALLWINNER_A20
141 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_padconf},
143 #ifdef SOC_ALLWINNER_A31
144 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_padconf},
146 #ifdef SOC_ALLWINNER_A31S
147 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_padconf},
149 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
150 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_padconf},
152 #ifdef SOC_ALLWINNER_A33
153 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_padconf},
155 #ifdef SOC_ALLWINNER_A83T
156 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_padconf},
157 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_padconf},
159 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
160 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf},
161 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_padconf},
162 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf},
164 #ifdef SOC_ALLWINNER_A64
165 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_padconf},
166 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_padconf},
172 TAILQ_ENTRY(clk_list) next;
176 struct aw_gpio_softc {
180 struct resource * sc_mem_res;
181 struct resource * sc_irq_res;
182 bus_space_tag_t sc_bst;
183 bus_space_handle_t sc_bsh;
185 const struct allwinner_padconf * padconf;
186 TAILQ_HEAD(, clk_list) clk_list;
189 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
190 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
191 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
193 #define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
194 #define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
195 #define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
196 #define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
198 #define AW_GPIO_GP_INT_CFG0 0x200
199 #define AW_GPIO_GP_INT_CFG1 0x204
200 #define AW_GPIO_GP_INT_CFG2 0x208
201 #define AW_GPIO_GP_INT_CFG3 0x20c
203 #define AW_GPIO_GP_INT_CTL 0x210
204 #define AW_GPIO_GP_INT_STA 0x214
205 #define AW_GPIO_GP_INT_DEB 0x218
207 static char *aw_gpio_parse_function(phandle_t node);
208 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb);
209 static uint32_t aw_gpio_parse_bias(phandle_t node);
210 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
212 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
213 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
214 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value);
215 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value);
217 #define AW_GPIO_WRITE(_sc, _off, _val) \
218 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
219 #define AW_GPIO_READ(_sc, _off) \
220 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
223 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin)
225 uint32_t bank, func, offset;
227 /* Must be called with lock held. */
228 AW_GPIO_LOCK_ASSERT(sc);
230 if (pin > sc->padconf->npins)
232 bank = sc->padconf->pins[pin].port;
233 pin = sc->padconf->pins[pin].pin;
234 offset = ((pin & 0x07) << 2);
236 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
238 return ((func >> offset) & 0x7);
242 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f)
244 uint32_t bank, data, offset;
246 /* Check if the function exists in the padconf data */
247 if (sc->padconf->pins[pin].functions[f] == NULL)
250 /* Must be called with lock held. */
251 AW_GPIO_LOCK_ASSERT(sc);
253 bank = sc->padconf->pins[pin].port;
254 pin = sc->padconf->pins[pin].pin;
255 offset = ((pin & 0x07) << 2);
257 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
258 data &= ~(7 << offset);
259 data |= (f << offset);
260 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data);
266 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin)
268 uint32_t bank, offset, val;
270 /* Must be called with lock held. */
271 AW_GPIO_LOCK_ASSERT(sc);
273 bank = sc->padconf->pins[pin].port;
274 pin = sc->padconf->pins[pin].pin;
275 offset = ((pin & 0x0f) << 1);
277 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
279 return ((val >> offset) & AW_GPIO_PUD_MASK);
283 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state)
285 uint32_t bank, offset, val;
287 if (aw_gpio_get_pud(sc, pin) == state)
290 /* Must be called with lock held. */
291 AW_GPIO_LOCK_ASSERT(sc);
293 bank = sc->padconf->pins[pin].port;
294 pin = sc->padconf->pins[pin].pin;
295 offset = ((pin & 0x0f) << 1);
297 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
298 val &= ~(AW_GPIO_PUD_MASK << offset);
299 val |= (state << offset);
300 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val);
304 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin)
306 uint32_t bank, offset, val;
308 /* Must be called with lock held. */
309 AW_GPIO_LOCK_ASSERT(sc);
311 bank = sc->padconf->pins[pin].port;
312 pin = sc->padconf->pins[pin].pin;
313 offset = ((pin & 0x0f) << 1);
315 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
317 return ((val >> offset) & AW_GPIO_DRV_MASK);
321 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive)
323 uint32_t bank, offset, val;
325 if (aw_gpio_get_drv(sc, pin) == drive)
328 /* Must be called with lock held. */
329 AW_GPIO_LOCK_ASSERT(sc);
331 bank = sc->padconf->pins[pin].port;
332 pin = sc->padconf->pins[pin].pin;
333 offset = ((pin & 0x0f) << 1);
335 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
336 val &= ~(AW_GPIO_DRV_MASK << offset);
337 val |= (drive << offset);
338 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val);
342 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags)
347 /* Must be called with lock held. */
348 AW_GPIO_LOCK_ASSERT(sc);
350 if (pin > sc->padconf->npins)
353 /* Manage input/output. */
354 if (flags & GPIO_PIN_INPUT) {
355 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
356 } else if ((flags & GPIO_PIN_OUTPUT) &&
357 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) {
358 if (flags & GPIO_PIN_PRESET_LOW) {
359 aw_gpio_pin_set_locked(sc, pin, 0);
360 } else if (flags & GPIO_PIN_PRESET_HIGH) {
361 aw_gpio_pin_set_locked(sc, pin, 1);
363 /* Read the pin and preset output to current state. */
364 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
366 aw_gpio_pin_get_locked(sc, pin, &val);
367 aw_gpio_pin_set_locked(sc, pin, val);
371 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT);
377 /* Manage Pull-up/pull-down. */
378 if (flags & GPIO_PIN_PULLUP)
379 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP);
380 else if (flags & GPIO_PIN_PULLDOWN)
381 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN);
383 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE);
389 aw_gpio_get_bus(device_t dev)
391 struct aw_gpio_softc *sc;
393 sc = device_get_softc(dev);
395 return (sc->sc_busdev);
399 aw_gpio_pin_max(device_t dev, int *maxpin)
401 struct aw_gpio_softc *sc;
403 sc = device_get_softc(dev);
405 *maxpin = sc->padconf->npins - 1;
410 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
412 struct aw_gpio_softc *sc;
414 sc = device_get_softc(dev);
415 if (pin >= sc->padconf->npins)
418 *caps = AW_GPIO_DEFAULT_CAPS;
424 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
426 struct aw_gpio_softc *sc;
430 sc = device_get_softc(dev);
431 if (pin >= sc->padconf->npins)
435 func = aw_gpio_get_function(sc, pin);
438 *flags = GPIO_PIN_INPUT;
441 *flags = GPIO_PIN_OUTPUT;
448 pud = aw_gpio_get_pud(sc, pin);
450 case AW_GPIO_PULLDOWN:
451 *flags |= GPIO_PIN_PULLDOWN;
454 *flags |= GPIO_PIN_PULLUP;
466 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
468 struct aw_gpio_softc *sc;
470 sc = device_get_softc(dev);
471 if (pin >= sc->padconf->npins)
474 snprintf(name, GPIOMAXNAME - 1, "%s",
475 sc->padconf->pins[pin].name);
476 name[GPIOMAXNAME - 1] = '\0';
482 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
484 struct aw_gpio_softc *sc;
487 sc = device_get_softc(dev);
488 if (pin > sc->padconf->npins)
492 err = aw_gpio_pin_configure(sc, pin, flags);
499 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin,
504 AW_GPIO_LOCK_ASSERT(sc);
506 if (pin > sc->padconf->npins)
509 bank = sc->padconf->pins[pin].port;
510 pin = sc->padconf->pins[pin].pin;
512 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
517 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
523 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
525 struct aw_gpio_softc *sc;
528 sc = device_get_softc(dev);
531 ret = aw_gpio_pin_set_locked(sc, pin, value);
538 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin,
541 uint32_t bank, reg_data;
543 AW_GPIO_LOCK_ASSERT(sc);
545 if (pin > sc->padconf->npins)
548 bank = sc->padconf->pins[pin].port;
549 pin = sc->padconf->pins[pin].pin;
551 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
552 *val = (reg_data & (1 << pin)) ? 1 : 0;
558 aw_gpio_parse_function(phandle_t node)
562 if (OF_getprop_alloc(node, "function",
563 (void **)&function) != -1)
565 if (OF_getprop_alloc(node, "allwinner,function",
566 (void **)&function) != -1)
573 aw_gpio_parse_pins(phandle_t node, int *pins_nb)
575 const char **pinlist;
577 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist);
581 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins",
590 aw_gpio_parse_bias(phandle_t node)
594 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1)
596 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1)
598 if (OF_hasprop(node, "bias-disable"))
599 return (AW_GPIO_NONE);
600 if (OF_hasprop(node, "bias-pull-up"))
601 return (AW_GPIO_PULLUP);
602 if (OF_hasprop(node, "bias-pull-down"))
603 return (AW_GPIO_PULLDOWN);
605 return (AW_GPIO_NONE);
609 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
613 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1)
615 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1)
617 if (OF_getencprop(node, "drive-strength", &drive_str,
618 sizeof(drive_str)) != -1) {
619 *drive = (drive_str / 10) - 1;
627 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
629 struct aw_gpio_softc *sc;
632 sc = device_get_softc(dev);
635 ret = aw_gpio_pin_get_locked(sc, pin, val);
642 aw_gpio_pin_toggle(device_t dev, uint32_t pin)
644 struct aw_gpio_softc *sc;
647 sc = device_get_softc(dev);
648 if (pin > sc->padconf->npins)
651 bank = sc->padconf->pins[pin].port;
652 pin = sc->padconf->pins[pin].pin;
655 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
656 if (data & (1 << pin))
660 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
667 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
668 uint32_t change_pins, uint32_t *orig_pins)
670 struct aw_gpio_softc *sc;
671 uint32_t bank, data, pin;
673 sc = device_get_softc(dev);
674 if (first_pin > sc->padconf->npins)
678 * We require that first_pin refers to the first pin in a bank, because
679 * this API is not about convenience, it's for making a set of pins
680 * change simultaneously (required) with reasonably high performance
681 * (desired); we need to do a read-modify-write on a single register.
683 bank = sc->padconf->pins[first_pin].port;
684 pin = sc->padconf->pins[first_pin].pin;
689 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
690 if ((clear_pins | change_pins) != 0)
691 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank),
692 (data & ~clear_pins) ^ change_pins);
695 if (orig_pins != NULL)
702 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
705 struct aw_gpio_softc *sc;
709 sc = device_get_softc(dev);
710 if (first_pin > sc->padconf->npins)
713 bank = sc->padconf->pins[first_pin].port;
714 if (sc->padconf->pins[first_pin].pin != 0)
718 * The configuration for a bank of pins is scattered among several
719 * registers; we cannot g'tee to simultaneously change the state of all
720 * the pins in the flags array. So just loop through the array
721 * configuring each pin for now. If there was a strong need, it might
722 * be possible to support some limited simultaneous config, such as
723 * adjacent groups of 8 pins that line up the same as the config regs.
725 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
726 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
727 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]);
734 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname)
738 for (i = 0; i < sc->padconf->npins; i++)
739 if (!strcmp(pinname, sc->padconf->pins[i].name))
746 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func)
750 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
751 if (sc->padconf->pins[pin].functions[i] &&
752 !strcmp(func, sc->padconf->pins[pin].functions[i]))
759 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
761 struct aw_gpio_softc *sc;
763 const char **pinlist = NULL;
764 char *pin_function = NULL;
765 uint32_t pin_drive, pin_pull;
766 int pins_nb, pin_num, pin_func, i, ret;
769 sc = device_get_softc(dev);
770 node = OF_node_from_xref(cfgxref);
774 /* Getting all prop for configuring pins */
775 pinlist = aw_gpio_parse_pins(node, &pins_nb);
779 pin_function = aw_gpio_parse_function(node);
780 if (pin_function == NULL) {
785 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0)
788 pin_pull = aw_gpio_parse_bias(node);
790 /* Configure each pin to the correct function, drive and pull */
791 for (i = 0; i < pins_nb; i++) {
792 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
797 pin_func = aw_find_pin_func(sc, pin_num, pin_function);
798 if (pin_func == -1) {
805 if (aw_gpio_get_function(sc, pin_num) != pin_func)
806 aw_gpio_set_function(sc, pin_num, pin_func);
808 aw_gpio_set_drv(sc, pin_num, pin_drive);
809 if (pin_pull != AW_GPIO_NONE)
810 aw_gpio_set_pud(sc, pin_num, pin_pull);
816 OF_prop_free(pinlist);
817 OF_prop_free(pin_function);
822 aw_gpio_probe(device_t dev)
825 if (!ofw_bus_status_okay(dev))
828 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
831 device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
832 return (BUS_PROBE_DEFAULT);
836 aw_gpio_attach(device_t dev)
840 struct aw_gpio_softc *sc;
841 struct clk_list *clkp, *clkp_tmp;
843 hwreset_t rst = NULL;
844 int off, err, clkret;
846 sc = device_get_softc(dev);
849 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN);
852 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
854 if (!sc->sc_mem_res) {
855 device_printf(dev, "cannot allocate memory window\n");
859 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
860 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
863 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
865 if (!sc->sc_irq_res) {
866 device_printf(dev, "cannot allocate interrupt\n");
871 gpio = ofw_bus_get_node(sc->sc_dev);
872 if (!OF_hasprop(gpio, "gpio-controller"))
873 /* Node is not a GPIO controller. */
876 /* Use the right pin data for the current SoC */
877 sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev,
878 compat_data)->ocd_data;
880 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
881 error = hwreset_deassert(rst);
883 device_printf(dev, "cannot de-assert reset\n");
888 TAILQ_INIT(&sc->clk_list);
889 for (off = 0, clkret = 0; clkret == 0; off++) {
890 clkret = clk_get_by_ofw_index(dev, 0, off, &clk);
893 err = clk_enable(clk);
895 device_printf(dev, "Could not enable clock %s\n",
899 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
901 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
903 if (clkret != 0 && clkret != ENOENT) {
904 device_printf(dev, "Could not find clock at offset %d (%d)\n",
909 sc->sc_busdev = gpiobus_attach_bus(dev);
910 if (sc->sc_busdev == NULL)
914 * Register as a pinctrl device
916 fdt_pinctrl_register(dev, "pins");
917 fdt_pinctrl_configure_tree(dev);
918 fdt_pinctrl_register(dev, "allwinner,pins");
919 fdt_pinctrl_configure_tree(dev);
925 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
927 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
928 mtx_destroy(&sc->sc_mtx);
931 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
932 err = clk_disable(clkp->clk);
934 device_printf(dev, "Could not disable clock %s\n",
935 clk_get_name(clkp->clk));
936 err = clk_release(clkp->clk);
938 device_printf(dev, "Could not release clock %s\n",
939 clk_get_name(clkp->clk));
940 TAILQ_REMOVE(&sc->clk_list, clkp, next);
941 free(clkp, M_DEVBUF);
947 hwreset_release(rst);
954 aw_gpio_detach(device_t dev)
961 aw_gpio_get_node(device_t dev, device_t bus)
964 /* We only have one child, the GPIO bus, which needs our own node. */
965 return (ofw_bus_get_node(dev));
969 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
970 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
972 struct aw_gpio_softc *sc;
975 sc = device_get_softc(bus);
977 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
978 for (i = 0; i < sc->padconf->npins; i++)
979 if (sc->padconf->pins[i].port == gpios[0] &&
980 sc->padconf->pins[i].pin == gpios[1]) {
984 *flags = gpios[gcells - 1];
989 static device_method_t aw_gpio_methods[] = {
990 /* Device interface */
991 DEVMETHOD(device_probe, aw_gpio_probe),
992 DEVMETHOD(device_attach, aw_gpio_attach),
993 DEVMETHOD(device_detach, aw_gpio_detach),
996 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus),
997 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max),
998 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname),
999 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags),
1000 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps),
1001 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags),
1002 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get),
1003 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set),
1004 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle),
1005 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32),
1006 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32),
1007 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios),
1009 /* ofw_bus interface */
1010 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node),
1012 /* fdt_pinctrl interface */
1013 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
1018 static devclass_t aw_gpio_devclass;
1020 static driver_t aw_gpio_driver = {
1023 sizeof(struct aw_gpio_softc),
1026 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, aw_gpio_devclass, 0, 0,
1027 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);