2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6 * Copyright (c) 2012 Luiz Otavio O Souza.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
42 #include <sys/mutex.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/fdt/fdt_pinctrl.h>
54 #include <arm/allwinner/aw_machdep.h>
55 #include <arm/allwinner/allwinner_pinctrl.h>
56 #include <dev/extres/clk/clk.h>
57 #include <dev/extres/hwreset/hwreset.h>
58 #include <dev/extres/regulator/regulator.h>
60 #if defined(__aarch64__)
66 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
67 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
69 #define AW_GPIO_NONE 0
70 #define AW_GPIO_PULLUP 1
71 #define AW_GPIO_PULLDOWN 2
73 #define AW_GPIO_INPUT 0
74 #define AW_GPIO_OUTPUT 1
76 #define AW_GPIO_DRV_MASK 0x3
77 #define AW_GPIO_PUD_MASK 0x3
80 #define AW_R_PINCTRL 2
83 struct allwinner_padconf *padconf;
87 /* Defined in aw_padconf.c */
88 #ifdef SOC_ALLWINNER_A10
89 extern struct allwinner_padconf a10_padconf;
90 struct aw_gpio_conf a10_gpio_conf = {
91 .padconf = &a10_padconf,
96 /* Defined in a13_padconf.c */
97 #ifdef SOC_ALLWINNER_A13
98 extern struct allwinner_padconf a13_padconf;
99 struct aw_gpio_conf a13_gpio_conf = {
100 .padconf = &a13_padconf,
105 /* Defined in a20_padconf.c */
106 #ifdef SOC_ALLWINNER_A20
107 extern struct allwinner_padconf a20_padconf;
108 struct aw_gpio_conf a20_gpio_conf = {
109 .padconf = &a20_padconf,
110 .banks = "abcdefghi",
114 /* Defined in a31_padconf.c */
115 #ifdef SOC_ALLWINNER_A31
116 extern struct allwinner_padconf a31_padconf;
117 struct aw_gpio_conf a31_gpio_conf = {
118 .padconf = &a31_padconf,
123 /* Defined in a31s_padconf.c */
124 #ifdef SOC_ALLWINNER_A31S
125 extern struct allwinner_padconf a31s_padconf;
126 struct aw_gpio_conf a31s_gpio_conf = {
127 .padconf = &a31s_padconf,
132 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
133 extern struct allwinner_padconf a31_r_padconf;
134 struct aw_gpio_conf a31_r_gpio_conf = {
135 .padconf = &a31_r_padconf,
140 /* Defined in a33_padconf.c */
141 #ifdef SOC_ALLWINNER_A33
142 extern struct allwinner_padconf a33_padconf;
143 struct aw_gpio_conf a33_gpio_conf = {
144 .padconf = &a33_padconf,
149 /* Defined in h3_padconf.c */
150 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
151 extern struct allwinner_padconf h3_padconf;
152 extern struct allwinner_padconf h3_r_padconf;
153 struct aw_gpio_conf h3_gpio_conf = {
154 .padconf = &h3_padconf,
157 struct aw_gpio_conf h3_r_gpio_conf = {
158 .padconf = &h3_r_padconf,
163 /* Defined in a83t_padconf.c */
164 #ifdef SOC_ALLWINNER_A83T
165 extern struct allwinner_padconf a83t_padconf;
166 extern struct allwinner_padconf a83t_r_padconf;
167 struct aw_gpio_conf a83t_gpio_conf = {
168 .padconf = &a83t_padconf,
171 struct aw_gpio_conf a83t_r_gpio_conf = {
172 .padconf = &a83t_r_padconf,
177 /* Defined in a64_padconf.c */
178 #ifdef SOC_ALLWINNER_A64
179 extern struct allwinner_padconf a64_padconf;
180 extern struct allwinner_padconf a64_r_padconf;
181 struct aw_gpio_conf a64_gpio_conf = {
182 .padconf = &a64_padconf,
185 struct aw_gpio_conf a64_r_gpio_conf = {
186 .padconf = &a64_r_padconf,
191 /* Defined in h6_padconf.c */
192 #ifdef SOC_ALLWINNER_H6
193 extern struct allwinner_padconf h6_padconf;
194 extern struct allwinner_padconf h6_r_padconf;
195 struct aw_gpio_conf h6_gpio_conf = {
196 .padconf = &h6_padconf,
199 struct aw_gpio_conf h6_r_gpio_conf = {
200 .padconf = &h6_r_padconf,
205 static struct ofw_compat_data compat_data[] = {
206 #ifdef SOC_ALLWINNER_A10
207 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
209 #ifdef SOC_ALLWINNER_A13
210 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
212 #ifdef SOC_ALLWINNER_A20
213 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
215 #ifdef SOC_ALLWINNER_A31
216 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
218 #ifdef SOC_ALLWINNER_A31S
219 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
221 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
222 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
224 #ifdef SOC_ALLWINNER_A33
225 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
227 #ifdef SOC_ALLWINNER_A83T
228 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf},
229 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_gpio_conf},
231 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
232 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_gpio_conf},
233 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_gpio_conf},
234 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_gpio_conf},
236 #ifdef SOC_ALLWINNER_A64
237 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_gpio_conf},
238 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_gpio_conf},
240 #ifdef SOC_ALLWINNER_H6
241 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_gpio_conf},
242 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_gpio_conf},
248 TAILQ_ENTRY(clk_list) next;
252 struct aw_gpio_softc {
256 struct resource * sc_mem_res;
257 struct resource * sc_irq_res;
258 bus_space_tag_t sc_bst;
259 bus_space_handle_t sc_bsh;
261 struct aw_gpio_conf *conf;
262 TAILQ_HEAD(, clk_list) clk_list;
265 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
266 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
267 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
269 #define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
270 #define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
271 #define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
272 #define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
274 #define AW_GPIO_GP_INT_CFG0 0x200
275 #define AW_GPIO_GP_INT_CFG1 0x204
276 #define AW_GPIO_GP_INT_CFG2 0x208
277 #define AW_GPIO_GP_INT_CFG3 0x20c
279 #define AW_GPIO_GP_INT_CTL 0x210
280 #define AW_GPIO_GP_INT_STA 0x214
281 #define AW_GPIO_GP_INT_DEB 0x218
283 static char *aw_gpio_parse_function(phandle_t node);
284 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb);
285 static uint32_t aw_gpio_parse_bias(phandle_t node);
286 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
288 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
289 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
290 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value);
291 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value);
293 #define AW_GPIO_WRITE(_sc, _off, _val) \
294 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
295 #define AW_GPIO_READ(_sc, _off) \
296 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
299 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin)
301 uint32_t bank, func, offset;
303 /* Must be called with lock held. */
304 AW_GPIO_LOCK_ASSERT(sc);
306 if (pin > sc->conf->padconf->npins)
308 bank = sc->conf->padconf->pins[pin].port;
309 pin = sc->conf->padconf->pins[pin].pin;
310 offset = ((pin & 0x07) << 2);
312 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
314 return ((func >> offset) & 0x7);
318 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f)
320 uint32_t bank, data, offset;
322 /* Check if the function exists in the padconf data */
323 if (sc->conf->padconf->pins[pin].functions[f] == NULL)
326 /* Must be called with lock held. */
327 AW_GPIO_LOCK_ASSERT(sc);
329 bank = sc->conf->padconf->pins[pin].port;
330 pin = sc->conf->padconf->pins[pin].pin;
331 offset = ((pin & 0x07) << 2);
333 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
334 data &= ~(7 << offset);
335 data |= (f << offset);
336 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data);
342 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin)
344 uint32_t bank, offset, val;
346 /* Must be called with lock held. */
347 AW_GPIO_LOCK_ASSERT(sc);
349 bank = sc->conf->padconf->pins[pin].port;
350 pin = sc->conf->padconf->pins[pin].pin;
351 offset = ((pin & 0x0f) << 1);
353 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
355 return ((val >> offset) & AW_GPIO_PUD_MASK);
359 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state)
361 uint32_t bank, offset, val;
363 if (aw_gpio_get_pud(sc, pin) == state)
366 /* Must be called with lock held. */
367 AW_GPIO_LOCK_ASSERT(sc);
369 bank = sc->conf->padconf->pins[pin].port;
370 pin = sc->conf->padconf->pins[pin].pin;
371 offset = ((pin & 0x0f) << 1);
373 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
374 val &= ~(AW_GPIO_PUD_MASK << offset);
375 val |= (state << offset);
376 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val);
380 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin)
382 uint32_t bank, offset, val;
384 /* Must be called with lock held. */
385 AW_GPIO_LOCK_ASSERT(sc);
387 bank = sc->conf->padconf->pins[pin].port;
388 pin = sc->conf->padconf->pins[pin].pin;
389 offset = ((pin & 0x0f) << 1);
391 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
393 return ((val >> offset) & AW_GPIO_DRV_MASK);
397 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive)
399 uint32_t bank, offset, val;
401 if (aw_gpio_get_drv(sc, pin) == drive)
404 /* Must be called with lock held. */
405 AW_GPIO_LOCK_ASSERT(sc);
407 bank = sc->conf->padconf->pins[pin].port;
408 pin = sc->conf->padconf->pins[pin].pin;
409 offset = ((pin & 0x0f) << 1);
411 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
412 val &= ~(AW_GPIO_DRV_MASK << offset);
413 val |= (drive << offset);
414 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val);
418 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags)
423 /* Must be called with lock held. */
424 AW_GPIO_LOCK_ASSERT(sc);
426 if (pin > sc->conf->padconf->npins)
429 /* Manage input/output. */
430 if (flags & GPIO_PIN_INPUT) {
431 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
432 } else if ((flags & GPIO_PIN_OUTPUT) &&
433 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) {
434 if (flags & GPIO_PIN_PRESET_LOW) {
435 aw_gpio_pin_set_locked(sc, pin, 0);
436 } else if (flags & GPIO_PIN_PRESET_HIGH) {
437 aw_gpio_pin_set_locked(sc, pin, 1);
439 /* Read the pin and preset output to current state. */
440 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
442 aw_gpio_pin_get_locked(sc, pin, &val);
443 aw_gpio_pin_set_locked(sc, pin, val);
447 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT);
453 /* Manage Pull-up/pull-down. */
454 if (flags & GPIO_PIN_PULLUP)
455 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP);
456 else if (flags & GPIO_PIN_PULLDOWN)
457 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN);
459 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE);
465 aw_gpio_get_bus(device_t dev)
467 struct aw_gpio_softc *sc;
469 sc = device_get_softc(dev);
471 return (sc->sc_busdev);
475 aw_gpio_pin_max(device_t dev, int *maxpin)
477 struct aw_gpio_softc *sc;
479 sc = device_get_softc(dev);
481 *maxpin = sc->conf->padconf->npins - 1;
486 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
488 struct aw_gpio_softc *sc;
490 sc = device_get_softc(dev);
491 if (pin >= sc->conf->padconf->npins)
494 *caps = AW_GPIO_DEFAULT_CAPS;
500 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
502 struct aw_gpio_softc *sc;
506 sc = device_get_softc(dev);
507 if (pin >= sc->conf->padconf->npins)
511 func = aw_gpio_get_function(sc, pin);
514 *flags = GPIO_PIN_INPUT;
517 *flags = GPIO_PIN_OUTPUT;
524 pud = aw_gpio_get_pud(sc, pin);
526 case AW_GPIO_PULLDOWN:
527 *flags |= GPIO_PIN_PULLDOWN;
530 *flags |= GPIO_PIN_PULLUP;
542 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
544 struct aw_gpio_softc *sc;
546 sc = device_get_softc(dev);
547 if (pin >= sc->conf->padconf->npins)
550 snprintf(name, GPIOMAXNAME - 1, "%s",
551 sc->conf->padconf->pins[pin].name);
552 name[GPIOMAXNAME - 1] = '\0';
558 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
560 struct aw_gpio_softc *sc;
563 sc = device_get_softc(dev);
564 if (pin > sc->conf->padconf->npins)
568 err = aw_gpio_pin_configure(sc, pin, flags);
575 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin,
580 AW_GPIO_LOCK_ASSERT(sc);
582 if (pin > sc->conf->padconf->npins)
585 bank = sc->conf->padconf->pins[pin].port;
586 pin = sc->conf->padconf->pins[pin].pin;
588 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
593 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
599 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
601 struct aw_gpio_softc *sc;
604 sc = device_get_softc(dev);
607 ret = aw_gpio_pin_set_locked(sc, pin, value);
614 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin,
617 uint32_t bank, reg_data;
619 AW_GPIO_LOCK_ASSERT(sc);
621 if (pin > sc->conf->padconf->npins)
624 bank = sc->conf->padconf->pins[pin].port;
625 pin = sc->conf->padconf->pins[pin].pin;
627 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
628 *val = (reg_data & (1 << pin)) ? 1 : 0;
634 aw_gpio_parse_function(phandle_t node)
638 if (OF_getprop_alloc(node, "function",
639 (void **)&function) != -1)
641 if (OF_getprop_alloc(node, "allwinner,function",
642 (void **)&function) != -1)
649 aw_gpio_parse_pins(phandle_t node, int *pins_nb)
651 const char **pinlist;
653 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist);
657 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins",
666 aw_gpio_parse_bias(phandle_t node)
670 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1)
672 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1)
674 if (OF_hasprop(node, "bias-disable"))
675 return (AW_GPIO_NONE);
676 if (OF_hasprop(node, "bias-pull-up"))
677 return (AW_GPIO_PULLUP);
678 if (OF_hasprop(node, "bias-pull-down"))
679 return (AW_GPIO_PULLDOWN);
681 return (AW_GPIO_NONE);
685 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
689 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1)
691 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1)
693 if (OF_getencprop(node, "drive-strength", &drive_str,
694 sizeof(drive_str)) != -1) {
695 *drive = (drive_str / 10) - 1;
703 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
705 struct aw_gpio_softc *sc;
708 sc = device_get_softc(dev);
711 ret = aw_gpio_pin_get_locked(sc, pin, val);
718 aw_gpio_pin_toggle(device_t dev, uint32_t pin)
720 struct aw_gpio_softc *sc;
723 sc = device_get_softc(dev);
724 if (pin > sc->conf->padconf->npins)
727 bank = sc->conf->padconf->pins[pin].port;
728 pin = sc->conf->padconf->pins[pin].pin;
731 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
732 if (data & (1 << pin))
736 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
743 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
744 uint32_t change_pins, uint32_t *orig_pins)
746 struct aw_gpio_softc *sc;
747 uint32_t bank, data, pin;
749 sc = device_get_softc(dev);
750 if (first_pin > sc->conf->padconf->npins)
754 * We require that first_pin refers to the first pin in a bank, because
755 * this API is not about convenience, it's for making a set of pins
756 * change simultaneously (required) with reasonably high performance
757 * (desired); we need to do a read-modify-write on a single register.
759 bank = sc->conf->padconf->pins[first_pin].port;
760 pin = sc->conf->padconf->pins[first_pin].pin;
765 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
766 if ((clear_pins | change_pins) != 0)
767 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank),
768 (data & ~clear_pins) ^ change_pins);
771 if (orig_pins != NULL)
778 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
781 struct aw_gpio_softc *sc;
785 sc = device_get_softc(dev);
786 if (first_pin > sc->conf->padconf->npins)
789 bank = sc->conf->padconf->pins[first_pin].port;
790 if (sc->conf->padconf->pins[first_pin].pin != 0)
794 * The configuration for a bank of pins is scattered among several
795 * registers; we cannot g'tee to simultaneously change the state of all
796 * the pins in the flags array. So just loop through the array
797 * configuring each pin for now. If there was a strong need, it might
798 * be possible to support some limited simultaneous config, such as
799 * adjacent groups of 8 pins that line up the same as the config regs.
801 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
802 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
803 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]);
810 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname)
814 for (i = 0; i < sc->conf->padconf->npins; i++)
815 if (!strcmp(pinname, sc->conf->padconf->pins[i].name))
822 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func)
826 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
827 if (sc->conf->padconf->pins[pin].functions[i] &&
828 !strcmp(func, sc->conf->padconf->pins[pin].functions[i]))
835 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
837 struct aw_gpio_softc *sc;
839 const char **pinlist = NULL;
840 char *pin_function = NULL;
841 uint32_t pin_drive, pin_pull;
842 int pins_nb, pin_num, pin_func, i, ret;
845 sc = device_get_softc(dev);
846 node = OF_node_from_xref(cfgxref);
850 /* Getting all prop for configuring pins */
851 pinlist = aw_gpio_parse_pins(node, &pins_nb);
855 pin_function = aw_gpio_parse_function(node);
856 if (pin_function == NULL) {
861 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0)
864 pin_pull = aw_gpio_parse_bias(node);
866 /* Configure each pin to the correct function, drive and pull */
867 for (i = 0; i < pins_nb; i++) {
868 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
873 pin_func = aw_find_pin_func(sc, pin_num, pin_function);
874 if (pin_func == -1) {
881 if (aw_gpio_get_function(sc, pin_num) != pin_func)
882 aw_gpio_set_function(sc, pin_num, pin_func);
884 aw_gpio_set_drv(sc, pin_num, pin_drive);
885 if (pin_pull != AW_GPIO_NONE)
886 aw_gpio_set_pud(sc, pin_num, pin_pull);
892 OF_prop_free(pinlist);
893 OF_prop_free(pin_function);
898 aw_gpio_enable_bank_supply(void *arg)
900 struct aw_gpio_softc *sc = arg;
901 regulator_t vcc_supply;
902 char bank_reg_name[16];
905 nbanks = strlen(sc->conf->banks);
906 for (i = 0; i < nbanks; i++) {
907 snprintf(bank_reg_name, sizeof(bank_reg_name), "vcc-p%c-supply",
910 if (regulator_get_by_ofw_property(sc->sc_dev, 0, bank_reg_name, &vcc_supply) == 0) {
912 device_printf(sc->sc_dev,
913 "Enabling regulator for gpio bank %c\n",
915 if (regulator_enable(vcc_supply) != 0) {
916 device_printf(sc->sc_dev,
917 "Cannot enable regulator for bank %c\n",
925 aw_gpio_probe(device_t dev)
928 if (!ofw_bus_status_okay(dev))
931 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
934 device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
935 return (BUS_PROBE_DEFAULT);
939 aw_gpio_attach(device_t dev)
943 struct aw_gpio_softc *sc;
944 struct clk_list *clkp, *clkp_tmp;
946 hwreset_t rst = NULL;
947 int off, err, clkret;
949 sc = device_get_softc(dev);
952 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN);
955 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
957 if (!sc->sc_mem_res) {
958 device_printf(dev, "cannot allocate memory window\n");
962 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
963 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
966 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
968 if (!sc->sc_irq_res) {
969 device_printf(dev, "cannot allocate interrupt\n");
974 gpio = ofw_bus_get_node(sc->sc_dev);
975 if (!OF_hasprop(gpio, "gpio-controller"))
976 /* Node is not a GPIO controller. */
979 /* Use the right pin data for the current SoC */
980 sc->conf = (struct aw_gpio_conf *)ofw_bus_search_compatible(dev,
981 compat_data)->ocd_data;
983 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
984 error = hwreset_deassert(rst);
986 device_printf(dev, "cannot de-assert reset\n");
991 TAILQ_INIT(&sc->clk_list);
992 for (off = 0, clkret = 0; clkret == 0; off++) {
993 clkret = clk_get_by_ofw_index(dev, 0, off, &clk);
996 err = clk_enable(clk);
998 device_printf(dev, "Could not enable clock %s\n",
1002 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
1004 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
1006 if (clkret != 0 && clkret != ENOENT) {
1007 device_printf(dev, "Could not find clock at offset %d (%d)\n",
1012 sc->sc_busdev = gpiobus_attach_bus(dev);
1013 if (sc->sc_busdev == NULL)
1017 * Register as a pinctrl device
1019 fdt_pinctrl_register(dev, "pins");
1020 fdt_pinctrl_configure_tree(dev);
1021 fdt_pinctrl_register(dev, "allwinner,pins");
1022 fdt_pinctrl_configure_tree(dev);
1024 config_intrhook_oneshot(aw_gpio_enable_bank_supply, sc);
1030 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
1032 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
1033 mtx_destroy(&sc->sc_mtx);
1036 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
1037 err = clk_disable(clkp->clk);
1039 device_printf(dev, "Could not disable clock %s\n",
1040 clk_get_name(clkp->clk));
1041 err = clk_release(clkp->clk);
1043 device_printf(dev, "Could not release clock %s\n",
1044 clk_get_name(clkp->clk));
1045 TAILQ_REMOVE(&sc->clk_list, clkp, next);
1046 free(clkp, M_DEVBUF);
1051 hwreset_assert(rst);
1052 hwreset_release(rst);
1059 aw_gpio_detach(device_t dev)
1066 aw_gpio_get_node(device_t dev, device_t bus)
1069 /* We only have one child, the GPIO bus, which needs our own node. */
1070 return (ofw_bus_get_node(dev));
1074 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
1075 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
1077 struct aw_gpio_softc *sc;
1080 sc = device_get_softc(bus);
1082 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
1083 for (i = 0; i < sc->conf->padconf->npins; i++)
1084 if (sc->conf->padconf->pins[i].port == gpios[0] &&
1085 sc->conf->padconf->pins[i].pin == gpios[1]) {
1089 *flags = gpios[gcells - 1];
1094 static device_method_t aw_gpio_methods[] = {
1095 /* Device interface */
1096 DEVMETHOD(device_probe, aw_gpio_probe),
1097 DEVMETHOD(device_attach, aw_gpio_attach),
1098 DEVMETHOD(device_detach, aw_gpio_detach),
1101 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus),
1102 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max),
1103 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname),
1104 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags),
1105 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps),
1106 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags),
1107 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get),
1108 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set),
1109 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle),
1110 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32),
1111 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32),
1112 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios),
1114 /* ofw_bus interface */
1115 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node),
1117 /* fdt_pinctrl interface */
1118 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
1123 static devclass_t aw_gpio_devclass;
1125 static driver_t aw_gpio_driver = {
1128 sizeof(struct aw_gpio_softc),
1131 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, aw_gpio_devclass, 0, 0,
1132 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);