2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6 * Copyright (c) 2012 Luiz Otavio O Souza.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
42 #include <sys/mutex.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/intr.h>
50 #include <dev/gpio/gpiobusvar.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53 #include <dev/fdt/fdt_pinctrl.h>
55 #include <arm/allwinner/aw_machdep.h>
56 #include <arm/allwinner/allwinner_pinctrl.h>
57 #include <dev/extres/clk/clk.h>
58 #include <dev/extres/hwreset/hwreset.h>
59 #include <dev/extres/regulator/regulator.h>
61 #if defined(__aarch64__)
71 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
72 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
74 #define AW_GPIO_INTR_CAPS (GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | \
75 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
77 #define AW_GPIO_NONE 0
78 #define AW_GPIO_PULLUP 1
79 #define AW_GPIO_PULLDOWN 2
81 #define AW_GPIO_INPUT 0
82 #define AW_GPIO_OUTPUT 1
84 #define AW_GPIO_DRV_MASK 0x3
85 #define AW_GPIO_PUD_MASK 0x3
88 #define AW_R_PINCTRL 2
91 struct allwinner_padconf *padconf;
95 /* Defined in aw_padconf.c */
96 #ifdef SOC_ALLWINNER_A10
97 extern struct allwinner_padconf a10_padconf;
98 struct aw_gpio_conf a10_gpio_conf = {
99 .padconf = &a10_padconf,
100 .banks = "abcdefghi",
104 /* Defined in a13_padconf.c */
105 #ifdef SOC_ALLWINNER_A13
106 extern struct allwinner_padconf a13_padconf;
107 struct aw_gpio_conf a13_gpio_conf = {
108 .padconf = &a13_padconf,
113 /* Defined in a20_padconf.c */
114 #ifdef SOC_ALLWINNER_A20
115 extern struct allwinner_padconf a20_padconf;
116 struct aw_gpio_conf a20_gpio_conf = {
117 .padconf = &a20_padconf,
118 .banks = "abcdefghi",
122 /* Defined in a31_padconf.c */
123 #ifdef SOC_ALLWINNER_A31
124 extern struct allwinner_padconf a31_padconf;
125 struct aw_gpio_conf a31_gpio_conf = {
126 .padconf = &a31_padconf,
131 /* Defined in a31s_padconf.c */
132 #ifdef SOC_ALLWINNER_A31S
133 extern struct allwinner_padconf a31s_padconf;
134 struct aw_gpio_conf a31s_gpio_conf = {
135 .padconf = &a31s_padconf,
140 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
141 extern struct allwinner_padconf a31_r_padconf;
142 struct aw_gpio_conf a31_r_gpio_conf = {
143 .padconf = &a31_r_padconf,
148 /* Defined in a33_padconf.c */
149 #ifdef SOC_ALLWINNER_A33
150 extern struct allwinner_padconf a33_padconf;
151 struct aw_gpio_conf a33_gpio_conf = {
152 .padconf = &a33_padconf,
157 /* Defined in h3_padconf.c */
158 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
159 extern struct allwinner_padconf h3_padconf;
160 extern struct allwinner_padconf h3_r_padconf;
161 struct aw_gpio_conf h3_gpio_conf = {
162 .padconf = &h3_padconf,
165 struct aw_gpio_conf h3_r_gpio_conf = {
166 .padconf = &h3_r_padconf,
171 /* Defined in a83t_padconf.c */
172 #ifdef SOC_ALLWINNER_A83T
173 extern struct allwinner_padconf a83t_padconf;
174 extern struct allwinner_padconf a83t_r_padconf;
175 struct aw_gpio_conf a83t_gpio_conf = {
176 .padconf = &a83t_padconf,
179 struct aw_gpio_conf a83t_r_gpio_conf = {
180 .padconf = &a83t_r_padconf,
185 /* Defined in a64_padconf.c */
186 #ifdef SOC_ALLWINNER_A64
187 extern struct allwinner_padconf a64_padconf;
188 extern struct allwinner_padconf a64_r_padconf;
189 struct aw_gpio_conf a64_gpio_conf = {
190 .padconf = &a64_padconf,
193 struct aw_gpio_conf a64_r_gpio_conf = {
194 .padconf = &a64_r_padconf,
199 /* Defined in h6_padconf.c */
200 #ifdef SOC_ALLWINNER_H6
201 extern struct allwinner_padconf h6_padconf;
202 extern struct allwinner_padconf h6_r_padconf;
203 struct aw_gpio_conf h6_gpio_conf = {
204 .padconf = &h6_padconf,
207 struct aw_gpio_conf h6_r_gpio_conf = {
208 .padconf = &h6_r_padconf,
213 static struct ofw_compat_data compat_data[] = {
214 #ifdef SOC_ALLWINNER_A10
215 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
217 #ifdef SOC_ALLWINNER_A13
218 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
220 #ifdef SOC_ALLWINNER_A20
221 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
223 #ifdef SOC_ALLWINNER_A31
224 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
226 #ifdef SOC_ALLWINNER_A31S
227 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
229 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
230 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
232 #ifdef SOC_ALLWINNER_A33
233 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
235 #ifdef SOC_ALLWINNER_A83T
236 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf},
237 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_gpio_conf},
239 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
240 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_gpio_conf},
241 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_gpio_conf},
242 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_gpio_conf},
244 #ifdef SOC_ALLWINNER_A64
245 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_gpio_conf},
246 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_gpio_conf},
248 #ifdef SOC_ALLWINNER_H6
249 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_gpio_conf},
250 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_gpio_conf},
256 TAILQ_ENTRY(clk_list) next;
262 struct intr_irqsrc isrc;
274 #define AW_GPIO_MEMRES 0
275 #define AW_GPIO_IRQRES 1
276 #define AW_GPIO_RESSZ 2
278 struct aw_gpio_softc {
281 struct resource * sc_res[AW_GPIO_RESSZ];
283 struct resource * sc_mem_res;
284 struct resource * sc_irq_res;
286 struct aw_gpio_conf *conf;
287 TAILQ_HEAD(, clk_list) clk_list;
290 struct gpio_irqsrc *gpio_pic_irqsrc;
295 static struct resource_spec aw_gpio_res_spec[] = {
296 { SYS_RES_MEMORY, 0, RF_ACTIVE },
297 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
301 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
302 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
303 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
305 #define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
306 #define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
307 #define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
308 #define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
310 #define AW_GPIO_GP_INT_BASE(_bank) (0x200 + 0x20 * _bank)
312 #define AW_GPIO_GP_INT_CFG(_bank, _pin) (AW_GPIO_GP_INT_BASE(_bank) + (0x4 * ((_pin) / 8)))
313 #define AW_GPIO_GP_INT_CTL(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x10)
314 #define AW_GPIO_GP_INT_STA(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x14)
315 #define AW_GPIO_GP_INT_DEB(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x18)
317 #define AW_GPIO_INT_EDGE_POSITIVE 0x0
318 #define AW_GPIO_INT_EDGE_NEGATIVE 0x1
319 #define AW_GPIO_INT_LEVEL_HIGH 0x2
320 #define AW_GPIO_INT_LEVEL_LOW 0x3
321 #define AW_GPIO_INT_EDGE_BOTH 0x4
323 static char *aw_gpio_parse_function(phandle_t node);
324 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb);
325 static uint32_t aw_gpio_parse_bias(phandle_t node);
326 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
328 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
329 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
330 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value);
331 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value);
333 static void aw_gpio_intr(void *arg);
334 static void aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc);
335 static void aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc);
336 static void aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc);
337 static int aw_gpio_register_isrcs(struct aw_gpio_softc *sc);
339 #define AW_GPIO_WRITE(_sc, _off, _val) \
340 bus_write_4((_sc)->sc_res[AW_GPIO_MEMRES], _off, _val)
341 #define AW_GPIO_READ(_sc, _off) \
342 bus_read_4((_sc)->sc_res[AW_GPIO_MEMRES], _off)
345 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin)
347 uint32_t bank, func, offset;
349 /* Must be called with lock held. */
350 AW_GPIO_LOCK_ASSERT(sc);
352 if (pin > sc->conf->padconf->npins)
354 bank = sc->conf->padconf->pins[pin].port;
355 pin = sc->conf->padconf->pins[pin].pin;
356 offset = ((pin & 0x07) << 2);
358 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
360 return ((func >> offset) & 0x7);
364 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f)
366 uint32_t bank, data, offset;
368 /* Check if the function exists in the padconf data */
369 if (sc->conf->padconf->pins[pin].functions[f] == NULL)
372 /* Must be called with lock held. */
373 AW_GPIO_LOCK_ASSERT(sc);
375 bank = sc->conf->padconf->pins[pin].port;
376 pin = sc->conf->padconf->pins[pin].pin;
377 offset = ((pin & 0x07) << 2);
379 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
380 data &= ~(7 << offset);
381 data |= (f << offset);
382 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data);
388 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin)
390 uint32_t bank, offset, val;
392 /* Must be called with lock held. */
393 AW_GPIO_LOCK_ASSERT(sc);
395 bank = sc->conf->padconf->pins[pin].port;
396 pin = sc->conf->padconf->pins[pin].pin;
397 offset = ((pin & 0x0f) << 1);
399 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
401 return ((val >> offset) & AW_GPIO_PUD_MASK);
405 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state)
407 uint32_t bank, offset, val;
409 if (aw_gpio_get_pud(sc, pin) == state)
412 /* Must be called with lock held. */
413 AW_GPIO_LOCK_ASSERT(sc);
415 bank = sc->conf->padconf->pins[pin].port;
416 pin = sc->conf->padconf->pins[pin].pin;
417 offset = ((pin & 0x0f) << 1);
419 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
420 val &= ~(AW_GPIO_PUD_MASK << offset);
421 val |= (state << offset);
422 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val);
426 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin)
428 uint32_t bank, offset, val;
430 /* Must be called with lock held. */
431 AW_GPIO_LOCK_ASSERT(sc);
433 bank = sc->conf->padconf->pins[pin].port;
434 pin = sc->conf->padconf->pins[pin].pin;
435 offset = ((pin & 0x0f) << 1);
437 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
439 return ((val >> offset) & AW_GPIO_DRV_MASK);
443 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive)
445 uint32_t bank, offset, val;
447 if (aw_gpio_get_drv(sc, pin) == drive)
450 /* Must be called with lock held. */
451 AW_GPIO_LOCK_ASSERT(sc);
453 bank = sc->conf->padconf->pins[pin].port;
454 pin = sc->conf->padconf->pins[pin].pin;
455 offset = ((pin & 0x0f) << 1);
457 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
458 val &= ~(AW_GPIO_DRV_MASK << offset);
459 val |= (drive << offset);
460 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val);
464 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags)
469 /* Must be called with lock held. */
470 AW_GPIO_LOCK_ASSERT(sc);
472 if (pin > sc->conf->padconf->npins)
475 /* Manage input/output. */
476 if (flags & GPIO_PIN_INPUT) {
477 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
478 } else if ((flags & GPIO_PIN_OUTPUT) &&
479 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) {
480 if (flags & GPIO_PIN_PRESET_LOW) {
481 aw_gpio_pin_set_locked(sc, pin, 0);
482 } else if (flags & GPIO_PIN_PRESET_HIGH) {
483 aw_gpio_pin_set_locked(sc, pin, 1);
485 /* Read the pin and preset output to current state. */
486 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
488 aw_gpio_pin_get_locked(sc, pin, &val);
489 aw_gpio_pin_set_locked(sc, pin, val);
493 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT);
499 /* Manage Pull-up/pull-down. */
500 if (flags & GPIO_PIN_PULLUP)
501 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP);
502 else if (flags & GPIO_PIN_PULLDOWN)
503 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN);
505 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE);
511 aw_gpio_get_bus(device_t dev)
513 struct aw_gpio_softc *sc;
515 sc = device_get_softc(dev);
517 return (sc->sc_busdev);
521 aw_gpio_pin_max(device_t dev, int *maxpin)
523 struct aw_gpio_softc *sc;
525 sc = device_get_softc(dev);
527 *maxpin = sc->conf->padconf->npins - 1;
532 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
534 struct aw_gpio_softc *sc;
536 sc = device_get_softc(dev);
537 if (pin >= sc->conf->padconf->npins)
540 *caps = AW_GPIO_DEFAULT_CAPS;
541 if (sc->conf->padconf->pins[pin].eint_func != 0)
542 *caps |= AW_GPIO_INTR_CAPS;
548 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
550 struct aw_gpio_softc *sc;
554 sc = device_get_softc(dev);
555 if (pin >= sc->conf->padconf->npins)
559 func = aw_gpio_get_function(sc, pin);
562 *flags = GPIO_PIN_INPUT;
565 *flags = GPIO_PIN_OUTPUT;
572 pud = aw_gpio_get_pud(sc, pin);
574 case AW_GPIO_PULLDOWN:
575 *flags |= GPIO_PIN_PULLDOWN;
578 *flags |= GPIO_PIN_PULLUP;
590 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
592 struct aw_gpio_softc *sc;
594 sc = device_get_softc(dev);
595 if (pin >= sc->conf->padconf->npins)
598 snprintf(name, GPIOMAXNAME - 1, "%s",
599 sc->conf->padconf->pins[pin].name);
600 name[GPIOMAXNAME - 1] = '\0';
606 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
608 struct aw_gpio_softc *sc;
611 sc = device_get_softc(dev);
612 if (pin > sc->conf->padconf->npins)
616 err = aw_gpio_pin_configure(sc, pin, flags);
623 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin,
628 AW_GPIO_LOCK_ASSERT(sc);
630 if (pin > sc->conf->padconf->npins)
633 bank = sc->conf->padconf->pins[pin].port;
634 pin = sc->conf->padconf->pins[pin].pin;
636 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
641 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
647 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
649 struct aw_gpio_softc *sc;
652 sc = device_get_softc(dev);
655 ret = aw_gpio_pin_set_locked(sc, pin, value);
662 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin,
665 uint32_t bank, reg_data;
667 AW_GPIO_LOCK_ASSERT(sc);
669 if (pin > sc->conf->padconf->npins)
672 bank = sc->conf->padconf->pins[pin].port;
673 pin = sc->conf->padconf->pins[pin].pin;
675 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
676 *val = (reg_data & (1 << pin)) ? 1 : 0;
682 aw_gpio_parse_function(phandle_t node)
686 if (OF_getprop_alloc(node, "function",
687 (void **)&function) != -1)
689 if (OF_getprop_alloc(node, "allwinner,function",
690 (void **)&function) != -1)
697 aw_gpio_parse_pins(phandle_t node, int *pins_nb)
699 const char **pinlist;
701 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist);
705 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins",
714 aw_gpio_parse_bias(phandle_t node)
718 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1)
720 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1)
722 if (OF_hasprop(node, "bias-disable"))
723 return (AW_GPIO_NONE);
724 if (OF_hasprop(node, "bias-pull-up"))
725 return (AW_GPIO_PULLUP);
726 if (OF_hasprop(node, "bias-pull-down"))
727 return (AW_GPIO_PULLDOWN);
729 return (AW_GPIO_NONE);
733 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
737 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1)
739 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1)
741 if (OF_getencprop(node, "drive-strength", &drive_str,
742 sizeof(drive_str)) != -1) {
743 *drive = (drive_str / 10) - 1;
751 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
753 struct aw_gpio_softc *sc;
756 sc = device_get_softc(dev);
759 ret = aw_gpio_pin_get_locked(sc, pin, val);
766 aw_gpio_pin_toggle(device_t dev, uint32_t pin)
768 struct aw_gpio_softc *sc;
771 sc = device_get_softc(dev);
772 if (pin > sc->conf->padconf->npins)
775 bank = sc->conf->padconf->pins[pin].port;
776 pin = sc->conf->padconf->pins[pin].pin;
779 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
780 if (data & (1 << pin))
784 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
791 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
792 uint32_t change_pins, uint32_t *orig_pins)
794 struct aw_gpio_softc *sc;
795 uint32_t bank, data, pin;
797 sc = device_get_softc(dev);
798 if (first_pin > sc->conf->padconf->npins)
802 * We require that first_pin refers to the first pin in a bank, because
803 * this API is not about convenience, it's for making a set of pins
804 * change simultaneously (required) with reasonably high performance
805 * (desired); we need to do a read-modify-write on a single register.
807 bank = sc->conf->padconf->pins[first_pin].port;
808 pin = sc->conf->padconf->pins[first_pin].pin;
813 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
814 if ((clear_pins | change_pins) != 0)
815 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank),
816 (data & ~clear_pins) ^ change_pins);
819 if (orig_pins != NULL)
826 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
829 struct aw_gpio_softc *sc;
833 sc = device_get_softc(dev);
834 if (first_pin > sc->conf->padconf->npins)
837 bank = sc->conf->padconf->pins[first_pin].port;
838 if (sc->conf->padconf->pins[first_pin].pin != 0)
842 * The configuration for a bank of pins is scattered among several
843 * registers; we cannot g'tee to simultaneously change the state of all
844 * the pins in the flags array. So just loop through the array
845 * configuring each pin for now. If there was a strong need, it might
846 * be possible to support some limited simultaneous config, such as
847 * adjacent groups of 8 pins that line up the same as the config regs.
849 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
850 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
851 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]);
858 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
859 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
861 struct aw_gpio_softc *sc;
864 sc = device_get_softc(bus);
866 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
867 for (i = 0; i < sc->conf->padconf->npins; i++)
868 if (sc->conf->padconf->pins[i].port == gpios[0] &&
869 sc->conf->padconf->pins[i].pin == gpios[1]) {
873 *flags = gpios[gcells - 1];
879 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname)
883 for (i = 0; i < sc->conf->padconf->npins; i++)
884 if (!strcmp(pinname, sc->conf->padconf->pins[i].name))
891 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func)
895 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
896 if (sc->conf->padconf->pins[pin].functions[i] &&
897 !strcmp(func, sc->conf->padconf->pins[pin].functions[i]))
904 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
906 struct aw_gpio_softc *sc;
908 const char **pinlist = NULL;
909 char *pin_function = NULL;
910 uint32_t pin_drive, pin_pull;
911 int pins_nb, pin_num, pin_func, i, ret;
914 sc = device_get_softc(dev);
915 node = OF_node_from_xref(cfgxref);
919 /* Getting all prop for configuring pins */
920 pinlist = aw_gpio_parse_pins(node, &pins_nb);
924 pin_function = aw_gpio_parse_function(node);
925 if (pin_function == NULL) {
930 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0)
933 pin_pull = aw_gpio_parse_bias(node);
935 /* Configure each pin to the correct function, drive and pull */
936 for (i = 0; i < pins_nb; i++) {
937 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
942 pin_func = aw_find_pin_func(sc, pin_num, pin_function);
943 if (pin_func == -1) {
950 if (aw_gpio_get_function(sc, pin_num) != pin_func)
951 aw_gpio_set_function(sc, pin_num, pin_func);
953 aw_gpio_set_drv(sc, pin_num, pin_drive);
954 if (pin_pull != AW_GPIO_NONE)
955 aw_gpio_set_pud(sc, pin_num, pin_pull);
961 OF_prop_free(pinlist);
962 OF_prop_free(pin_function);
967 aw_gpio_enable_bank_supply(void *arg)
969 struct aw_gpio_softc *sc = arg;
970 regulator_t vcc_supply;
971 char bank_reg_name[16];
974 nbanks = strlen(sc->conf->banks);
975 for (i = 0; i < nbanks; i++) {
976 snprintf(bank_reg_name, sizeof(bank_reg_name), "vcc-p%c-supply",
979 if (regulator_get_by_ofw_property(sc->sc_dev, 0, bank_reg_name, &vcc_supply) == 0) {
981 device_printf(sc->sc_dev,
982 "Enabling regulator for gpio bank %c\n",
984 if (regulator_enable(vcc_supply) != 0) {
985 device_printf(sc->sc_dev,
986 "Cannot enable regulator for bank %c\n",
994 aw_gpio_probe(device_t dev)
997 if (!ofw_bus_status_okay(dev))
1000 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1003 device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
1004 return (BUS_PROBE_DEFAULT);
1008 aw_gpio_attach(device_t dev)
1012 struct aw_gpio_softc *sc;
1013 struct clk_list *clkp, *clkp_tmp;
1015 hwreset_t rst = NULL;
1016 int off, err, clkret;
1018 sc = device_get_softc(dev);
1021 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN);
1023 if (bus_alloc_resources(dev, aw_gpio_res_spec, sc->sc_res) != 0) {
1024 device_printf(dev, "cannot allocate device resources\n");
1028 if (bus_setup_intr(dev, sc->sc_res[AW_GPIO_IRQRES],
1029 INTR_TYPE_CLK | INTR_MPSAFE, NULL, aw_gpio_intr, sc,
1030 &sc->sc_intrhand)) {
1031 device_printf(dev, "cannot setup interrupt handler\n");
1035 /* Find our node. */
1036 gpio = ofw_bus_get_node(sc->sc_dev);
1037 if (!OF_hasprop(gpio, "gpio-controller"))
1038 /* Node is not a GPIO controller. */
1041 /* Use the right pin data for the current SoC */
1042 sc->conf = (struct aw_gpio_conf *)ofw_bus_search_compatible(dev,
1043 compat_data)->ocd_data;
1045 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
1046 error = hwreset_deassert(rst);
1048 device_printf(dev, "cannot de-assert reset\n");
1053 TAILQ_INIT(&sc->clk_list);
1054 for (off = 0, clkret = 0; clkret == 0; off++) {
1055 clkret = clk_get_by_ofw_index(dev, 0, off, &clk);
1058 err = clk_enable(clk);
1060 device_printf(dev, "Could not enable clock %s\n",
1064 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
1066 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
1068 if (clkret != 0 && clkret != ENOENT) {
1069 device_printf(dev, "Could not find clock at offset %d (%d)\n",
1075 aw_gpio_register_isrcs(sc);
1076 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
1079 sc->sc_busdev = gpiobus_attach_bus(dev);
1080 if (sc->sc_busdev == NULL)
1084 * Register as a pinctrl device
1086 fdt_pinctrl_register(dev, "pins");
1087 fdt_pinctrl_configure_tree(dev);
1088 fdt_pinctrl_register(dev, "allwinner,pins");
1089 fdt_pinctrl_configure_tree(dev);
1091 config_intrhook_oneshot(aw_gpio_enable_bank_supply, sc);
1097 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
1099 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
1100 mtx_destroy(&sc->sc_mtx);
1103 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
1104 err = clk_disable(clkp->clk);
1106 device_printf(dev, "Could not disable clock %s\n",
1107 clk_get_name(clkp->clk));
1108 err = clk_release(clkp->clk);
1110 device_printf(dev, "Could not release clock %s\n",
1111 clk_get_name(clkp->clk));
1112 TAILQ_REMOVE(&sc->clk_list, clkp, next);
1113 free(clkp, M_DEVBUF);
1118 hwreset_assert(rst);
1119 hwreset_release(rst);
1126 aw_gpio_detach(device_t dev)
1133 aw_gpio_intr(void *arg)
1135 struct aw_gpio_softc *sc;
1136 struct intr_irqsrc *isrc;
1140 sc = (struct aw_gpio_softc *)arg;
1143 for (irq = 0; irq < sc->nirqs; irq++) {
1144 if (!sc->gpio_pic_irqsrc[irq].enabled)
1147 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank));
1148 if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum)))
1151 isrc = &sc->gpio_pic_irqsrc[irq].isrc;
1152 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
1153 aw_gpio_pic_disable_intr_locked(sc, isrc);
1154 aw_gpio_pic_post_filter(sc->sc_dev, isrc);
1155 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq);
1162 * Interrupts support
1166 aw_gpio_register_isrcs(struct aw_gpio_softc *sc)
1173 name = device_get_nameunit(sc->sc_dev);
1175 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1176 if (sc->conf->padconf->pins[pin].eint_func == 0)
1182 sc->gpio_pic_irqsrc = malloc(sizeof(*sc->gpio_pic_irqsrc) * nirqs,
1183 M_DEVBUF, M_WAITOK | M_ZERO);
1184 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1185 if (sc->conf->padconf->pins[pin].eint_func == 0)
1188 sc->gpio_pic_irqsrc[nirqs].pin = pin;
1189 sc->gpio_pic_irqsrc[nirqs].bank = sc->conf->padconf->pins[pin].eint_bank;
1190 sc->gpio_pic_irqsrc[nirqs].intnum = sc->conf->padconf->pins[pin].eint_num;
1191 sc->gpio_pic_irqsrc[nirqs].intfunc = sc->conf->padconf->pins[pin].eint_func;
1192 sc->gpio_pic_irqsrc[nirqs].irq = nirqs;
1193 sc->gpio_pic_irqsrc[nirqs].mode = GPIO_INTR_CONFORM;
1195 err = intr_isrc_register(&sc->gpio_pic_irqsrc[nirqs].isrc,
1196 sc->sc_dev, 0, "%s,%s", name,
1197 sc->conf->padconf->pins[pin].functions[sc->conf->padconf->pins[pin].eint_func]);
1199 device_printf(sc->sc_dev, "intr_isrs_register failed for irq %d\n", nirqs);
1211 aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc)
1216 AW_GPIO_LOCK_ASSERT(sc);
1217 irq = ((struct gpio_irqsrc *)isrc)->irq;
1218 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1219 reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum);
1220 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1222 sc->gpio_pic_irqsrc[irq].enabled = false;
1226 aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1228 struct aw_gpio_softc *sc;
1230 sc = device_get_softc(dev);
1233 aw_gpio_pic_disable_intr_locked(sc, isrc);
1238 aw_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1240 struct aw_gpio_softc *sc;
1244 sc = device_get_softc(dev);
1245 irq = ((struct gpio_irqsrc *)isrc)->irq;
1247 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1248 reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum;
1249 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1252 sc->gpio_pic_irqsrc[irq].enabled = true;
1256 aw_gpio_pic_map_gpio(struct aw_gpio_softc *sc, struct intr_map_data_gpio *dag,
1257 u_int *irqp, u_int *mode)
1262 irq = dag->gpio_pin_num;
1264 for (pin = 0; pin < sc->nirqs; pin++)
1265 if (sc->gpio_pic_irqsrc[pin].pin == irq)
1267 if (pin == sc->nirqs) {
1268 device_printf(sc->sc_dev, "Invalid interrupt number %u\n", irq);
1272 switch (dag->gpio_intr_mode) {
1273 case GPIO_INTR_LEVEL_LOW:
1274 case GPIO_INTR_LEVEL_HIGH:
1275 case GPIO_INTR_EDGE_RISING:
1276 case GPIO_INTR_EDGE_FALLING:
1277 case GPIO_INTR_EDGE_BOTH:
1280 device_printf(sc->sc_dev, "Unsupported interrupt mode 0x%8x\n",
1281 dag->gpio_intr_mode);
1287 *mode = dag->gpio_intr_mode;
1293 aw_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1294 struct intr_irqsrc **isrcp)
1296 struct aw_gpio_softc *sc;
1300 sc = device_get_softc(dev);
1301 switch (data->type) {
1302 case INTR_MAP_DATA_GPIO:
1303 err = aw_gpio_pic_map_gpio(sc,
1304 (struct intr_map_data_gpio *)data,
1312 *isrcp = &sc->gpio_pic_irqsrc[irq].isrc;
1317 aw_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1318 struct resource *res, struct intr_map_data *data)
1320 struct aw_gpio_softc *sc;
1321 struct gpio_irqsrc *gi;
1323 uint32_t pinidx, reg;
1327 sc = device_get_softc(dev);
1328 gi = (struct gpio_irqsrc *)isrc;
1330 switch (data->type) {
1331 case INTR_MAP_DATA_GPIO:
1332 err = aw_gpio_pic_map_gpio(sc,
1333 (struct intr_map_data_gpio *)data,
1340 pinidx = (sc->gpio_pic_irqsrc[irq].intnum % 8) * 4;
1344 case GPIO_INTR_LEVEL_LOW:
1345 irqcfg = AW_GPIO_INT_LEVEL_LOW << pinidx;
1347 case GPIO_INTR_LEVEL_HIGH:
1348 irqcfg = AW_GPIO_INT_LEVEL_HIGH << pinidx;
1350 case GPIO_INTR_EDGE_RISING:
1351 irqcfg = AW_GPIO_INT_EDGE_POSITIVE << pinidx;
1353 case GPIO_INTR_EDGE_FALLING:
1354 irqcfg = AW_GPIO_INT_EDGE_NEGATIVE << pinidx;
1356 case GPIO_INTR_EDGE_BOTH:
1357 irqcfg = AW_GPIO_INT_EDGE_BOTH << pinidx;
1361 /* Switch the pin to interrupt mode */
1362 sc->gpio_pic_irqsrc[irq].oldfunc = aw_gpio_get_function(sc,
1363 sc->gpio_pic_irqsrc[irq].pin);
1364 aw_gpio_set_function(sc, sc->gpio_pic_irqsrc[irq].pin,
1365 sc->gpio_pic_irqsrc[irq].intfunc);
1367 /* Write interrupt mode */
1368 reg = AW_GPIO_READ(sc,
1369 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1370 sc->gpio_pic_irqsrc[irq].intnum));
1371 reg &= ~(0xF << pinidx);
1374 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1375 sc->gpio_pic_irqsrc[irq].intnum),
1384 aw_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1385 struct resource *res, struct intr_map_data *data)
1387 struct aw_gpio_softc *sc;
1388 struct gpio_irqsrc *gi;
1390 sc = device_get_softc(dev);
1391 gi = (struct gpio_irqsrc *)isrc;
1393 /* Switch back the pin to it's original function */
1395 aw_gpio_set_function(sc, gi->pin, gi->oldfunc);
1402 aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1404 struct aw_gpio_softc *sc;
1405 struct gpio_irqsrc *gi;
1407 sc = device_get_softc(dev);
1408 gi = (struct gpio_irqsrc *)isrc;
1410 arm_irq_memory_barrier(0);
1411 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1415 aw_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1417 struct aw_gpio_softc *sc;
1418 struct gpio_irqsrc *gi;
1420 sc = device_get_softc(dev);
1421 gi = (struct gpio_irqsrc *)isrc;
1423 arm_irq_memory_barrier(0);
1424 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1425 aw_gpio_pic_enable_intr(dev, isrc);
1429 aw_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1431 struct aw_gpio_softc *sc;
1433 sc = device_get_softc(dev);
1434 aw_gpio_pic_disable_intr_locked(sc, isrc);
1441 aw_gpio_get_node(device_t dev, device_t bus)
1444 /* We only have one child, the GPIO bus, which needs our own node. */
1445 return (ofw_bus_get_node(dev));
1448 static device_method_t aw_gpio_methods[] = {
1449 /* Device interface */
1450 DEVMETHOD(device_probe, aw_gpio_probe),
1451 DEVMETHOD(device_attach, aw_gpio_attach),
1452 DEVMETHOD(device_detach, aw_gpio_detach),
1455 /* Interrupt controller interface */
1456 DEVMETHOD(pic_disable_intr, aw_gpio_pic_disable_intr),
1457 DEVMETHOD(pic_enable_intr, aw_gpio_pic_enable_intr),
1458 DEVMETHOD(pic_map_intr, aw_gpio_pic_map_intr),
1459 DEVMETHOD(pic_setup_intr, aw_gpio_pic_setup_intr),
1460 DEVMETHOD(pic_teardown_intr, aw_gpio_pic_teardown_intr),
1461 DEVMETHOD(pic_post_filter, aw_gpio_pic_post_filter),
1462 DEVMETHOD(pic_post_ithread, aw_gpio_pic_post_ithread),
1463 DEVMETHOD(pic_pre_ithread, aw_gpio_pic_pre_ithread),
1467 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus),
1468 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max),
1469 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname),
1470 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags),
1471 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps),
1472 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags),
1473 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get),
1474 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set),
1475 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle),
1476 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32),
1477 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32),
1478 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios),
1480 /* ofw_bus interface */
1481 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node),
1483 /* fdt_pinctrl interface */
1484 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
1489 static devclass_t aw_gpio_devclass;
1491 static driver_t aw_gpio_driver = {
1494 sizeof(struct aw_gpio_softc),
1497 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, aw_gpio_devclass, 0, 0,
1498 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);