sys/arm/allwinner/aw_mmc.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
   5  * Copyright (c) 2013 Alexander Fedorov
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/conf.h>
  37 #include <sys/kernel.h>
  38 #include <sys/lock.h>
  39 #include <sys/malloc.h>
  40 #include <sys/module.h>
  41 #include <sys/mutex.h>
  42 #include <sys/resource.h>
  43 #include <sys/rman.h>
  44 #include <sys/sysctl.h>
  45 #include <sys/queue.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <machine/bus.h>
  49
  50 #include <dev/ofw/ofw_bus.h>
  51 #include <dev/ofw/ofw_bus_subr.h>
  52
  53 #include <dev/mmc/bridge.h>
  54 #include <dev/mmc/mmcbrvar.h>
  55 #include <dev/mmc/mmc_fdt_helpers.h>
  56
  57 #include <arm/allwinner/aw_mmc.h>
  58 #include <dev/extres/clk/clk.h>
  59 #include <dev/extres/hwreset/hwreset.h>
  60 #include <dev/extres/regulator/regulator.h>
  61
  62 #include "opt_mmccam.h"
  63
  64 #ifdef MMCCAM
  65 #include <cam/cam.h>
  66 #include <cam/cam_ccb.h>
  67 #include <cam/cam_debug.h>
  68 #include <cam/cam_sim.h>
  69 #include <cam/cam_xpt_sim.h>
  70 #include <cam/mmc/mmc_sim.h>
  71
  72 #include "mmc_sim_if.h"
  73 #endif
  74
  75 #include "mmc_pwrseq_if.h"
  76
  77 #define AW_MMC_MEMRES           0
  78 #define AW_MMC_IRQRES           1
  79 #define AW_MMC_RESSZ            2
  80 #define AW_MMC_DMA_SEGS         (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc))
  81 #define AW_MMC_DMA_DESC_SIZE    (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS)
  82 #define AW_MMC_DMA_FTRGLEVEL    0x20070008
  83
  84 #define AW_MMC_RESET_RETRY      1000
  85
  86 #define CARD_ID_FREQUENCY       400000
  87
  88 struct aw_mmc_conf {
  89         uint32_t        dma_xferlen;
  90         bool            mask_data0;
  91         bool            can_calibrate;
  92         bool            new_timing;
  93 };
  94
  95 static const struct aw_mmc_conf a10_mmc_conf = {
  96         .dma_xferlen = 0x2000,
  97 };
  98
  99 static const struct aw_mmc_conf a13_mmc_conf = {
 100         .dma_xferlen = 0x10000,
 101 };
 102
 103 static const struct aw_mmc_conf a64_mmc_conf = {
 104         .dma_xferlen = 0x10000,
 105         .mask_data0 = true,
 106         .can_calibrate = true,
 107         .new_timing = true,
 108 };
 109
 110 static const struct aw_mmc_conf a64_emmc_conf = {
 111         .dma_xferlen = 0x2000,
 112         .can_calibrate = true,
 113 };
 114
 115 static struct ofw_compat_data compat_data[] = {
 116         {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf},
 117         {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf},
 118         {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf},
 119         {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf},
 120         {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf},
 121         {NULL,             0}
 122 };
 123
 124 struct aw_mmc_softc {
 125         device_t                aw_dev;
 126         clk_t                   aw_clk_ahb;
 127         clk_t                   aw_clk_mmc;
 128         hwreset_t               aw_rst_ahb;
 129         int                     aw_bus_busy;
 130         int                     aw_resid;
 131         int                     aw_timeout;
 132         struct callout          aw_timeoutc;
 133         struct mmc_host         aw_host;
 134         struct mmc_helper       mmc_helper;
 135 #ifdef MMCCAM
 136         union ccb *             ccb;
 137         struct mmc_sim          mmc_sim;
 138 #else
 139         struct mmc_request *    aw_req;
 140 #endif
 141         struct mtx              aw_mtx;
 142         struct resource *       aw_res[AW_MMC_RESSZ];
 143         struct aw_mmc_conf *    aw_mmc_conf;
 144         uint32_t                aw_intr;
 145         uint32_t                aw_intr_wait;
 146         void *                  aw_intrhand;
 147         unsigned int            aw_clock;
 148         device_t                child;
 149
 150         /* Fields required for DMA access. */
 151         bus_addr_t              aw_dma_desc_phys;
 152         bus_dmamap_t            aw_dma_map;
 153         bus_dma_tag_t           aw_dma_tag;
 154         void *                  aw_dma_desc;
 155         bus_dmamap_t            aw_dma_buf_map;
 156         bus_dma_tag_t           aw_dma_buf_tag;
 157         int                     aw_dma_map_err;
 158 };
 159
 160 static struct resource_spec aw_mmc_res_spec[] = {
 161         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 162         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_SHAREABLE },
 163         { -1,                   0,      0 }
 164 };
 165
 166 static int aw_mmc_probe(device_t);
 167 static int aw_mmc_attach(device_t);
 168 static int aw_mmc_detach(device_t);
 169 static int aw_mmc_setup_dma(struct aw_mmc_softc *);
 170 static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc);
 171 static int aw_mmc_reset(struct aw_mmc_softc *);
 172 static int aw_mmc_init(struct aw_mmc_softc *);
 173 static void aw_mmc_intr(void *);
 174 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t);
 175 static void aw_mmc_helper_cd_handler(device_t, bool);
 176
 177 static void aw_mmc_print_error(uint32_t);
 178 static int aw_mmc_update_ios(device_t, device_t);
 179 static int aw_mmc_request(device_t, device_t, struct mmc_request *);
 180
 181 #ifndef MMCCAM
 182 static int aw_mmc_get_ro(device_t, device_t);
 183 static int aw_mmc_acquire_host(device_t, device_t);
 184 static int aw_mmc_release_host(device_t, device_t);
 185 #endif
 186
 187 #define AW_MMC_LOCK(_sc)        mtx_lock(&(_sc)->aw_mtx)
 188 #define AW_MMC_UNLOCK(_sc)      mtx_unlock(&(_sc)->aw_mtx)
 189 #define AW_MMC_READ_4(_sc, _reg)                                        \
 190         bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg)
 191 #define AW_MMC_WRITE_4(_sc, _reg, _value)                               \
 192         bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value)
 193
 194 SYSCTL_NODE(_hw, OID_AUTO, aw_mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 195     "aw_mmc driver");
 196
 197 static int aw_mmc_debug = 0;
 198 SYSCTL_INT(_hw_aw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_mmc_debug, 0,
 199     "Debug level bit0=card changes bit1=ios changes, bit2=interrupts, bit3=commands");
 200 #define AW_MMC_DEBUG_CARD       0x1
 201 #define AW_MMC_DEBUG_IOS        0x2
 202 #define AW_MMC_DEBUG_INT        0x4
 203 #define AW_MMC_DEBUG_CMD        0x8
 204
 205 #ifdef MMCCAM
 206 static int
 207 aw_mmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
 208 {
 209         struct aw_mmc_softc *sc;
 210
 211         sc = device_get_softc(dev);
 212
 213         cts->host_ocr = sc->aw_host.host_ocr;
 214         cts->host_f_min = sc->aw_host.f_min;
 215         cts->host_f_max = sc->aw_host.f_max;
 216         cts->host_caps = sc->aw_host.caps;
 217         cts->host_max_data = (sc->aw_mmc_conf->dma_xferlen *
 218             AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
 219         memcpy(&cts->ios, &sc->aw_host.ios, sizeof(struct mmc_ios));
 220
 221         return (0);
 222 }
 223
 224 static int
 225 aw_mmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
 226 {
 227         struct aw_mmc_softc *sc;
 228         struct mmc_ios *ios;
 229         struct mmc_ios *new_ios;
 230
 231         sc = device_get_softc(dev);
 232         ios = &sc->aw_host.ios;
 233         new_ios = &cts->ios;
 234
 235         /* Update only requested fields */
 236         if (cts->ios_valid & MMC_CLK) {
 237                 ios->clock = new_ios->clock;
 238                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
 239                         device_printf(sc->aw_dev, "Clock => %d\n", ios->clock);
 240         }
 241         if (cts->ios_valid & MMC_VDD) {
 242                 ios->vdd = new_ios->vdd;
 243                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
 244                         device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd);
 245         }
 246         if (cts->ios_valid & MMC_CS) {
 247                 ios->chip_select = new_ios->chip_select;
 248                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
 249                         device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select);
 250         }
 251         if (cts->ios_valid & MMC_BW) {
 252                 ios->bus_width = new_ios->bus_width;
 253                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
 254                         device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width);
 255         }
 256         if (cts->ios_valid & MMC_PM) {
 257                 ios->power_mode = new_ios->power_mode;
 258                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
 259                         device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode);
 260         }
 261         if (cts->ios_valid & MMC_BT) {
 262                 ios->timing = new_ios->timing;
 263                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
 264                         device_printf(sc->aw_dev, "Timing => %d\n", ios->timing);
 265         }
 266         if (cts->ios_valid & MMC_BM) {
 267                 ios->bus_mode = new_ios->bus_mode;
 268                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
 269                         device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode);
 270         }
 271
 272         return (aw_mmc_update_ios(sc->aw_dev, NULL));
 273 }
 274
 275 static int
 276 aw_mmc_cam_request(device_t dev, union ccb *ccb)
 277 {
 278         struct aw_mmc_softc *sc;
 279         struct ccb_mmcio *mmcio;
 280
 281         sc = device_get_softc(dev);
 282         mmcio = &ccb->mmcio;
 283
 284         AW_MMC_LOCK(sc);
 285
 286         if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
 287                 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
 288                             mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
 289                             mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
 290                             mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
 291         }
 292         if (mmcio->cmd.data != NULL) {
 293                 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
 294                         panic("data->len = %d, data->flags = %d -- something is b0rked",
 295                               (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
 296         }
 297         if (sc->ccb != NULL) {
 298                 device_printf(sc->aw_dev, "Controller still has an active command\n");
 299                 return (EBUSY);
 300         }
 301         sc->ccb = ccb;
 302         /* aw_mmc_request locks again */
 303         AW_MMC_UNLOCK(sc);
 304         aw_mmc_request(sc->aw_dev, NULL, NULL);
 305
 306         return (0);
 307 }
 308
 309 static void
 310 aw_mmc_cam_poll(device_t dev)
 311 {
 312         struct aw_mmc_softc *sc;
 313
 314         sc = device_get_softc(dev);
 315         aw_mmc_intr(sc);
 316 }
 317 #endif /* MMCCAM */
 318
 319 static void
 320 aw_mmc_helper_cd_handler(device_t dev, bool present)
 321 {
 322         struct aw_mmc_softc *sc;
 323
 324         sc = device_get_softc(dev);
 325 #ifdef MMCCAM
 326         mmc_cam_sim_discover(&sc->mmc_sim);
 327 #else
 328         AW_MMC_LOCK(sc);
 329         if (present) {
 330                 if (sc->child == NULL) {
 331                         if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
 332                                 device_printf(sc->aw_dev, "Card inserted\n");
 333
 334                         sc->child = device_add_child(sc->aw_dev, "mmc", -1);
 335                         AW_MMC_UNLOCK(sc);
 336                         if (sc->child) {
 337                                 device_set_ivars(sc->child, sc);
 338                                 (void)device_probe_and_attach(sc->child);
 339                         }
 340                 } else
 341                         AW_MMC_UNLOCK(sc);
 342         } else {
 343                 /* Card isn't present, detach if necessary */
 344                 if (sc->child != NULL) {
 345                         if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
 346                                 device_printf(sc->aw_dev, "Card removed\n");
 347
 348                         AW_MMC_UNLOCK(sc);
 349                         device_delete_child(sc->aw_dev, sc->child);
 350                         sc->child = NULL;
 351                 } else
 352                         AW_MMC_UNLOCK(sc);
 353         }
 354 #endif /* MMCCAM */
 355 }
 356
 357 static int
 358 aw_mmc_probe(device_t dev)
 359 {
 360
 361         if (!ofw_bus_status_okay(dev))
 362                 return (ENXIO);
 363         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 364                 return (ENXIO);
 365
 366         device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
 367
 368         return (BUS_PROBE_DEFAULT);
 369 }
 370
 371 static int
 372 aw_mmc_attach(device_t dev)
 373 {
 374         struct aw_mmc_softc *sc;
 375         struct sysctl_ctx_list *ctx;
 376         struct sysctl_oid_list *tree;
 377         int error;
 378
 379         sc = device_get_softc(dev);
 380         sc->aw_dev = dev;
 381
 382         sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
 383
 384 #ifndef MMCCAM
 385         sc->aw_req = NULL;
 386 #endif
 387         if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) {
 388                 device_printf(dev, "cannot allocate device resources\n");
 389                 return (ENXIO);
 390         }
 391         if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES],
 392             INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc,
 393             &sc->aw_intrhand)) {
 394                 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
 395                 device_printf(dev, "cannot setup interrupt handler\n");
 396                 return (ENXIO);
 397         }
 398         mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc",
 399             MTX_DEF);
 400         callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0);
 401
 402         /* De-assert reset */
 403         if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) {
 404                 error = hwreset_deassert(sc->aw_rst_ahb);
 405                 if (error != 0) {
 406                         device_printf(dev, "cannot de-assert reset\n");
 407                         goto fail;
 408                 }
 409         }
 410
 411         /* Activate the module clock. */
 412         error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb);
 413         if (error != 0) {
 414                 device_printf(dev, "cannot get ahb clock\n");
 415                 goto fail;
 416         }
 417         error = clk_enable(sc->aw_clk_ahb);
 418         if (error != 0) {
 419                 device_printf(dev, "cannot enable ahb clock\n");
 420                 goto fail;
 421         }
 422         error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc);
 423         if (error != 0) {
 424                 device_printf(dev, "cannot get mmc clock\n");
 425                 goto fail;
 426         }
 427         error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY,
 428             CLK_SET_ROUND_DOWN);
 429         if (error != 0) {
 430                 device_printf(dev, "cannot init mmc clock\n");
 431                 goto fail;
 432         }
 433         error = clk_enable(sc->aw_clk_mmc);
 434         if (error != 0) {
 435                 device_printf(dev, "cannot enable mmc clock\n");
 436                 goto fail;
 437         }
 438
 439         sc->aw_timeout = 10;
 440         ctx = device_get_sysctl_ctx(dev);
 441         tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
 442         SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
 443             &sc->aw_timeout, 0, "Request timeout in seconds");
 444
 445         /* Soft Reset controller. */
 446         if (aw_mmc_reset(sc) != 0) {
 447                 device_printf(dev, "cannot reset the controller\n");
 448                 goto fail;
 449         }
 450
 451         if (aw_mmc_setup_dma(sc) != 0) {
 452                 device_printf(sc->aw_dev, "Couldn't setup DMA!\n");
 453                 goto fail;
 454         }
 455
 456         /* Set some defaults for freq and supported mode */
 457         sc->aw_host.f_min = 400000;
 458         sc->aw_host.f_max = 52000000;
 459         sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
 460         sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330;
 461         mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host);
 462         mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler);
 463
 464 #ifdef MMCCAM
 465         sc->ccb = NULL;
 466
 467         if (mmc_cam_sim_alloc(dev, "aw_mmc", &sc->mmc_sim) != 0) {
 468                 device_printf(dev, "cannot alloc cam sim\n");
 469                 goto fail;
 470         }
 471 #endif /* MMCCAM */
 472
 473         return (0);
 474
 475 fail:
 476         callout_drain(&sc->aw_timeoutc);
 477         mtx_destroy(&sc->aw_mtx);
 478         bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
 479         bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
 480
 481         return (ENXIO);
 482 }
 483
 484 static int
 485 aw_mmc_detach(device_t dev)
 486 {
 487         struct aw_mmc_softc *sc;
 488         device_t d;
 489
 490         sc = device_get_softc(dev);
 491
 492         clk_disable(sc->aw_clk_mmc);
 493         clk_disable(sc->aw_clk_ahb);
 494         hwreset_assert(sc->aw_rst_ahb);
 495
 496         mmc_fdt_gpio_teardown(&sc->mmc_helper);
 497
 498         callout_drain(&sc->aw_timeoutc);
 499
 500         AW_MMC_LOCK(sc);
 501         d = sc->child;
 502         sc->child = NULL;
 503         AW_MMC_UNLOCK(sc);
 504         if (d != NULL)
 505                 device_delete_child(sc->aw_dev, d);
 506
 507         aw_mmc_teardown_dma(sc);
 508
 509         mtx_destroy(&sc->aw_mtx);
 510
 511         bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
 512         bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
 513
 514 #ifdef MMCCAM
 515         mmc_cam_sim_free(&sc->mmc_sim);
 516 #endif
 517
 518         return (0);
 519 }
 520
 521 static void
 522 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
 523 {
 524         struct aw_mmc_softc *sc;
 525
 526         sc = (struct aw_mmc_softc *)arg;
 527         if (err) {
 528                 sc->aw_dma_map_err = err;
 529                 return;
 530         }
 531         sc->aw_dma_desc_phys = segs[0].ds_addr;
 532 }
 533
 534 static int
 535 aw_mmc_setup_dma(struct aw_mmc_softc *sc)
 536 {
 537         int error;
 538
 539         /* Allocate the DMA descriptor memory. */
 540         error = bus_dma_tag_create(
 541             bus_get_dma_tag(sc->aw_dev),        /* parent */
 542             AW_MMC_DMA_ALIGN, 0,                /* align, boundary */
 543             BUS_SPACE_MAXADDR_32BIT,            /* lowaddr */
 544             BUS_SPACE_MAXADDR,                  /* highaddr */
 545             NULL, NULL,                         /* filter, filterarg*/
 546             AW_MMC_DMA_DESC_SIZE, 1,            /* maxsize, nsegment */
 547             AW_MMC_DMA_DESC_SIZE,               /* maxsegsize */
 548             0,                                  /* flags */
 549             NULL, NULL,                         /* lock, lockarg*/
 550             &sc->aw_dma_tag);
 551         if (error)
 552                 return (error);
 553
 554         error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc,
 555             BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
 556             &sc->aw_dma_map);
 557         if (error)
 558                 return (error);
 559
 560         error = bus_dmamap_load(sc->aw_dma_tag,
 561             sc->aw_dma_map,
 562             sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE,
 563             aw_dma_desc_cb, sc, 0);
 564         if (error)
 565                 return (error);
 566         if (sc->aw_dma_map_err)
 567                 return (sc->aw_dma_map_err);
 568
 569         /* Create the DMA map for data transfers. */
 570         error = bus_dma_tag_create(
 571             bus_get_dma_tag(sc->aw_dev),        /* parent */
 572             AW_MMC_DMA_ALIGN, 0,                /* align, boundary */
 573             BUS_SPACE_MAXADDR_32BIT,            /* lowaddr */
 574             BUS_SPACE_MAXADDR,                  /* highaddr */
 575             NULL, NULL,                         /* filter, filterarg*/
 576             sc->aw_mmc_conf->dma_xferlen *
 577             AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS,   /* maxsize, nsegments */
 578             sc->aw_mmc_conf->dma_xferlen,       /* maxsegsize */
 579             BUS_DMA_ALLOCNOW,                   /* flags */
 580             NULL, NULL,                         /* lock, lockarg*/
 581             &sc->aw_dma_buf_tag);
 582         if (error)
 583                 return (error);
 584         error = bus_dmamap_create(sc->aw_dma_buf_tag, 0,
 585             &sc->aw_dma_buf_map);
 586         if (error)
 587                 return (error);
 588
 589         return (0);
 590 }
 591
 592 static void
 593 aw_mmc_teardown_dma(struct aw_mmc_softc *sc)
 594 {
 595
 596         bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map);
 597         bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map);
 598         if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0)
 599                 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n");
 600
 601         bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
 602         bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
 603         if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0)
 604                 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n");
 605 }
 606
 607 static void
 608 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
 609 {
 610         int i;
 611         struct aw_mmc_dma_desc *dma_desc;
 612         struct aw_mmc_softc *sc;
 613
 614         sc = (struct aw_mmc_softc *)arg;
 615         sc->aw_dma_map_err = err;
 616
 617         if (err)
 618                 return;
 619
 620         dma_desc = sc->aw_dma_desc;
 621         for (i = 0; i < nsegs; i++) {
 622                 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen)
 623                         dma_desc[i].buf_size = 0;               /* Size of 0 indicate max len */
 624                 else
 625                         dma_desc[i].buf_size = segs[i].ds_len;
 626                 dma_desc[i].buf_addr = segs[i].ds_addr;
 627                 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH |
 628                         AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC;
 629
 630                 dma_desc[i].next = sc->aw_dma_desc_phys +
 631                         ((i + 1) * sizeof(struct aw_mmc_dma_desc));
 632         }
 633
 634         dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD;
 635         dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD |
 636                 AW_MMC_DMA_CONFIG_ER;
 637         dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC;
 638         dma_desc[nsegs - 1].next = 0;
 639 }
 640
 641 static int
 642 aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
 643 {
 644         bus_dmasync_op_t sync_op;
 645         int error;
 646         struct mmc_command *cmd;
 647         uint32_t val;
 648
 649 #ifdef MMCCAM
 650         cmd = &sc->ccb->mmcio.cmd;
 651 #else
 652         cmd = sc->aw_req->cmd;
 653 #endif
 654         if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS))
 655                 return (EFBIG);
 656         error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
 657             cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0);
 658         if (error)
 659                 return (error);
 660         if (sc->aw_dma_map_err)
 661                 return (sc->aw_dma_map_err);
 662
 663         if (cmd->data->flags & MMC_DATA_WRITE)
 664                 sync_op = BUS_DMASYNC_PREWRITE;
 665         else
 666                 sync_op = BUS_DMASYNC_PREREAD;
 667         bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op);
 668         bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE);
 669
 670         /* Enable DMA */
 671         val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
 672         val &= ~AW_MMC_GCTL_FIFO_AC_MOD;
 673         val |= AW_MMC_GCTL_DMA_ENB;
 674         AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
 675
 676         /* Reset DMA */
 677         val |= AW_MMC_GCTL_DMA_RST;
 678         AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
 679
 680         AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST);
 681         AW_MMC_WRITE_4(sc, AW_MMC_DMAC,
 682             AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST);
 683
 684         /* Enable RX or TX DMA interrupt */
 685         val = AW_MMC_READ_4(sc, AW_MMC_IDIE);
 686         if (cmd->data->flags & MMC_DATA_WRITE)
 687                 val |= AW_MMC_IDST_TX_INT;
 688         else
 689                 val |= AW_MMC_IDST_RX_INT;
 690         AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val);
 691
 692         /* Set DMA descritptor list address */
 693         AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys);
 694
 695         /* FIFO trigger level */
 696         AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL);
 697
 698         return (0);
 699 }
 700
 701 static int
 702 aw_mmc_reset(struct aw_mmc_softc *sc)
 703 {
 704         uint32_t reg;
 705         int timeout;
 706
 707         reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
 708         reg |= AW_MMC_GCTL_RESET;
 709         AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
 710         timeout = AW_MMC_RESET_RETRY;
 711         while (--timeout > 0) {
 712                 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0)
 713                         break;
 714                 DELAY(100);
 715         }
 716         if (timeout == 0)
 717                 return (ETIMEDOUT);
 718
 719         return (0);
 720 }
 721
 722 static int
 723 aw_mmc_init(struct aw_mmc_softc *sc)
 724 {
 725         uint32_t reg;
 726         int ret;
 727
 728         ret = aw_mmc_reset(sc);
 729         if (ret != 0)
 730                 return (ret);
 731
 732         /* Set the timeout. */
 733         AW_MMC_WRITE_4(sc, AW_MMC_TMOR,
 734             AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) |
 735             AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK));
 736
 737         /* Unmask interrupts. */
 738         AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0);
 739
 740         /* Clear pending interrupts. */
 741         AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
 742
 743         /* Debug register, undocumented */
 744         AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb);
 745
 746         /* Function select register */
 747         AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000);
 748
 749         AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
 750
 751         /* Enable interrupts and disable AHB access. */
 752         reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
 753         reg |= AW_MMC_GCTL_INT_ENB;
 754         reg &= ~AW_MMC_GCTL_FIFO_AC_MOD;
 755         reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS;
 756         AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
 757
 758         return (0);
 759 }
 760
 761 static void
 762 aw_mmc_req_done(struct aw_mmc_softc *sc)
 763 {
 764         struct mmc_command *cmd;
 765 #ifdef MMCCAM
 766         union ccb *ccb;
 767 #else
 768         struct mmc_request *req;
 769 #endif
 770         uint32_t val, mask;
 771         int retry;
 772
 773 #ifdef MMCCAM
 774         ccb = sc->ccb;
 775         cmd = &ccb->mmcio.cmd;
 776 #else
 777         cmd = sc->aw_req->cmd;
 778 #endif
 779         if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
 780                 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error);
 781         }
 782         if (cmd->error != MMC_ERR_NONE) {
 783                 /* Reset the FIFO and DMA engines. */
 784                 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST;
 785                 val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
 786                 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask);
 787
 788                 retry = AW_MMC_RESET_RETRY;
 789                 while (--retry > 0) {
 790                         if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) &
 791                             AW_MMC_GCTL_RESET) == 0)
 792                                 break;
 793                         DELAY(100);
 794                 }
 795                 if (retry == 0)
 796                         device_printf(sc->aw_dev,
 797                             "timeout resetting DMA/FIFO\n");
 798                 aw_mmc_update_clock(sc, 1);
 799         }
 800
 801         if (!dumping)
 802                 callout_stop(&sc->aw_timeoutc);
 803         sc->aw_intr = 0;
 804         sc->aw_resid = 0;
 805         sc->aw_dma_map_err = 0;
 806         sc->aw_intr_wait = 0;
 807 #ifdef MMCCAM
 808         sc->ccb = NULL;
 809         ccb->ccb_h.status =
 810                 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
 811         xpt_done(ccb);
 812 #else
 813         req = sc->aw_req;
 814         sc->aw_req = NULL;
 815         req->done(req);
 816 #endif
 817 }
 818
 819 static void
 820 aw_mmc_req_ok(struct aw_mmc_softc *sc)
 821 {
 822         int timeout;
 823         struct mmc_command *cmd;
 824         uint32_t status;
 825
 826         timeout = 1000;
 827         while (--timeout > 0) {
 828                 status = AW_MMC_READ_4(sc, AW_MMC_STAR);
 829                 if ((status & AW_MMC_STAR_CARD_BUSY) == 0)
 830                         break;
 831                 DELAY(1000);
 832         }
 833 #ifdef MMCCAM
 834         cmd = &sc->ccb->mmcio.cmd;
 835 #else
 836         cmd = sc->aw_req->cmd;
 837 #endif
 838         if (timeout == 0) {
 839                 cmd->error = MMC_ERR_FAILED;
 840                 aw_mmc_req_done(sc);
 841                 return;
 842         }
 843         if (cmd->flags & MMC_RSP_PRESENT) {
 844                 if (cmd->flags & MMC_RSP_136) {
 845                         cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3);
 846                         cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2);
 847                         cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1);
 848                         cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
 849                 } else
 850                         cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
 851         }
 852         /* All data has been transferred ? */
 853         if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len)
 854                 cmd->error = MMC_ERR_FAILED;
 855         aw_mmc_req_done(sc);
 856 }
 857
 858 static inline void
 859 set_mmc_error(struct aw_mmc_softc *sc, int error_code)
 860 {
 861 #ifdef MMCCAM
 862         sc->ccb->mmcio.cmd.error = error_code;
 863 #else
 864         sc->aw_req->cmd->error = error_code;
 865 #endif
 866 }
 867
 868 static void
 869 aw_mmc_timeout(void *arg)
 870 {
 871         struct aw_mmc_softc *sc;
 872
 873         sc = (struct aw_mmc_softc *)arg;
 874 #ifdef MMCCAM
 875         if (sc->ccb != NULL) {
 876 #else
 877         if (sc->aw_req != NULL) {
 878 #endif
 879                 device_printf(sc->aw_dev, "controller timeout\n");
 880                 set_mmc_error(sc, MMC_ERR_TIMEOUT);
 881                 aw_mmc_req_done(sc);
 882         } else
 883                 device_printf(sc->aw_dev,
 884                     "Spurious timeout - no active request\n");
 885 }
 886
 887 static void
 888 aw_mmc_print_error(uint32_t err)
 889 {
 890         if(err & AW_MMC_INT_RESP_ERR)
 891                 printf("AW_MMC_INT_RESP_ERR ");
 892         if (err & AW_MMC_INT_RESP_CRC_ERR)
 893                 printf("AW_MMC_INT_RESP_CRC_ERR ");
 894         if (err & AW_MMC_INT_DATA_CRC_ERR)
 895                 printf("AW_MMC_INT_DATA_CRC_ERR ");
 896         if (err & AW_MMC_INT_RESP_TIMEOUT)
 897                 printf("AW_MMC_INT_RESP_TIMEOUT ");
 898         if (err & AW_MMC_INT_FIFO_RUN_ERR)
 899                 printf("AW_MMC_INT_FIFO_RUN_ERR ");
 900         if (err & AW_MMC_INT_CMD_BUSY)
 901                 printf("AW_MMC_INT_CMD_BUSY ");
 902         if (err & AW_MMC_INT_DATA_START_ERR)
 903                 printf("AW_MMC_INT_DATA_START_ERR ");
 904         if (err & AW_MMC_INT_DATA_END_BIT_ERR)
 905                 printf("AW_MMC_INT_DATA_END_BIT_ERR");
 906         printf("\n");
 907 }
 908
 909 static void
 910 aw_mmc_intr(void *arg)
 911 {
 912         bus_dmasync_op_t sync_op;
 913         struct aw_mmc_softc *sc;
 914         struct mmc_data *data;
 915         uint32_t idst, imask, rint;
 916
 917         sc = (struct aw_mmc_softc *)arg;
 918         AW_MMC_LOCK(sc);
 919         rint = AW_MMC_READ_4(sc, AW_MMC_RISR);
 920         idst = AW_MMC_READ_4(sc, AW_MMC_IDST);
 921         imask = AW_MMC_READ_4(sc, AW_MMC_IMKR);
 922         if (idst == 0 && imask == 0 && rint == 0) {
 923                 AW_MMC_UNLOCK(sc);
 924                 return;
 925         }
 926         if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
 927                 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n",
 928                     idst, imask, rint);
 929         }
 930 #ifdef MMCCAM
 931         if (sc->ccb == NULL) {
 932 #else
 933         if (sc->aw_req == NULL) {
 934 #endif
 935                 device_printf(sc->aw_dev,
 936                     "Spurious interrupt - no active request, rint: 0x%08X\n",
 937                     rint);
 938                 aw_mmc_print_error(rint);
 939                 goto end;
 940         }
 941         if (rint & AW_MMC_INT_ERR_BIT) {
 942                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
 943                         device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
 944                         aw_mmc_print_error(rint);
 945                 }
 946                 if (rint & AW_MMC_INT_RESP_TIMEOUT)
 947                         set_mmc_error(sc, MMC_ERR_TIMEOUT);
 948                 else
 949                         set_mmc_error(sc, MMC_ERR_FAILED);
 950                 aw_mmc_req_done(sc);
 951                 goto end;
 952         }
 953         if (idst & AW_MMC_IDST_ERROR) {
 954                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT))
 955                         device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst);
 956                 set_mmc_error(sc, MMC_ERR_FAILED);
 957                 aw_mmc_req_done(sc);
 958                 goto end;
 959         }
 960
 961         sc->aw_intr |= rint;
 962 #ifdef MMCCAM
 963         data = sc->ccb->mmcio.cmd.data;
 964 #else
 965         data = sc->aw_req->cmd->data;
 966 #endif
 967         if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) {
 968                 if (data->flags & MMC_DATA_WRITE)
 969                         sync_op = BUS_DMASYNC_POSTWRITE;
 970                 else
 971                         sync_op = BUS_DMASYNC_POSTREAD;
 972                 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
 973                     sync_op);
 974                 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map,
 975                     BUS_DMASYNC_POSTWRITE);
 976                 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
 977                 sc->aw_resid = data->len >> 2;
 978         }
 979         if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait)
 980                 aw_mmc_req_ok(sc);
 981
 982 end:
 983         AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst);
 984         AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint);
 985         AW_MMC_UNLOCK(sc);
 986 }
 987
 988 static int
 989 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
 990 {
 991         int blksz;
 992         struct aw_mmc_softc *sc;
 993         struct mmc_command *cmd;
 994         uint32_t cmdreg, imask;
 995         int err;
 996
 997         sc = device_get_softc(bus);
 998
 999         AW_MMC_LOCK(sc);
1000 #ifdef MMCCAM
1001         KASSERT(req == NULL, ("req should be NULL in MMCCAM case!"));
1002         /*
1003          * For MMCCAM, sc->ccb has been NULL-checked and populated
1004          * by aw_mmc_cam_request() already.
1005          */
1006         cmd = &sc->ccb->mmcio.cmd;
1007 #else
1008         if (sc->aw_req) {
1009                 AW_MMC_UNLOCK(sc);
1010                 return (EBUSY);
1011         }
1012         sc->aw_req = req;
1013         cmd = req->cmd;
1014
1015         if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
1016                 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1017                               cmd->opcode, cmd->arg, cmd->flags,
1018                               cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
1019                               cmd->data != NULL ? cmd->data->flags: 0);
1020         }
1021 #endif
1022         cmdreg = AW_MMC_CMDR_LOAD;
1023         imask = AW_MMC_INT_ERR_BIT;
1024         sc->aw_intr_wait = 0;
1025         sc->aw_intr = 0;
1026         sc->aw_resid = 0;
1027         cmd->error = MMC_ERR_NONE;
1028
1029         if (cmd->opcode == MMC_GO_IDLE_STATE)
1030                 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ;
1031
1032         if (cmd->flags & MMC_RSP_PRESENT)
1033                 cmdreg |= AW_MMC_CMDR_RESP_RCV;
1034         if (cmd->flags & MMC_RSP_136)
1035                 cmdreg |= AW_MMC_CMDR_LONG_RESP;
1036         if (cmd->flags & MMC_RSP_CRC)
1037                 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC;
1038
1039         if (cmd->data) {
1040                 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER;
1041
1042                 if (cmd->data->flags & MMC_DATA_MULTI) {
1043                         cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG;
1044                         imask |= AW_MMC_INT_AUTO_STOP_DONE;
1045                         sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE;
1046                 } else {
1047                         sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
1048                         imask |= AW_MMC_INT_DATA_OVER;
1049                 }
1050                 if (cmd->data->flags & MMC_DATA_WRITE)
1051                         cmdreg |= AW_MMC_CMDR_DIR_WRITE;
1052 #ifdef MMCCAM
1053                 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) {
1054                         AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size);
1055                         AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1056                 } else
1057 #endif
1058                 {
1059                         blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
1060                         AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz);
1061                         AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1062                 }
1063         } else {
1064                 imask |= AW_MMC_INT_CMD_DONE;
1065         }
1066
1067         /* Enable the interrupts we are interested in */
1068         AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask);
1069         AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1070
1071         /* Enable auto stop if needed */
1072         AW_MMC_WRITE_4(sc, AW_MMC_A12A,
1073             cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff);
1074
1075         /* Write the command argument */
1076         AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
1077
1078         /*
1079          * If we don't have data start the request
1080          * if we do prepare the dma request and start the request
1081          */
1082         if (cmd->data == NULL) {
1083                 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1084         } else {
1085                 err = aw_mmc_prepare_dma(sc);
1086                 if (err != 0)
1087                         device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err);
1088
1089                 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1090         }
1091
1092         if (!dumping) {
1093                 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz,
1094                     aw_mmc_timeout, sc);
1095         }
1096         AW_MMC_UNLOCK(sc);
1097
1098         return (0);
1099 }
1100
1101 static int
1102 aw_mmc_read_ivar(device_t bus, device_t child, int which,
1103     uintptr_t *result)
1104 {
1105         struct aw_mmc_softc *sc;
1106
1107         sc = device_get_softc(bus);
1108         switch (which) {
1109         default:
1110                 return (EINVAL);
1111         case MMCBR_IVAR_BUS_MODE:
1112                 *(int *)result = sc->aw_host.ios.bus_mode;
1113                 break;
1114         case MMCBR_IVAR_BUS_WIDTH:
1115                 *(int *)result = sc->aw_host.ios.bus_width;
1116                 break;
1117         case MMCBR_IVAR_CHIP_SELECT:
1118                 *(int *)result = sc->aw_host.ios.chip_select;
1119                 break;
1120         case MMCBR_IVAR_CLOCK:
1121                 *(int *)result = sc->aw_host.ios.clock;
1122                 break;
1123         case MMCBR_IVAR_F_MIN:
1124                 *(int *)result = sc->aw_host.f_min;
1125                 break;
1126         case MMCBR_IVAR_F_MAX:
1127                 *(int *)result = sc->aw_host.f_max;
1128                 break;
1129         case MMCBR_IVAR_HOST_OCR:
1130                 *(int *)result = sc->aw_host.host_ocr;
1131                 break;
1132         case MMCBR_IVAR_MODE:
1133                 *(int *)result = sc->aw_host.mode;
1134                 break;
1135         case MMCBR_IVAR_OCR:
1136                 *(int *)result = sc->aw_host.ocr;
1137                 break;
1138         case MMCBR_IVAR_POWER_MODE:
1139                 *(int *)result = sc->aw_host.ios.power_mode;
1140                 break;
1141         case MMCBR_IVAR_VDD:
1142                 *(int *)result = sc->aw_host.ios.vdd;
1143                 break;
1144         case MMCBR_IVAR_VCCQ:
1145                 *(int *)result = sc->aw_host.ios.vccq;
1146                 break;
1147         case MMCBR_IVAR_CAPS:
1148                 *(int *)result = sc->aw_host.caps;
1149                 break;
1150         case MMCBR_IVAR_TIMING:
1151                 *(int *)result = sc->aw_host.ios.timing;
1152                 break;
1153         case MMCBR_IVAR_MAX_DATA:
1154                 *(int *)result = (sc->aw_mmc_conf->dma_xferlen *
1155                     AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
1156                 break;
1157         case MMCBR_IVAR_RETUNE_REQ:
1158                 *(int *)result = retune_req_none;
1159                 break;
1160         }
1161
1162         return (0);
1163 }
1164
1165 static int
1166 aw_mmc_write_ivar(device_t bus, device_t child, int which,
1167     uintptr_t value)
1168 {
1169         struct aw_mmc_softc *sc;
1170
1171         sc = device_get_softc(bus);
1172         switch (which) {
1173         default:
1174                 return (EINVAL);
1175         case MMCBR_IVAR_BUS_MODE:
1176                 sc->aw_host.ios.bus_mode = value;
1177                 break;
1178         case MMCBR_IVAR_BUS_WIDTH:
1179                 sc->aw_host.ios.bus_width = value;
1180                 break;
1181         case MMCBR_IVAR_CHIP_SELECT:
1182                 sc->aw_host.ios.chip_select = value;
1183                 break;
1184         case MMCBR_IVAR_CLOCK:
1185                 sc->aw_host.ios.clock = value;
1186                 break;
1187         case MMCBR_IVAR_MODE:
1188                 sc->aw_host.mode = value;
1189                 break;
1190         case MMCBR_IVAR_OCR:
1191                 sc->aw_host.ocr = value;
1192                 break;
1193         case MMCBR_IVAR_POWER_MODE:
1194                 sc->aw_host.ios.power_mode = value;
1195                 break;
1196         case MMCBR_IVAR_VDD:
1197                 sc->aw_host.ios.vdd = value;
1198                 break;
1199         case MMCBR_IVAR_VCCQ:
1200                 sc->aw_host.ios.vccq = value;
1201                 break;
1202         case MMCBR_IVAR_TIMING:
1203                 sc->aw_host.ios.timing = value;
1204                 break;
1205         /* These are read-only */
1206         case MMCBR_IVAR_CAPS:
1207         case MMCBR_IVAR_HOST_OCR:
1208         case MMCBR_IVAR_F_MIN:
1209         case MMCBR_IVAR_F_MAX:
1210         case MMCBR_IVAR_MAX_DATA:
1211                 return (EINVAL);
1212         }
1213
1214         return (0);
1215 }
1216
1217 static int
1218 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon)
1219 {
1220         uint32_t reg;
1221         int retry;
1222
1223         reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1224         reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER |
1225             AW_MMC_CKCR_MASK_DATA0);
1226
1227         if (clkon)
1228                 reg |= AW_MMC_CKCR_ENB;
1229         if (sc->aw_mmc_conf->mask_data0)
1230                 reg |= AW_MMC_CKCR_MASK_DATA0;
1231
1232         AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1233
1234         reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
1235             AW_MMC_CMDR_WAIT_PRE_OVER;
1236         AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg);
1237         retry = 0xfffff;
1238
1239         while (reg & AW_MMC_CMDR_LOAD && --retry > 0) {
1240                 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR);
1241                 DELAY(10);
1242         }
1243         AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1244
1245         if (reg & AW_MMC_CMDR_LOAD) {
1246                 device_printf(sc->aw_dev, "timeout updating clock\n");
1247                 return (ETIMEDOUT);
1248         }
1249
1250         if (sc->aw_mmc_conf->mask_data0) {
1251                 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1252                 reg &= ~AW_MMC_CKCR_MASK_DATA0;
1253                 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1254         }
1255
1256         return (0);
1257 }
1258
1259 #ifndef MMCCAM
1260 static int
1261 aw_mmc_switch_vccq(device_t bus, device_t child)
1262 {
1263         struct aw_mmc_softc *sc;
1264         int uvolt, err;
1265
1266         sc = device_get_softc(bus);
1267
1268         if (sc->mmc_helper.vqmmc_supply == NULL)
1269                 return EOPNOTSUPP;
1270
1271         switch (sc->aw_host.ios.vccq) {
1272         case vccq_180:
1273                 uvolt = 1800000;
1274                 break;
1275         case vccq_330:
1276                 uvolt = 3300000;
1277                 break;
1278         default:
1279                 return EINVAL;
1280         }
1281
1282         err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt);
1283         if (err != 0) {
1284                 device_printf(sc->aw_dev,
1285                     "Cannot set vqmmc to %d<->%d\n",
1286                     uvolt,
1287                     uvolt);
1288                 return (err);
1289         }
1290
1291         return (0);
1292 }
1293 #endif
1294
1295 static int
1296 aw_mmc_update_ios(device_t bus, device_t child)
1297 {
1298         int error;
1299         struct aw_mmc_softc *sc;
1300         struct mmc_ios *ios;
1301         unsigned int clock;
1302         uint32_t reg, div = 1;
1303         int reg_status;
1304         int rv;
1305
1306         sc = device_get_softc(bus);
1307
1308         ios = &sc->aw_host.ios;
1309
1310         /* Set the bus width. */
1311         switch (ios->bus_width) {
1312         case bus_width_1:
1313                 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1);
1314                 break;
1315         case bus_width_4:
1316                 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4);
1317                 break;
1318         case bus_width_8:
1319                 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8);
1320                 break;
1321         }
1322
1323         switch (ios->power_mode) {
1324         case power_on:
1325                 break;
1326         case power_off:
1327                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1328                         device_printf(sc->aw_dev, "Powering down sd/mmc\n");
1329
1330                 if (sc->mmc_helper.vmmc_supply) {
1331                         rv = regulator_status(sc->mmc_helper.vmmc_supply, &reg_status);
1332                         if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1333                                 regulator_disable(sc->mmc_helper.vmmc_supply);
1334                 }
1335                 if (sc->mmc_helper.vqmmc_supply) {
1336                         rv = regulator_status(sc->mmc_helper.vqmmc_supply, &reg_status);
1337                         if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1338                                 regulator_disable(sc->mmc_helper.vqmmc_supply);
1339                 }
1340
1341                 if (sc->mmc_helper.mmc_pwrseq)
1342                         MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, false);
1343
1344                 aw_mmc_reset(sc);
1345                 break;
1346         case power_up:
1347                 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1348                         device_printf(sc->aw_dev, "Powering up sd/mmc\n");
1349
1350                 if (sc->mmc_helper.vmmc_supply) {
1351                         rv = regulator_status(sc->mmc_helper.vmmc_supply, &reg_status);
1352                         if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1353                                 regulator_enable(sc->mmc_helper.vmmc_supply);
1354                 }
1355                 if (sc->mmc_helper.vqmmc_supply) {
1356                         rv = regulator_status(sc->mmc_helper.vqmmc_supply, &reg_status);
1357                         if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1358                                 regulator_enable(sc->mmc_helper.vqmmc_supply);
1359                 }
1360
1361                 if (sc->mmc_helper.mmc_pwrseq)
1362                         MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, true);
1363                 aw_mmc_init(sc);
1364                 break;
1365         };
1366
1367         /* Enable ddr mode if needed */
1368         reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
1369         if (ios->timing == bus_timing_uhs_ddr50 ||
1370           ios->timing == bus_timing_mmc_ddr52)
1371                 reg |= AW_MMC_GCTL_DDR_MOD_SEL;
1372         else
1373                 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL;
1374         AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
1375
1376         if (ios->clock && ios->clock != sc->aw_clock) {
1377                 sc->aw_clock = clock = ios->clock;
1378
1379                 /* Disable clock */
1380                 error = aw_mmc_update_clock(sc, 0);
1381                 if (error != 0)
1382                         return (error);
1383
1384                 if (ios->timing == bus_timing_mmc_ddr52 &&
1385                     (sc->aw_mmc_conf->new_timing ||
1386                     ios->bus_width == bus_width_8)) {
1387                         div = 2;
1388                         clock <<= 1;
1389                 }
1390
1391                 /* Reset the divider. */
1392                 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1393                 reg &= ~AW_MMC_CKCR_DIV;
1394                 reg |= div - 1;
1395                 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1396
1397                 /* New timing mode if needed */
1398                 if (sc->aw_mmc_conf->new_timing) {
1399                         reg = AW_MMC_READ_4(sc, AW_MMC_NTSR);
1400                         reg |= AW_MMC_NTSR_MODE_SELECT;
1401                         AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg);
1402                 }
1403
1404                 /* Set the MMC clock. */
1405                 error = clk_disable(sc->aw_clk_mmc);
1406                 if (error != 0 && bootverbose)
1407                         device_printf(sc->aw_dev,
1408                           "failed to disable mmc clock: %d\n", error);
1409                 error = clk_set_freq(sc->aw_clk_mmc, clock,
1410                     CLK_SET_ROUND_DOWN);
1411                 if (error != 0) {
1412                         device_printf(sc->aw_dev,
1413                             "failed to set frequency to %u Hz: %d\n",
1414                             clock, error);
1415                         return (error);
1416                 }
1417                 error = clk_enable(sc->aw_clk_mmc);
1418                 if (error != 0 && bootverbose)
1419                         device_printf(sc->aw_dev,
1420                           "failed to re-enable mmc clock: %d\n", error);
1421
1422                 if (sc->aw_mmc_conf->can_calibrate)
1423                         AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN);
1424
1425                 /* Enable clock. */
1426                 error = aw_mmc_update_clock(sc, 1);
1427                 if (error != 0)
1428                         return (error);
1429         }
1430
1431         return (0);
1432 }
1433
1434 #ifndef MMCCAM
1435 static int
1436 aw_mmc_get_ro(device_t bus, device_t child)
1437 {
1438         struct aw_mmc_softc *sc;
1439
1440         sc = device_get_softc(bus);
1441
1442         return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper));
1443 }
1444
1445 static int
1446 aw_mmc_acquire_host(device_t bus, device_t child)
1447 {
1448         struct aw_mmc_softc *sc;
1449         int error;
1450
1451         sc = device_get_softc(bus);
1452         AW_MMC_LOCK(sc);
1453         while (sc->aw_bus_busy) {
1454                 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0);
1455                 if (error != 0) {
1456                         AW_MMC_UNLOCK(sc);
1457                         return (error);
1458                 }
1459         }
1460         sc->aw_bus_busy++;
1461         AW_MMC_UNLOCK(sc);
1462
1463         return (0);
1464 }
1465
1466 static int
1467 aw_mmc_release_host(device_t bus, device_t child)
1468 {
1469         struct aw_mmc_softc *sc;
1470
1471         sc = device_get_softc(bus);
1472         AW_MMC_LOCK(sc);
1473         sc->aw_bus_busy--;
1474         wakeup(sc);
1475         AW_MMC_UNLOCK(sc);
1476
1477         return (0);
1478 }
1479 #endif
1480
1481 static device_method_t aw_mmc_methods[] = {
1482         /* Device interface */
1483         DEVMETHOD(device_probe,         aw_mmc_probe),
1484         DEVMETHOD(device_attach,        aw_mmc_attach),
1485         DEVMETHOD(device_detach,        aw_mmc_detach),
1486
1487         /* Bus interface */
1488         DEVMETHOD(bus_read_ivar,        aw_mmc_read_ivar),
1489         DEVMETHOD(bus_write_ivar,       aw_mmc_write_ivar),
1490         DEVMETHOD(bus_add_child,        bus_generic_add_child),
1491
1492 #ifndef MMCCAM
1493         /* MMC bridge interface */
1494         DEVMETHOD(mmcbr_update_ios,     aw_mmc_update_ios),
1495         DEVMETHOD(mmcbr_request,        aw_mmc_request),
1496         DEVMETHOD(mmcbr_get_ro,         aw_mmc_get_ro),
1497         DEVMETHOD(mmcbr_switch_vccq,    aw_mmc_switch_vccq),
1498         DEVMETHOD(mmcbr_acquire_host,   aw_mmc_acquire_host),
1499         DEVMETHOD(mmcbr_release_host,   aw_mmc_release_host),
1500 #endif
1501
1502 #ifdef MMCCAM
1503         /* MMCCAM interface */
1504         DEVMETHOD(mmc_sim_get_tran_settings,    aw_mmc_get_tran_settings),
1505         DEVMETHOD(mmc_sim_set_tran_settings,    aw_mmc_set_tran_settings),
1506         DEVMETHOD(mmc_sim_cam_request,          aw_mmc_cam_request),
1507         DEVMETHOD(mmc_sim_cam_poll,             aw_mmc_cam_poll),
1508 #endif
1509
1510         DEVMETHOD_END
1511 };
1512
1513 static driver_t aw_mmc_driver = {
1514         "aw_mmc",
1515         aw_mmc_methods,
1516         sizeof(struct aw_mmc_softc),
1517 };
1518
1519 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, NULL, NULL);
1520 #ifndef MMCCAM
1521 MMC_DECLARE_BRIDGE(aw_mmc);
1522 #endif
1523 SIMPLEBUS_PNP_INFO(compat_data);