2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner RSB (Reduced Serial Bus)
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <dev/iicbus/iiconf.h>
48 #include <dev/iicbus/iicbus.h>
50 #include <dev/extres/clk/clk.h>
51 #include <dev/extres/hwreset/hwreset.h>
53 #include "iicbus_if.h"
56 #define START_TRANS (1 << 7)
57 #define GLOBAL_INT_ENB (1 << 1)
58 #define SOFT_RESET (1 << 0)
62 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf)
63 #define INT_LOAD_BSY (1 << 2)
64 #define INT_TRANS_ERR (1 << 1)
65 #define INT_TRANS_OVER (1 << 0)
66 #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER)
67 #define RSB_DADDR0 0x10
68 #define RSB_DADDR1 0x14
70 #define DLEN_READ (1 << 4)
71 #define RSB_DATA0 0x1c
72 #define RSB_DATA1 0x20
82 #define DAR_RTA (0xff << 16)
83 #define DAR_RTA_SHIFT 16
84 #define DAR_DA (0xffff << 0)
85 #define DAR_DA_SHIFT 0
88 #define RSB_RESET_RETRY 100
89 #define RSB_I2C_TIMEOUT hz
91 #define RSB_ADDR_PMIC_PRIMARY 0x3a3
92 #define RSB_ADDR_PMIC_SECONDARY 0x745
93 #define RSB_ADDR_PERIPH_IC 0xe89
95 static struct ofw_compat_data compat_data[] = {
96 { "allwinner,sun8i-a23-rsb", 1 },
100 static struct resource_spec rsb_spec[] = {
101 { SYS_RES_MEMORY, 0, RF_ACTIVE },
106 * Device address to Run-time address mappings.
108 * Run-time address (RTA) is an 8-bit value used to address the device during
109 * a read or write transaction. The following are valid RTAs:
110 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff
112 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC,
113 * and 0x4e for the peripheral IC (where applicable).
115 static const struct {
119 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d },
120 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a },
121 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e },
122 { .addr = 0, .rta = 0 }
126 struct resource *res;
138 #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx)
139 #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
140 #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
141 #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg))
142 #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
145 rsb_get_node(device_t bus, device_t dev)
147 return (ofw_bus_get_node(bus));
151 rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
153 struct rsb_softc *sc;
156 sc = device_get_softc(dev);
160 /* Write soft-reset bit and wait for it to self-clear. */
161 RSB_WRITE(sc, RSB_CTRL, SOFT_RESET);
162 for (retry = RSB_RESET_RETRY; retry > 0; retry--)
163 if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0)
169 device_printf(dev, "soft reset timeout\n");
173 return (IIC_ENOADDR);
177 rsb_encode(const uint8_t *buf, u_int len, u_int off)
183 for (n = off; n < MIN(len, 4 + off); n++)
184 val |= ((uint32_t)buf[n] << ((n - off) * NBBY));
190 rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off)
194 for (n = off; n < MIN(len, 4 + off); n++)
195 buf[n] = (val >> ((n - off) * NBBY)) & 0xff;
199 rsb_start(device_t dev)
201 struct rsb_softc *sc;
204 sc = device_get_softc(dev);
206 RSB_ASSERT_LOCKED(sc);
208 /* Start the transfer */
209 RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS);
211 /* Wait for transfer to complete */
213 for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) {
214 sc->status |= RSB_READ(sc, RSB_INTS);
215 if ((sc->status & INT_TRANS_OVER) != 0) {
219 DELAY((1000 * hz) / RSB_I2C_TIMEOUT);
221 if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) {
222 device_printf(dev, "transfer error, status 0x%08x\n",
232 rsb_set_rta(device_t dev, uint16_t addr)
234 struct rsb_softc *sc;
238 sc = device_get_softc(dev);
240 RSB_ASSERT_LOCKED(sc);
242 /* Lookup run-time address for given device address */
243 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++)
244 if (rsb_rtamap[i].addr == addr) {
245 rta = rsb_rtamap[i].rta;
249 device_printf(dev, "RTA not known for address %#x\n", addr);
253 /* Set run-time address */
254 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
255 RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT));
256 RSB_WRITE(sc, RSB_CMD, CMD_SRTA);
258 return (rsb_start(dev));
262 rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
264 struct rsb_softc *sc;
265 uint32_t daddr[2], data[2], dlen;
266 uint16_t device_addr;
270 sc = device_get_softc(dev);
273 * RSB is not really an I2C or SMBus controller, so there are some
274 * restrictions imposed by the driver.
276 * Transfers must contain exactly two messages. The first is always
277 * a write, containing a single data byte offset. Data will either
278 * be read from or written to the corresponding data byte in the
279 * second message. The slave address in both messages must be the
282 if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD ||
283 (msgs[0].slave >> 1) != (msgs[1].slave >> 1) ||
284 msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN)
287 /* The controller can read or write 1, 2, or 4 bytes at a time. */
288 if ((msgs[1].flags & IIC_M_RD) != 0) {
289 switch (msgs[1].len) {
303 switch (msgs[1].len) {
320 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
324 /* Select current run-time address if necessary */
325 device_addr = msgs[0].slave >> 1;
326 if (sc->cur_addr != device_addr) {
327 error = rsb_set_rta(dev, device_addr);
330 sc->cur_addr = device_addr;
334 /* Clear interrupt status */
335 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
337 /* Program data access address registers */
338 daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0);
339 RSB_WRITE(sc, RSB_DADDR0, daddr[0]);
342 if ((msgs[1].flags & IIC_M_RD) == 0) {
343 data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0);
344 RSB_WRITE(sc, RSB_DATA0, data[0]);
347 /* Set command type */
348 RSB_WRITE(sc, RSB_CMD, cmd);
350 /* Program data length register and transfer direction */
351 dlen = msgs[0].len - 1;
352 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD)
354 RSB_WRITE(sc, RSB_DLEN, dlen);
357 error = rsb_start(dev);
362 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) {
363 data[0] = RSB_READ(sc, RSB_DATA0);
364 rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0);
377 rsb_probe(device_t dev)
379 if (!ofw_bus_status_okay(dev))
382 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
385 device_set_desc(dev, "Allwinner RSB");
386 return (BUS_PROBE_DEFAULT);
390 rsb_attach(device_t dev)
392 struct rsb_softc *sc;
395 sc = device_get_softc(dev);
396 mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF);
398 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) {
399 error = clk_enable(sc->clk);
401 device_printf(dev, "cannot enable clock\n");
405 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) {
406 error = hwreset_deassert(sc->rst);
408 device_printf(dev, "cannot de-assert reset\n");
413 if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) {
414 device_printf(dev, "cannot allocate resources for device\n");
419 sc->iicbus = device_add_child(dev, "iicbus", -1);
420 if (sc->iicbus == NULL) {
421 device_printf(dev, "cannot add iicbus child device\n");
426 bus_generic_attach(dev);
431 bus_release_resources(dev, rsb_spec, &sc->res);
433 hwreset_release(sc->rst);
435 clk_release(sc->clk);
436 mtx_destroy(&sc->mtx);
440 static device_method_t rsb_methods[] = {
441 /* Device interface */
442 DEVMETHOD(device_probe, rsb_probe),
443 DEVMETHOD(device_attach, rsb_attach),
446 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
447 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
448 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
449 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
450 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
451 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
452 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
453 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
454 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
457 DEVMETHOD(ofw_bus_get_node, rsb_get_node),
459 /* iicbus interface */
460 DEVMETHOD(iicbus_callback, iicbus_null_callback),
461 DEVMETHOD(iicbus_reset, rsb_reset),
462 DEVMETHOD(iicbus_transfer, rsb_transfer),
467 static driver_t rsb_driver = {
470 sizeof(struct rsb_softc),
473 static devclass_t rsb_devclass;
475 EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0,
476 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
477 EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0,
478 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
479 MODULE_VERSION(rsb, 1);