2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface)
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <machine/bus.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/iicbus/iiconf.h>
49 #include <dev/iicbus/iicbus.h>
51 #include <dev/extres/clk/clk.h>
52 #include <dev/extres/hwreset/hwreset.h>
54 #include "iicbus_if.h"
57 #define START_TRANS (1 << 7)
58 #define GLOBAL_INT_ENB (1 << 1)
59 #define SOFT_RESET (1 << 0)
63 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf)
64 #define INT_LOAD_BSY (1 << 2)
65 #define INT_TRANS_ERR (1 << 1)
66 #define INT_TRANS_OVER (1 << 0)
67 #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER)
68 #define RSB_DADDR0 0x10
69 #define RSB_DADDR1 0x14
71 #define DLEN_READ (1 << 4)
72 #define RSB_DATA0 0x1c
73 #define RSB_DATA1 0x20
75 #define RSB_PMCR_START (1 << 31)
76 #define RSB_PMCR_DATA(x) (x << 16)
77 #define RSB_PMCR_REG(x) (x << 8)
87 #define DAR_RTA (0xff << 16)
88 #define DAR_RTA_SHIFT 16
89 #define DAR_DA (0xffff << 0)
90 #define DAR_DA_SHIFT 0
93 #define RSB_RESET_RETRY 100
94 #define RSB_I2C_TIMEOUT hz
96 #define RSB_ADDR_PMIC_PRIMARY 0x3a3
97 #define RSB_ADDR_PMIC_SECONDARY 0x745
98 #define RSB_ADDR_PERIPH_IC 0xe89
100 #define PMIC_MODE_REG 0x3e
101 #define PMIC_MODE_I2C 0x00
102 #define PMIC_MODE_RSB 0x7c
107 static struct ofw_compat_data compat_data[] = {
108 { "allwinner,sun6i-a31-p2wi", A31_P2WI },
109 { "allwinner,sun8i-a23-rsb", A23_RSB },
113 static struct resource_spec rsb_spec[] = {
114 { SYS_RES_MEMORY, 0, RF_ACTIVE },
119 * Device address to Run-time address mappings.
121 * Run-time address (RTA) is an 8-bit value used to address the device during
122 * a read or write transaction. The following are valid RTAs:
123 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff
125 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC,
126 * and 0x4e for the peripheral IC (where applicable).
128 static const struct {
132 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d },
133 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a },
134 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e },
135 { .addr = 0, .rta = 0 }
139 struct resource *res;
152 #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx)
153 #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
154 #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
155 #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg))
156 #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
159 rsb_get_node(device_t bus, device_t dev)
161 return (ofw_bus_get_node(bus));
165 rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
167 struct rsb_softc *sc;
170 sc = device_get_softc(dev);
174 /* Write soft-reset bit and wait for it to self-clear. */
175 RSB_WRITE(sc, RSB_CTRL, SOFT_RESET);
176 for (retry = RSB_RESET_RETRY; retry > 0; retry--)
177 if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0)
183 device_printf(dev, "soft reset timeout\n");
187 return (IIC_ENOADDR);
191 rsb_encode(const uint8_t *buf, u_int len, u_int off)
197 for (n = off; n < MIN(len, 4 + off); n++)
198 val |= ((uint32_t)buf[n] << ((n - off) * NBBY));
204 rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off)
208 for (n = off; n < MIN(len, 4 + off); n++)
209 buf[n] = (val >> ((n - off) * NBBY)) & 0xff;
213 rsb_start(device_t dev)
215 struct rsb_softc *sc;
218 sc = device_get_softc(dev);
220 RSB_ASSERT_LOCKED(sc);
222 /* Start the transfer */
223 RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS);
225 /* Wait for transfer to complete */
227 for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) {
228 sc->status |= RSB_READ(sc, RSB_INTS);
229 if ((sc->status & INT_TRANS_OVER) != 0) {
233 DELAY((1000 * hz) / RSB_I2C_TIMEOUT);
235 if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) {
236 device_printf(dev, "transfer error, status 0x%08x\n",
246 rsb_set_rta(device_t dev, uint16_t addr)
248 struct rsb_softc *sc;
252 sc = device_get_softc(dev);
254 RSB_ASSERT_LOCKED(sc);
256 /* Lookup run-time address for given device address */
257 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++)
258 if (rsb_rtamap[i].addr == addr) {
259 rta = rsb_rtamap[i].rta;
263 device_printf(dev, "RTA not known for address %#x\n", addr);
267 /* Set run-time address */
268 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
269 RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT));
270 RSB_WRITE(sc, RSB_CMD, CMD_SRTA);
272 return (rsb_start(dev));
276 rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
278 struct rsb_softc *sc;
279 uint32_t daddr[2], data[2], dlen;
280 uint16_t device_addr;
284 sc = device_get_softc(dev);
287 * P2WI and RSB are not really I2C or SMBus controllers, so there are
288 * some restrictions imposed by the driver.
290 * Transfers must contain exactly two messages. The first is always
291 * a write, containing a single data byte offset. Data will either
292 * be read from or written to the corresponding data byte in the
293 * second message. The slave address in both messages must be the
296 if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD ||
297 (msgs[0].slave >> 1) != (msgs[1].slave >> 1) ||
298 msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN)
301 /* The RSB controller can read or write 1, 2, or 4 bytes at a time. */
302 if (sc->type == A23_RSB) {
303 if ((msgs[1].flags & IIC_M_RD) != 0) {
304 switch (msgs[1].len) {
318 switch (msgs[1].len) {
336 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
340 /* Select current run-time address if necessary */
341 if (sc->type == A23_RSB) {
342 device_addr = msgs[0].slave >> 1;
343 if (sc->cur_addr != device_addr) {
344 error = rsb_set_rta(dev, device_addr);
347 sc->cur_addr = device_addr;
352 /* Clear interrupt status */
353 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
355 /* Program data access address registers */
356 daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0);
357 RSB_WRITE(sc, RSB_DADDR0, daddr[0]);
360 if ((msgs[1].flags & IIC_M_RD) == 0) {
361 data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0);
362 RSB_WRITE(sc, RSB_DATA0, data[0]);
365 /* Set command type for RSB */
366 if (sc->type == A23_RSB)
367 RSB_WRITE(sc, RSB_CMD, cmd);
369 /* Program data length register and transfer direction */
370 dlen = msgs[0].len - 1;
371 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD)
373 RSB_WRITE(sc, RSB_DLEN, dlen);
376 error = rsb_start(dev);
381 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) {
382 data[0] = RSB_READ(sc, RSB_DATA0);
383 rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0);
396 rsb_probe(device_t dev)
398 if (!ofw_bus_status_okay(dev))
401 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
403 device_set_desc(dev, "Allwinner RSB");
406 device_set_desc(dev, "Allwinner P2WI");
412 return (BUS_PROBE_DEFAULT);
416 rsb_attach(device_t dev)
418 struct rsb_softc *sc;
421 sc = device_get_softc(dev);
422 mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF);
424 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
426 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) {
427 error = clk_enable(sc->clk);
429 device_printf(dev, "cannot enable clock\n");
433 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) {
434 error = hwreset_deassert(sc->rst);
436 device_printf(dev, "cannot de-assert reset\n");
441 if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) {
442 device_printf(dev, "cannot allocate resources for device\n");
447 /* Set the PMIC into RSB mode as ATF might have leave it in I2C mode */
448 RSB_WRITE(sc, RSB_PMCR, RSB_PMCR_REG(PMIC_MODE_REG) | RSB_PMCR_DATA(PMIC_MODE_RSB) | RSB_PMCR_START);
450 sc->iicbus = device_add_child(dev, "iicbus", -1);
451 if (sc->iicbus == NULL) {
452 device_printf(dev, "cannot add iicbus child device\n");
457 bus_generic_attach(dev);
462 bus_release_resources(dev, rsb_spec, &sc->res);
464 hwreset_release(sc->rst);
466 clk_release(sc->clk);
467 mtx_destroy(&sc->mtx);
471 static device_method_t rsb_methods[] = {
472 /* Device interface */
473 DEVMETHOD(device_probe, rsb_probe),
474 DEVMETHOD(device_attach, rsb_attach),
477 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
478 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
479 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
480 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
481 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
482 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
483 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
484 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
485 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
488 DEVMETHOD(ofw_bus_get_node, rsb_get_node),
490 /* iicbus interface */
491 DEVMETHOD(iicbus_callback, iicbus_null_callback),
492 DEVMETHOD(iicbus_reset, rsb_reset),
493 DEVMETHOD(iicbus_transfer, rsb_transfer),
498 static driver_t rsb_driver = {
501 sizeof(struct rsb_softc),
504 static devclass_t rsb_devclass;
506 EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0,
507 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
508 EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0,
509 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
510 MODULE_VERSION(rsb, 1);
511 MODULE_DEPEND(rsb, iicbus, 1, 1, 1);
512 SIMPLEBUS_PNP_INFO(compat_data);