2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk.h>
50 #include "clkdev_if.h"
52 #define A10_APB0_CLK_RATIO (0x3 << 8)
53 #define A10_APB0_CLK_RATIO_SHIFT 8
54 #define A10_APB1_CLK_SRC_SEL (0x3 << 24)
55 #define A10_APB1_CLK_SRC_SEL_SHIFT 24
56 #define A10_APB1_CLK_SRC_SEL_MAX 0x3
57 #define A10_APB1_CLK_RAT_N (0x3 << 16)
58 #define A10_APB1_CLK_RAT_N_SHIFT 16
59 #define A10_APB1_CLK_RAT_M (0x1f << 0)
60 #define A10_APB1_CLK_RAT_M_SHIFT 0
61 #define A23_APB0_CLK_RATIO (0x3 << 0)
62 #define A23_APB0_CLK_RATIO_SHIFT 0
63 #define A83T_APB1_CLK_RATIO (0x3 << 8)
64 #define A83T_APB1_CLK_RATIO_SHIFT 8
73 static struct ofw_compat_data compat_data[] = {
74 { "allwinner,sun4i-a10-apb0-clk", AW_A10_APB0 },
75 { "allwinner,sun4i-a10-apb1-clk", AW_A10_APB1 },
76 { "allwinner,sun8i-a23-apb0-clk", AW_A23_APB0 },
77 { "allwinner,sun8i-a83t-apb1-clk", AW_A83T_APB1 },
84 enum aw_apbclk_type type;
87 #define APBCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
88 #define APBCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
89 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
90 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
93 aw_apbclk_init(struct clknode *clk, device_t dev)
95 struct aw_apbclk_sc *sc;
98 sc = clknode_get_softc(clk);
108 APBCLK_READ(sc, &val);
110 index = (val & A10_APB1_CLK_SRC_SEL) >>
111 A10_APB1_CLK_SRC_SEL_SHIFT;
117 clknode_init_parent_idx(clk, index);
122 aw_apbclk_recalc_freq(struct clknode *clk, uint64_t *freq)
124 struct aw_apbclk_sc *sc;
125 uint32_t val, div, m, n;
127 sc = clknode_get_softc(clk);
130 APBCLK_READ(sc, &val);
135 div = 1 << ((val & A10_APB0_CLK_RATIO) >>
136 A10_APB0_CLK_RATIO_SHIFT);
142 n = 1 << ((val & A10_APB1_CLK_RAT_N) >>
143 A10_APB1_CLK_RAT_N_SHIFT);
144 m = ((val & A10_APB1_CLK_RAT_N) >>
145 A10_APB1_CLK_RAT_M_SHIFT) + 1;
146 *freq = *freq / n / m;
149 div = 1 << ((val & A23_APB0_CLK_RATIO) >>
150 A23_APB0_CLK_RATIO_SHIFT);
154 div = ((val & A83T_APB1_CLK_RATIO) >>
155 A83T_APB1_CLK_RATIO_SHIFT) + 1;
166 aw_apbclk_set_mux(struct clknode *clk, int index)
168 struct aw_apbclk_sc *sc;
171 sc = clknode_get_softc(clk);
173 if (sc->type != AW_A10_APB1)
176 if (index < 0 || index > A10_APB1_CLK_SRC_SEL_MAX)
180 APBCLK_READ(sc, &val);
181 val &= ~A10_APB1_CLK_SRC_SEL;
182 val |= (index << A10_APB1_CLK_SRC_SEL_SHIFT);
183 APBCLK_WRITE(sc, val);
189 static clknode_method_t aw_apbclk_clknode_methods[] = {
190 /* Device interface */
191 CLKNODEMETHOD(clknode_init, aw_apbclk_init),
192 CLKNODEMETHOD(clknode_recalc_freq, aw_apbclk_recalc_freq),
193 CLKNODEMETHOD(clknode_set_mux, aw_apbclk_set_mux),
196 DEFINE_CLASS_1(aw_apbclk_clknode, aw_apbclk_clknode_class,
197 aw_apbclk_clknode_methods, sizeof(struct aw_apbclk_sc), clknode_class);
200 aw_apbclk_probe(device_t dev)
202 if (!ofw_bus_status_okay(dev))
205 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
208 device_set_desc(dev, "Allwinner APB Clock");
209 return (BUS_PROBE_DEFAULT);
213 aw_apbclk_attach(device_t dev)
215 struct clknode_init_def def;
216 struct aw_apbclk_sc *sc;
217 struct clkdom *clkdom;
223 int error, ncells, i;
225 node = ofw_bus_get_node(dev);
227 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
228 device_printf(dev, "cannot parse 'reg' property\n");
232 error = ofw_bus_parse_xref_list_get_length(node, "clocks",
233 "#clock-cells", &ncells);
235 device_printf(dev, "cannot get clock count\n");
239 clkdom = clkdom_create(dev);
241 memset(&def, 0, sizeof(def));
242 error = clk_parse_ofw_clk_name(dev, node, &def.name);
244 device_printf(dev, "cannot parse clock name\n");
249 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
250 for (i = 0; i < ncells; i++) {
251 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
253 device_printf(dev, "cannot get clock %d\n", i);
256 def.parent_names[i] = clk_get_name(clk_parent);
257 clk_release(clk_parent);
259 def.parent_cnt = ncells;
261 clk = clknode_create(clkdom, &aw_apbclk_clknode_class, &def);
263 device_printf(dev, "cannot create clknode\n");
268 sc = clknode_get_softc(clk);
269 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
271 sc->clkdev = device_get_parent(dev);
273 clknode_register(clkdom, clk);
275 if (clkdom_finit(clkdom) != 0) {
276 device_printf(dev, "cannot finalize clkdom initialization\n");
290 static device_method_t aw_apbclk_methods[] = {
291 /* Device interface */
292 DEVMETHOD(device_probe, aw_apbclk_probe),
293 DEVMETHOD(device_attach, aw_apbclk_attach),
298 static driver_t aw_apbclk_driver = {
304 static devclass_t aw_apbclk_devclass;
306 EARLY_DRIVER_MODULE(aw_apbclk, simplebus, aw_apbclk_driver,
307 aw_apbclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);