2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner LCD clocks
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk.h>
49 #include <dev/extres/hwreset/hwreset.h>
51 #include "clkdev_if.h"
52 #include "hwreset_if.h"
55 #define CH0_SCLK_GATING (1 << 31)
56 #define CH0_LCD_RST (1 << 30)
57 #define CH0_CLK_SRC_SEL (0x3 << 24)
58 #define CH0_CLK_SRC_SEL_SHIFT 24
59 #define CH0_CLK_SRC_SEL_PLL3_1X 0
60 #define CH0_CLK_SRC_SEL_PLL7_1X 1
61 #define CH0_CLK_SRC_SEL_PLL3_2X 2
62 #define CH0_CLK_SRC_SEL_PLL6 3
65 #define CH1_SCLK2_GATING (1 << 31)
66 #define CH1_SCLK2_SEL (0x3 << 24)
67 #define CH1_SCLK2_SEL_SHIFT 24
68 #define CH1_SCLK2_SEL_PLL3_1X 0
69 #define CH1_SCLK2_SEL_PLL7_1X 1
70 #define CH1_SCLK2_SEL_PLL3_2X 2
71 #define CH1_SCLK2_SEL_PLL7_2X 3
72 #define CH1_SCLK1_GATING (1 << 15)
73 #define CH1_SCLK1_SEL (0x1 << 11)
74 #define CH1_SCLK1_SEL_SHIFT 11
75 #define CH1_SCLK1_SEL_SCLK2 0
76 #define CH1_SCLK1_SEL_SCLK2_DIV2 1
77 #define CH1_CLK_DIV_RATIO_M (0x1f << 0)
78 #define CH1_CLK_DIV_RATIO_M_SHIFT 0
80 #define TCON_PLLREF 3000000ULL
81 #define TCON_PLLREF_FRAC1 297000000ULL
82 #define TCON_PLLREF_FRAC2 270000000ULL
83 #define TCON_PLL_M_MIN 1
84 #define TCON_PLL_M_MAX 15
85 #define TCON_PLL_N_MIN 9
86 #define TCON_PLL_N_MAX 127
88 #define CLK_IDX_CH1_SCLK1 0
89 #define CLK_IDX_CH1_SCLK2 1
98 static struct ofw_compat_data compat_data[] = {
99 { "allwinner,sun4i-a10-lcd-ch0-clk", AW_LCD_CH0 },
100 { "allwinner,sun4i-a10-lcd-ch1-clk", AW_LCD_CH1 },
104 struct aw_lcdclk_softc {
105 enum aw_lcdclk_type type;
111 #define LCDCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
112 #define LCDCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
113 #define LCDCLK_MODIFY(sc, clr, set) \
114 CLKDEV_MODIFY_4((sc)->clkdev, (sc)->reg, (clr), (set))
115 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
116 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
119 aw_lcdclk_hwreset_assert(device_t dev, intptr_t id, bool value)
121 struct aw_lcdclk_softc *sc;
124 sc = device_get_softc(dev);
126 if (sc->type != AW_LCD_CH0)
130 error = LCDCLK_MODIFY(sc, CH0_LCD_RST, value ? 0 : CH0_LCD_RST);
137 aw_lcdclk_hwreset_is_asserted(device_t dev, intptr_t id, bool *value)
139 struct aw_lcdclk_softc *sc;
143 sc = device_get_softc(dev);
145 if (sc->type != AW_LCD_CH0)
149 error = LCDCLK_READ(sc, &val);
155 *value = (val & CH0_LCD_RST) != 0 ? false : true;
161 aw_lcdclk_init(struct clknode *clk, device_t dev)
163 struct aw_lcdclk_softc *sc;
166 sc = clknode_get_softc(clk);
169 LCDCLK_READ(sc, &val);
174 index = (val & CH0_CLK_SRC_SEL) >> CH0_CLK_SRC_SEL_SHIFT;
178 case CLK_IDX_CH1_SCLK1:
181 case CLK_IDX_CH1_SCLK2:
182 index = (val & CH1_SCLK2_SEL_SHIFT) >>
193 clknode_init_parent_idx(clk, index);
198 aw_lcdclk_set_mux(struct clknode *clk, int index)
200 struct aw_lcdclk_softc *sc;
203 sc = clknode_get_softc(clk);
208 LCDCLK_READ(sc, &val);
209 val &= ~CH0_CLK_SRC_SEL;
210 val |= (index << CH0_CLK_SRC_SEL_SHIFT);
211 LCDCLK_WRITE(sc, val);
216 case CLK_IDX_CH1_SCLK2:
218 LCDCLK_READ(sc, &val);
219 val &= ~CH1_SCLK2_SEL;
220 val |= (index << CH1_SCLK2_SEL_SHIFT);
221 LCDCLK_WRITE(sc, val);
236 aw_lcdclk_set_gate(struct clknode *clk, bool enable)
238 struct aw_lcdclk_softc *sc;
241 sc = clknode_get_softc(clk);
245 mask = CH0_SCLK_GATING;
248 mask = (sc->id == CLK_IDX_CH1_SCLK1) ? CH1_SCLK1_GATING :
256 LCDCLK_READ(sc, &val);
261 LCDCLK_WRITE(sc, val);
268 aw_lcdclk_recalc_freq(struct clknode *clk, uint64_t *freq)
270 struct aw_lcdclk_softc *sc;
271 uint32_t val, m, src_sel;
273 sc = clknode_get_softc(clk);
275 if (sc->type != AW_LCD_CH1)
279 LCDCLK_READ(sc, &val);
282 m = ((val & CH1_CLK_DIV_RATIO_M) >> CH1_CLK_DIV_RATIO_M_SHIFT) + 1;
285 if (sc->id == CLK_IDX_CH1_SCLK1) {
286 src_sel = (val & CH1_SCLK1_SEL) >> CH1_SCLK1_SEL_SHIFT;
287 if (src_sel == CH1_SCLK1_SEL_SCLK2_DIV2)
295 calc_tcon_pll_integer(uint64_t fin, uint64_t fout, uint32_t *pm, uint32_t *pn)
297 int64_t diff, fcur, best;
301 for (m = TCON_PLL_M_MIN; m <= TCON_PLL_M_MAX; m++) {
302 for (n = TCON_PLL_N_MIN; n <= TCON_PLL_N_MAX; n++) {
303 fcur = (n * fin) / m;
304 diff = (int64_t)fout - fcur;
305 if (diff > 0 && diff < best) {
315 calc_tcon_pll_fractional(uint64_t fin, uint64_t fout, int *clk_div)
319 /* Test for 1X match */
320 for (m = TCON_PLL_M_MIN; m <= TCON_PLL_M_MAX; m++) {
321 if (fout == (fin / m)) {
323 return (CH0_CLK_SRC_SEL_PLL3_1X);
327 /* Test for 2X match */
328 for (m = TCON_PLL_M_MIN; m <= TCON_PLL_M_MAX; m++) {
329 if (fout == ((fin * 2) / m)) {
331 return (CH0_CLK_SRC_SEL_PLL3_2X);
339 calc_tcon_pll(uint64_t fin, uint64_t fout, uint64_t *pll_freq, int *tcon_pll_div)
341 uint32_t m, m2, n, n2;
342 uint64_t fsingle, fdouble;
346 /* Test fractional freq first */
347 src_sel = calc_tcon_pll_fractional(TCON_PLLREF_FRAC1, fout,
350 *pll_freq = TCON_PLLREF_FRAC1;
353 src_sel = calc_tcon_pll_fractional(TCON_PLLREF_FRAC2, fout,
356 *pll_freq = TCON_PLLREF_FRAC2;
363 /* Find the frequency closes to the target dot clock, using
364 * both 1X and 2X PLL inputs as possible candidates.
366 calc_tcon_pll_integer(TCON_PLLREF, fout, &m, &n);
367 calc_tcon_pll_integer(TCON_PLLREF * 2, fout, &m2, &n2);
369 fsingle = m ? (n * TCON_PLLREF) / m : 0;
370 fdouble = m2 ? (n2 * TCON_PLLREF * 2) / m2 : 0;
372 if (fdouble > fsingle) {
378 /* Set desired parent frequency */
379 *pll_freq = n * TCON_PLLREF;
382 /* Return the desired source clock */
383 return (dbl ? CH0_CLK_SRC_SEL_PLL3_2X :
384 CH0_CLK_SRC_SEL_PLL3_1X);
388 aw_lcdclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
389 int flags, int *stop)
391 struct aw_lcdclk_softc *sc;
392 struct clknode *parent_clk;
393 const char **parent_names;
395 uint32_t val, src_sel;
396 int error, tcon_pll_div;
398 sc = clknode_get_softc(clk);
400 if (sc->type == AW_LCD_CH0) {
405 if (sc->id != CLK_IDX_CH1_SCLK2)
408 src_sel = calc_tcon_pll(fin, *fout, &pll_freq, &tcon_pll_div);
410 parent_names = clknode_get_parent_names(clk);
411 parent_clk = clknode_find_by_name(parent_names[src_sel]);
413 if (parent_clk == NULL)
416 /* Fetch input frequency */
417 error = clknode_get_freq(parent_clk, &pll_freq);
421 *fout = pll_freq / tcon_pll_div;
424 if ((flags & CLK_SET_DRYRUN) != 0)
427 /* Switch parent clock if necessary */
428 error = clknode_set_parent_by_idx(clk, src_sel);
432 error = clknode_set_freq(parent_clk, pll_freq,
437 /* Fetch new input frequency */
438 error = clknode_get_freq(parent_clk, &pll_freq);
442 *fout = pll_freq / tcon_pll_div;
444 error = clknode_enable(parent_clk);
448 /* Set LCD divisor */
450 LCDCLK_READ(sc, &val);
451 val &= ~CH1_CLK_DIV_RATIO_M;
452 val |= ((tcon_pll_div - 1) << CH1_CLK_DIV_RATIO_M_SHIFT);
453 LCDCLK_WRITE(sc, val);
459 static clknode_method_t aw_lcdclk_clknode_methods[] = {
460 /* Device interface */
461 CLKNODEMETHOD(clknode_init, aw_lcdclk_init),
462 CLKNODEMETHOD(clknode_set_gate, aw_lcdclk_set_gate),
463 CLKNODEMETHOD(clknode_set_mux, aw_lcdclk_set_mux),
464 CLKNODEMETHOD(clknode_recalc_freq, aw_lcdclk_recalc_freq),
465 CLKNODEMETHOD(clknode_set_freq, aw_lcdclk_set_freq),
468 DEFINE_CLASS_1(aw_lcdclk_clknode, aw_lcdclk_clknode_class,
469 aw_lcdclk_clknode_methods, sizeof(struct aw_lcdclk_softc), clknode_class);
472 aw_lcdclk_create(device_t dev, struct clkdom *clkdom,
473 const char **parent_names, int parent_cnt, const char *name, int index)
475 struct aw_lcdclk_softc *sc, *clk_sc;
476 struct clknode_init_def def;
480 sc = device_get_softc(dev);
481 node = ofw_bus_get_node(dev);
483 memset(&def, 0, sizeof(def));
486 def.parent_names = parent_names;
487 def.parent_cnt = parent_cnt;
489 clk = clknode_create(clkdom, &aw_lcdclk_clknode_class, &def);
491 device_printf(dev, "cannot create clknode\n");
495 clk_sc = clknode_get_softc(clk);
496 clk_sc->type = sc->type;
497 clk_sc->reg = sc->reg;
498 clk_sc->clkdev = sc->clkdev;
501 clknode_register(clkdom, clk);
507 aw_lcdclk_probe(device_t dev)
509 enum aw_lcdclk_type type;
511 if (!ofw_bus_status_okay(dev))
514 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
517 device_set_desc(dev, "Allwinner LCD CH0 Clock");
520 device_set_desc(dev, "Allwinner LCD CH1 Clock");
526 return (BUS_PROBE_DEFAULT);
530 aw_lcdclk_attach(device_t dev)
532 struct aw_lcdclk_softc *sc;
533 struct clkdom *clkdom;
538 const char **parent_names;
540 int error, ncells, nout, i;
542 sc = device_get_softc(dev);
543 sc->clkdev = device_get_parent(dev);
544 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
546 node = ofw_bus_get_node(dev);
548 if (ofw_reg_to_paddr(node, 0, &sc->reg, &psize, NULL) != 0) {
549 device_printf(dev, "cannot parse 'reg' property\n");
553 error = ofw_bus_parse_xref_list_get_length(node, "clocks",
554 "#clock-cells", &ncells);
556 device_printf(dev, "cannot get clock count\n");
560 parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
561 for (i = 0; i < ncells; i++) {
562 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
564 device_printf(dev, "cannot get clock %d\n", i);
567 parent_names[i] = clk_get_name(clk_parent);
568 clk_release(clk_parent);
571 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
573 device_printf(dev, "no clock outputs found\n");
577 clkdom = clkdom_create(dev);
579 for (i = 0; i < nout; i++) {
580 error = aw_lcdclk_create(dev, clkdom, parent_names, ncells,
581 names[i], nout == 1 ? 1 : i);
586 if (clkdom_finit(clkdom) != 0) {
587 device_printf(dev, "cannot finalize clkdom initialization\n");
595 if (sc->type == AW_LCD_CH0)
596 hwreset_register_ofw_provider(dev);
598 OF_prop_free(parent_names);
602 OF_prop_free(parent_names);
606 static device_method_t aw_lcdclk_methods[] = {
607 /* Device interface */
608 DEVMETHOD(device_probe, aw_lcdclk_probe),
609 DEVMETHOD(device_attach, aw_lcdclk_attach),
611 /* Reset interface */
612 DEVMETHOD(hwreset_assert, aw_lcdclk_hwreset_assert),
613 DEVMETHOD(hwreset_is_asserted, aw_lcdclk_hwreset_is_asserted),
618 static driver_t aw_lcdclk_driver = {
621 sizeof(struct aw_lcdclk_softc)
624 static devclass_t aw_lcdclk_devclass;
626 EARLY_DRIVER_MODULE(aw_lcdclk, simplebus, aw_lcdclk_driver,
627 aw_lcdclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);