2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner MMC clocks
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk_mux.h>
49 #include <dev/extres/clk/clk_gate.h>
51 #include "clkdev_if.h"
53 #define SCLK_GATING (1 << 31)
54 #define CLK_SRC_SEL (0x3 << 24)
55 #define CLK_SRC_SEL_SHIFT 24
56 #define CLK_SRC_SEL_MAX 0x3
57 #define CLK_SRC_SEL_OSC24M 0
58 #define CLK_SRC_SEL_PLL6 1
59 #define CLK_PHASE_CTR (0x7 << 20)
60 #define CLK_PHASE_CTR_SHIFT 20
61 #define CLK_RATIO_N (0x3 << 16)
62 #define CLK_RATIO_N_SHIFT 16
63 #define CLK_RATIO_N_MAX 0x3
64 #define OUTPUT_CLK_PHASE_CTR (0x7 << 8)
65 #define OUTPUT_CLK_PHASE_CTR_SHIFT 8
66 #define CLK_RATIO_M (0xf << 0)
67 #define CLK_RATIO_M_SHIFT 0
68 #define CLK_RATIO_M_MAX 0xf
70 static struct ofw_compat_data compat_data[] = {
71 { "allwinner,sun4i-a10-mmc-clk", 1 },
88 static struct phase_clk aw_mmcclk_phase[] = {
89 {400000, CLK_SRC_SEL_OSC24M, 0, 0, 2},
90 {25000000, CLK_SRC_SEL_PLL6, 0, 5, 2},
91 {52000000, CLK_SRC_SEL_PLL6, 3, 5, 0},
94 #define MODCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
95 #define MODCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
96 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
97 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
100 aw_mmcclk_init(struct clknode *clk, device_t dev)
102 struct aw_mmcclk_sc *sc;
105 sc = clknode_get_softc(clk);
108 MODCLK_READ(sc, &val);
111 index = (val & CLK_SRC_SEL) >> CLK_SRC_SEL_SHIFT;
113 clknode_init_parent_idx(clk, index);
118 aw_mmcclk_set_mux(struct clknode *clk, int index)
120 struct aw_mmcclk_sc *sc;
123 sc = clknode_get_softc(clk);
125 if (index < 0 || index > CLK_SRC_SEL_MAX)
129 MODCLK_READ(sc, &val);
131 val |= (index << CLK_SRC_SEL_SHIFT);
132 MODCLK_WRITE(sc, val);
139 aw_mmcclk_set_gate(struct clknode *clk, bool enable)
141 struct aw_mmcclk_sc *sc;
144 sc = clknode_get_softc(clk);
147 MODCLK_READ(sc, &val);
152 MODCLK_WRITE(sc, val);
159 aw_mmcclk_recalc_freq(struct clknode *clk, uint64_t *freq)
161 struct aw_mmcclk_sc *sc;
164 sc = clknode_get_softc(clk);
167 MODCLK_READ(sc, &val);
170 n = 1 << ((val & CLK_RATIO_N) >> CLK_RATIO_N_SHIFT);
171 m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1;
173 *freq = *freq / n / m;
179 aw_mmcclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
180 int flags, int *stop)
182 struct aw_mmcclk_sc *sc;
183 struct clknode *parent_clk;
184 const char **parent_names;
186 int parent_idx, error, phase;
188 sc = clknode_get_softc(clk);
191 * The ophase/phase values should be set by the MMC driver, but
192 * there is currently no way to do this with the clk API
194 for (phase = 0; phase < nitems(aw_mmcclk_phase); phase++) {
195 if (*fout <= aw_mmcclk_phase[phase].freq)
199 if (phase == nitems(aw_mmcclk_phase))
202 parent_names = clknode_get_parent_names(clk);
203 parent_idx = aw_mmcclk_phase[phase].parent_idx;
204 parent_clk = clknode_find_by_name(parent_names[parent_idx]);
206 if (parent_clk == NULL)
209 error = clknode_get_freq(parent_clk, &fin);
213 m = ((fin / (1 << aw_mmcclk_phase[phase].n)) / *fout) - 1;
215 *fout = fin / (1 << aw_mmcclk_phase[phase].n) / (m + 1);
218 if ((flags & CLK_SET_DRYRUN) != 0)
221 /* Switch to the correct parent if needed */
222 error = clknode_set_parent_by_idx(clk, parent_idx);
227 MODCLK_READ(sc, &val);
228 val &= ~(CLK_RATIO_N | CLK_RATIO_M | CLK_PHASE_CTR |
229 OUTPUT_CLK_PHASE_CTR);
230 val |= (aw_mmcclk_phase[phase].n << CLK_RATIO_N_SHIFT);
231 val |= (m << CLK_RATIO_M_SHIFT);
232 val |= (aw_mmcclk_phase[phase].phase << CLK_PHASE_CTR_SHIFT);
233 val |= (aw_mmcclk_phase[phase].ophase << OUTPUT_CLK_PHASE_CTR_SHIFT);
234 MODCLK_WRITE(sc, val);
240 static clknode_method_t aw_mmcclk_clknode_methods[] = {
241 /* Device interface */
242 CLKNODEMETHOD(clknode_init, aw_mmcclk_init),
243 CLKNODEMETHOD(clknode_set_gate, aw_mmcclk_set_gate),
244 CLKNODEMETHOD(clknode_set_mux, aw_mmcclk_set_mux),
245 CLKNODEMETHOD(clknode_recalc_freq, aw_mmcclk_recalc_freq),
246 CLKNODEMETHOD(clknode_set_freq, aw_mmcclk_set_freq),
249 DEFINE_CLASS_1(aw_mmcclk_clknode, aw_mmcclk_clknode_class,
250 aw_mmcclk_clknode_methods, sizeof(struct aw_mmcclk_sc), clknode_class);
253 aw_mmcclk_probe(device_t dev)
255 if (!ofw_bus_status_okay(dev))
258 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
261 device_set_desc(dev, "Allwinner MMC Clock");
262 return (BUS_PROBE_DEFAULT);
266 aw_mmcclk_attach(device_t dev)
268 struct clknode_init_def def;
269 struct aw_mmcclk_sc *sc;
270 struct clkdom *clkdom;
278 int error, nout, ncells, i;
280 node = ofw_bus_get_node(dev);
282 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
283 device_printf(dev, "cannot parse 'reg' property\n");
287 error = ofw_bus_parse_xref_list_get_length(node, "clocks",
288 "#clock-cells", &ncells);
289 if (error != 0 || ncells == 0) {
290 device_printf(dev, "couldn't find parent clocks\n");
294 clkdom = clkdom_create(dev);
296 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
298 device_printf(dev, "no output clocks found\n");
303 memset(&def, 0, sizeof(def));
306 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
307 for (i = 0; i < ncells; i++) {
308 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
310 device_printf(dev, "cannot get clock %d\n", i);
313 def.parent_names[i] = clk_get_name(clk_parent);
314 clk_release(clk_parent);
316 def.parent_cnt = ncells;
317 def.flags = CLK_NODE_GLITCH_FREE;
319 clk = clknode_create(clkdom, &aw_mmcclk_clknode_class, &def);
321 device_printf(dev, "cannot create clknode\n");
326 sc = clknode_get_softc(clk);
328 sc->clkdev = device_get_parent(dev);
330 clknode_register(clkdom, clk);
332 if (clkdom_finit(clkdom) != 0) {
333 device_printf(dev, "cannot finalize clkdom initialization\n");
347 static device_method_t aw_mmcclk_methods[] = {
348 /* Device interface */
349 DEVMETHOD(device_probe, aw_mmcclk_probe),
350 DEVMETHOD(device_attach, aw_mmcclk_attach),
355 static driver_t aw_mmcclk_driver = {
361 static devclass_t aw_mmcclk_devclass;
363 EARLY_DRIVER_MODULE(aw_mmcclk, simplebus, aw_mmcclk_driver,
364 aw_mmcclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);