2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner module clocks
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk_mux.h>
49 #include <dev/extres/clk/clk_gate.h>
51 #include "clkdev_if.h"
53 #define SCLK_GATING (1 << 31)
54 #define CLK_SRC_SEL (0x3 << 24)
55 #define CLK_SRC_SEL_SHIFT 24
56 #define CLK_RATIO_N (0x3 << 16)
57 #define CLK_RATIO_N_SHIFT 16
58 #define CLK_RATIO_N_MAX 0x3
59 #define CLK_RATIO_M (0xf << 0)
60 #define CLK_RATIO_M_SHIFT 0
61 #define CLK_RATIO_M_MAX 0xf
63 static struct ofw_compat_data compat_data[] = {
64 { "allwinner,sun4i-a10-mod0-clk", 1 },
73 #define MODCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
74 #define MODCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
75 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
76 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
79 aw_modclk_init(struct clknode *clk, device_t dev)
81 struct aw_modclk_sc *sc;
84 sc = clknode_get_softc(clk);
87 MODCLK_READ(sc, &val);
90 index = (val & CLK_SRC_SEL) >> CLK_SRC_SEL_SHIFT;
92 clknode_init_parent_idx(clk, index);
97 aw_modclk_set_mux(struct clknode *clk, int index)
99 struct aw_modclk_sc *sc;
102 sc = clknode_get_softc(clk);
104 if (index < 0 || index >= clknode_get_parents_num(clk))
108 MODCLK_READ(sc, &val);
110 val |= (index << CLK_SRC_SEL_SHIFT);
111 MODCLK_WRITE(sc, val);
118 aw_modclk_set_gate(struct clknode *clk, bool enable)
120 struct aw_modclk_sc *sc;
123 sc = clknode_get_softc(clk);
126 MODCLK_READ(sc, &val);
131 MODCLK_WRITE(sc, val);
138 aw_modclk_recalc_freq(struct clknode *clk, uint64_t *freq)
140 struct aw_modclk_sc *sc;
143 sc = clknode_get_softc(clk);
146 MODCLK_READ(sc, &val);
149 n = 1 << ((val & CLK_RATIO_N) >> CLK_RATIO_N_SHIFT);
150 m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1;
152 *freq = *freq / n / m;
158 aw_modclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
159 int flags, int *stop)
161 struct aw_modclk_sc *sc;
162 struct clknode *parent_clk, *best_parent;
163 const char **parent_names;
164 uint32_t val, m, n, src, best_m, best_n, best_src;
166 int64_t best_diff, cur_diff;
169 sc = clknode_get_softc(clk);
171 best_diff = (int64_t)*fout;
174 parent_names = clknode_get_parent_names(clk);
175 for (src = 0; src < clknode_get_parents_num(clk); src++) {
176 parent_clk = clknode_find_by_name(parent_names[src]);
177 if (parent_clk == NULL)
179 error = clknode_get_freq(parent_clk, &fin);
183 for (n = 0; n <= CLK_RATIO_N_MAX; n++)
184 for (m = 0; m <= CLK_RATIO_M_MAX; m++) {
185 cur_freq = fin / (1 << n) / (m + 1);
186 cur_diff = (int64_t)*fout - cur_freq;
187 if (cur_diff >= 0 && cur_diff < best_diff) {
189 best_parent = parent_clk;
190 best_diff = cur_diff;
197 if (best_diff == (int64_t)*fout)
200 error = clknode_get_freq(best_parent, &fin);
204 *fout = fin / (1 << best_n) / (best_m + 1);
207 if ((flags & CLK_SET_DRYRUN) != 0)
210 error = clknode_set_parent_by_idx(clk, best_src);
215 MODCLK_READ(sc, &val);
216 val &= ~(CLK_RATIO_N | CLK_RATIO_M);
217 val |= (best_n << CLK_RATIO_N_SHIFT);
218 val |= (best_m << CLK_RATIO_M_SHIFT);
219 MODCLK_WRITE(sc, val);
225 static clknode_method_t aw_modclk_clknode_methods[] = {
226 /* Device interface */
227 CLKNODEMETHOD(clknode_init, aw_modclk_init),
228 CLKNODEMETHOD(clknode_set_gate, aw_modclk_set_gate),
229 CLKNODEMETHOD(clknode_set_mux, aw_modclk_set_mux),
230 CLKNODEMETHOD(clknode_recalc_freq, aw_modclk_recalc_freq),
231 CLKNODEMETHOD(clknode_set_freq, aw_modclk_set_freq),
234 DEFINE_CLASS_1(aw_modclk_clknode, aw_modclk_clknode_class,
235 aw_modclk_clknode_methods, sizeof(struct aw_modclk_sc), clknode_class);
238 aw_modclk_probe(device_t dev)
240 if (!ofw_bus_status_okay(dev))
243 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
246 device_set_desc(dev, "Allwinner Module Clock");
247 return (BUS_PROBE_DEFAULT);
251 aw_modclk_attach(device_t dev)
253 struct clknode_init_def def;
254 struct aw_modclk_sc *sc;
255 struct clkdom *clkdom;
261 int error, ncells, i;
263 node = ofw_bus_get_node(dev);
265 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
266 device_printf(dev, "cannot parse 'reg' property\n");
270 error = ofw_bus_parse_xref_list_get_length(node, "clocks",
271 "#clock-cells", &ncells);
273 device_printf(dev, "cannot get clock count\n");
277 clkdom = clkdom_create(dev);
279 memset(&def, 0, sizeof(def));
280 error = clk_parse_ofw_clk_name(dev, node, &def.name);
282 device_printf(dev, "cannot parse clock name\n");
287 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
288 for (i = 0; i < ncells; i++) {
289 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
291 device_printf(dev, "cannot get clock %d\n", i);
294 def.parent_names[i] = clk_get_name(clk_parent);
295 clk_release(clk_parent);
297 def.parent_cnt = ncells;
299 clk = clknode_create(clkdom, &aw_modclk_clknode_class, &def);
301 device_printf(dev, "cannot create clknode\n");
306 sc = clknode_get_softc(clk);
308 sc->clkdev = device_get_parent(dev);
310 clknode_register(clkdom, clk);
312 if (clkdom_finit(clkdom) != 0) {
313 device_printf(dev, "cannot finalize clkdom initialization\n");
327 static device_method_t aw_modclk_methods[] = {
328 /* Device interface */
329 DEVMETHOD(device_probe, aw_modclk_probe),
330 DEVMETHOD(device_attach, aw_modclk_attach),
335 static driver_t aw_modclk_driver = {
341 static devclass_t aw_modclk_devclass;
343 EARLY_DRIVER_MODULE(aw_modclk, simplebus, aw_modclk_driver,
344 aw_modclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);