2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk.h>
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
52 #include <arm/allwinner/allwinner_machdep.h>
54 #include "clkdev_if.h"
56 #define AW_PLL_ENABLE (1 << 31)
58 #define A10_PLL1_OUT_EXT_DIVP (0x3 << 16)
59 #define A10_PLL1_OUT_EXT_DIVP_SHIFT 16
60 #define A10_PLL1_FACTOR_N (0x1f << 8)
61 #define A10_PLL1_FACTOR_N_SHIFT 8
62 #define A10_PLL1_FACTOR_K (0x3 << 4)
63 #define A10_PLL1_FACTOR_K_SHIFT 4
64 #define A10_PLL1_FACTOR_M (0x3 << 0)
65 #define A10_PLL1_FACTOR_M_SHIFT 0
67 #define A10_PLL2_POST_DIV (0xf << 26)
68 #define A10_PLL2_POST_DIV_SHIFT 26
69 #define A10_PLL2_FACTOR_N (0x7f << 8)
70 #define A10_PLL2_FACTOR_N_SHIFT 8
71 #define A10_PLL2_PRE_DIV (0x1f << 0)
72 #define A10_PLL2_PRE_DIV_SHIFT 0
74 #define A10_PLL3_MODE_SEL (0x1 << 15)
75 #define A10_PLL3_MODE_SEL_FRACT (0 << 15)
76 #define A10_PLL3_MODE_SEL_INT (1 << 15)
77 #define A10_PLL3_FUNC_SET (0x1 << 14)
78 #define A10_PLL3_FUNC_SET_270MHZ (0 << 14)
79 #define A10_PLL3_FUNC_SET_297MHZ (1 << 14)
80 #define A10_PLL3_FACTOR_M (0x7f << 0)
81 #define A10_PLL3_FACTOR_M_SHIFT 0
82 #define A10_PLL3_REF_FREQ 3000000
84 #define A10_PLL5_OUT_EXT_DIVP (0x3 << 16)
85 #define A10_PLL5_OUT_EXT_DIVP_SHIFT 16
86 #define A10_PLL5_FACTOR_N (0x1f << 8)
87 #define A10_PLL5_FACTOR_N_SHIFT 8
88 #define A10_PLL5_FACTOR_K (0x3 << 4)
89 #define A10_PLL5_FACTOR_K_SHIFT 4
90 #define A10_PLL5_FACTOR_M1 (0x3 << 2)
91 #define A10_PLL5_FACTOR_M1_SHIFT 2
92 #define A10_PLL5_FACTOR_M (0x3 << 0)
93 #define A10_PLL5_FACTOR_M_SHIFT 0
95 #define A10_PLL6_BYPASS_EN (1 << 30)
96 #define A10_PLL6_SATA_CLK_EN (1 << 14)
97 #define A10_PLL6_FACTOR_N (0x1f << 8)
98 #define A10_PLL6_FACTOR_N_SHIFT 8
99 #define A10_PLL6_FACTOR_K (0x3 << 4)
100 #define A10_PLL6_FACTOR_K_SHIFT 4
101 #define A10_PLL6_FACTOR_M (0x3 << 0)
102 #define A10_PLL6_FACTOR_M_SHIFT 0
104 #define A10_PLL2_POST_DIV (0xf << 26)
106 #define A13_PLL2_POST_DIV (0xf << 26)
107 #define A13_PLL2_POST_DIV_SHIFT 26
108 #define A13_PLL2_FACTOR_N (0x7f << 8)
109 #define A13_PLL2_FACTOR_N_SHIFT 8
110 #define A13_PLL2_PRE_DIV (0x1f << 0)
111 #define A13_PLL2_PRE_DIV_SHIFT 0
113 #define A23_PLL1_FACTOR_N (0x1f << 8)
114 #define A23_PLL1_FACTOR_N_SHIFT 8
115 #define A23_PLL1_FACTOR_K (0x3 << 4)
116 #define A23_PLL1_FACTOR_K_SHIFT 4
117 #define A23_PLL1_FACTOR_M (0x3 << 0)
118 #define A23_PLL1_FACTOR_M_SHIFT 0
119 #define A23_PLL1_FACTOR_P (0x3 << 16)
120 #define A23_PLL1_FACTOR_P_SHIFT 16
122 #define A31_PLL1_LOCK (1 << 28)
123 #define A31_PLL1_CPU_SIGMA_DELTA_EN (1 << 24)
124 #define A31_PLL1_FACTOR_N (0x1f << 8)
125 #define A31_PLL1_FACTOR_N_SHIFT 8
126 #define A31_PLL1_FACTOR_K (0x3 << 4)
127 #define A31_PLL1_FACTOR_K_SHIFT 4
128 #define A31_PLL1_FACTOR_M (0x3 << 0)
129 #define A31_PLL1_FACTOR_M_SHIFT 0
131 #define A31_PLL6_LOCK (1 << 28)
132 #define A31_PLL6_BYPASS_EN (1 << 25)
133 #define A31_PLL6_CLK_OUT_EN (1 << 24)
134 #define A31_PLL6_24M_OUT_EN (1 << 18)
135 #define A31_PLL6_24M_POST_DIV (0x3 << 16)
136 #define A31_PLL6_24M_POST_DIV_SHIFT 16
137 #define A31_PLL6_FACTOR_N (0x1f << 8)
138 #define A31_PLL6_FACTOR_N_SHIFT 8
139 #define A31_PLL6_FACTOR_K (0x3 << 4)
140 #define A31_PLL6_FACTOR_K_SHIFT 4
141 #define A31_PLL6_DEFAULT_N 0x18
142 #define A31_PLL6_DEFAULT_K 0x1
143 #define A31_PLL6_TIMEOUT 10
145 #define A80_PLL4_CLK_OUT_EN (1 << 20)
146 #define A80_PLL4_PLL_DIV2 (1 << 18)
147 #define A80_PLL4_PLL_DIV1 (1 << 16)
148 #define A80_PLL4_FACTOR_N (0xff << 8)
149 #define A80_PLL4_FACTOR_N_SHIFT 8
151 #define CLKID_A10_PLL3_1X 0
152 #define CLKID_A10_PLL3_2X 1
154 #define CLKID_A10_PLL5_DDR 0
155 #define CLKID_A10_PLL5_OTHER 1
157 #define CLKID_A10_PLL6_SATA 0
158 #define CLKID_A10_PLL6_OTHER 1
159 #define CLKID_A10_PLL6 2
160 #define CLKID_A10_PLL6_DIV_4 3
162 #define CLKID_A31_PLL6 0
163 #define CLKID_A31_PLL6_X2 1
179 enum aw_pll_type type;
185 struct aw_pll_funcs {
186 int (*recalc)(struct aw_pll_sc *, uint64_t *);
187 int (*set_freq)(struct aw_pll_sc *, uint64_t, uint64_t *, int);
188 int (*init)(device_t, bus_addr_t, struct clknode_init_def *);
191 #define PLL_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
192 #define PLL_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
193 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
194 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
197 a10_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
199 uint32_t val, m, n, k, p;
205 p = 1 << ((val & A10_PLL1_OUT_EXT_DIVP) >> A10_PLL1_OUT_EXT_DIVP_SHIFT);
206 m = ((val & A10_PLL1_FACTOR_M) >> A10_PLL1_FACTOR_M_SHIFT) + 1;
207 k = ((val & A10_PLL1_FACTOR_K) >> A10_PLL1_FACTOR_K_SHIFT) + 1;
208 n = (val & A10_PLL1_FACTOR_N) >> A10_PLL1_FACTOR_N_SHIFT;
212 *freq = (*freq * n * k) / (m * p);
218 a10_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
220 uint32_t val, post_div, n, pre_div;
226 post_div = (val & A10_PLL2_POST_DIV) >> A10_PLL2_POST_DIV_SHIFT;
229 n = (val & A10_PLL2_FACTOR_N) >> A10_PLL2_FACTOR_N_SHIFT;
232 pre_div = (val & A10_PLL2_PRE_DIV) >> A10_PLL2_PRE_DIV_SHIFT;
237 case SUN4I_A10_PLL2_1X:
238 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
240 case SUN4I_A10_PLL2_2X:
241 *freq = (*freq * 2 * n) / pre_div / 4;
243 case SUN4I_A10_PLL2_4X:
244 *freq = (*freq * 2 * n) / pre_div / 2;
246 case SUN4I_A10_PLL2_8X:
247 *freq = (*freq * 2 * n) / pre_div;
257 a10_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
260 uint32_t val, post_div, n, pre_div;
262 if (sc->id != SUN4I_A10_PLL2_1X)
266 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
268 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
269 * To get as close as possible to the desired rate, we use a
270 * pre-divider of 21 and a post-divider of 4. With these values,
271 * a multiplier of 86 or 79 gets us close to the target rates.
273 if (*fout != 24576000 && *fout != 22579200)
278 n = (*fout * pre_div * post_div * 2) / (2 * fin);
282 val &= ~(A10_PLL2_POST_DIV | A10_PLL2_FACTOR_N | A10_PLL2_PRE_DIV);
283 val |= (post_div << A10_PLL2_POST_DIV_SHIFT);
284 val |= (n << A10_PLL2_FACTOR_N_SHIFT);
285 val |= (pre_div << A10_PLL2_PRE_DIV_SHIFT);
293 a10_pll3_recalc(struct aw_pll_sc *sc, uint64_t *freq)
301 if ((val & A10_PLL3_MODE_SEL) == A10_PLL3_MODE_SEL_INT) {
302 /* In integer mode, output is 3MHz * m */
303 m = (val & A10_PLL3_FACTOR_M) >> A10_PLL3_FACTOR_M_SHIFT;
304 *freq = A10_PLL3_REF_FREQ * m;
306 /* In fractional mode, output is either 270MHz or 297MHz */
307 if ((val & A10_PLL3_FUNC_SET) == A10_PLL3_FUNC_SET_270MHZ)
313 if (sc->id == CLKID_A10_PLL3_2X)
320 a10_pll3_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
323 uint32_t val, m, mode, func;
325 m = *fout / A10_PLL3_REF_FREQ;
326 if (sc->id == CLKID_A10_PLL3_2X)
329 mode = A10_PLL3_MODE_SEL_INT;
331 *fout = m * A10_PLL3_REF_FREQ;
332 if (sc->id == CLKID_A10_PLL3_2X)
337 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
340 val |= (m << A10_PLL3_FACTOR_M_SHIFT);
348 a10_pll3_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
352 /* Allow changing PLL frequency while enabled */
353 def->flags = CLK_NODE_GLITCH_FREE;
355 /* Set PLL to 297MHz */
356 CLKDEV_DEVICE_LOCK(dev);
357 CLKDEV_READ_4(dev, reg, &val);
358 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
359 val |= A10_PLL3_MODE_SEL_FRACT;
360 val |= A10_PLL3_FUNC_SET_297MHZ;
361 CLKDEV_WRITE_4(dev, reg, val);
362 CLKDEV_DEVICE_UNLOCK(dev);
368 a10_pll5_recalc(struct aw_pll_sc *sc, uint64_t *freq)
370 uint32_t val, m, n, k, p;
376 p = 1 << ((val & A10_PLL5_OUT_EXT_DIVP) >> A10_PLL5_OUT_EXT_DIVP_SHIFT);
377 m = ((val & A10_PLL5_FACTOR_M) >> A10_PLL5_FACTOR_M_SHIFT) + 1;
378 k = ((val & A10_PLL5_FACTOR_K) >> A10_PLL5_FACTOR_K_SHIFT) + 1;
379 n = (val & A10_PLL5_FACTOR_N) >> A10_PLL5_FACTOR_N_SHIFT;
384 case CLKID_A10_PLL5_DDR:
385 *freq = (*freq * n * k) / m;
387 case CLKID_A10_PLL5_OTHER:
388 *freq = (*freq * n * k) / p;
398 a10_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
400 uint32_t val, m, n, k;
403 * SATA needs PLL6 to be a 100MHz clock.
405 * The SATA output frequency is (24MHz * n * k) / m / 6.
406 * To get to 100MHz, k & m must be equal and n must be 25.
411 CLKDEV_DEVICE_LOCK(dev);
412 CLKDEV_READ_4(dev, reg, &val);
413 val &= ~(A10_PLL6_FACTOR_N | A10_PLL6_FACTOR_K | A10_PLL6_FACTOR_M);
414 val &= ~A10_PLL6_BYPASS_EN;
415 val |= A10_PLL6_SATA_CLK_EN;
416 val |= (n << A10_PLL6_FACTOR_N_SHIFT);
417 val |= (k << A10_PLL6_FACTOR_K_SHIFT);
418 val |= (m << A10_PLL6_FACTOR_M_SHIFT);
419 CLKDEV_WRITE_4(dev, reg, val);
420 CLKDEV_DEVICE_UNLOCK(dev);
426 a10_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
428 uint32_t val, m, k, n;
434 m = ((val & A10_PLL6_FACTOR_M) >> A10_PLL6_FACTOR_M_SHIFT) + 1;
435 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
436 n = (val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT;
441 case CLKID_A10_PLL6_SATA:
442 *freq = (*freq * n * k) / m / 6;
444 case CLKID_A10_PLL6_OTHER:
445 *freq = (*freq * n * k) / 2;
448 *freq = (*freq * n * k);
450 case CLKID_A10_PLL6_DIV_4:
451 *freq = (*freq * n * k) / 4;
461 a10_pll6_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
464 if (sc->id != CLKID_A10_PLL6_SATA)
467 /* PLL6 SATA output has been set to 100MHz in a10_pll6_init */
468 if (*fout != 100000000)
475 a13_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
477 uint32_t val, post_div, n, pre_div;
483 post_div = ((val & A13_PLL2_POST_DIV) >> A13_PLL2_POST_DIV_SHIFT) + 1;
486 n = (val & A13_PLL2_FACTOR_N) >> A13_PLL2_FACTOR_N_SHIFT;
489 pre_div = ((val & A13_PLL2_PRE_DIV) >> A13_PLL2_PRE_DIV_SHIFT) + 1;
494 case SUN4I_A10_PLL2_1X:
495 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
497 case SUN4I_A10_PLL2_2X:
498 *freq = (*freq * 2 * n) / pre_div / 4;
500 case SUN4I_A10_PLL2_4X:
501 *freq = (*freq * 2 * n) / pre_div / 2;
503 case SUN4I_A10_PLL2_8X:
504 *freq = (*freq * 2 * n) / pre_div;
514 a13_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
517 uint32_t val, post_div, n, pre_div;
519 if (sc->id != SUN4I_A10_PLL2_1X)
523 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
525 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
526 * To get as close as possible to the desired rate, we use a
527 * pre-divider of 21 and a post-divider of 4. With these values,
528 * a multiplier of 86 or 79 gets us close to the target rates.
530 if (*fout != 24576000 && *fout != 22579200)
535 n = (*fout * pre_div * post_div * 2) / (2 * fin);
539 val &= ~(A13_PLL2_POST_DIV | A13_PLL2_FACTOR_N | A13_PLL2_PRE_DIV);
540 val |= ((post_div - 1) << A13_PLL2_POST_DIV_SHIFT);
541 val |= (n << A13_PLL2_FACTOR_N_SHIFT);
542 val |= ((pre_div - 1) << A13_PLL2_PRE_DIV_SHIFT);
550 a23_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
552 uint32_t val, m, n, k, p;
558 m = ((val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT) + 1;
559 k = ((val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT) + 1;
560 n = ((val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT) + 1;
561 p = ((val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT) + 1;
563 *freq = (*freq * n * k) / (m * p);
569 a31_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
571 uint32_t val, m, n, k;
577 m = ((val & A31_PLL1_FACTOR_M) >> A31_PLL1_FACTOR_M_SHIFT) + 1;
578 k = ((val & A31_PLL1_FACTOR_K) >> A31_PLL1_FACTOR_K_SHIFT) + 1;
579 n = ((val & A31_PLL1_FACTOR_N) >> A31_PLL1_FACTOR_N_SHIFT) + 1;
581 *freq = (*freq * n * k) / m;
587 a31_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
592 if (def->id != CLKID_A31_PLL6)
596 * The datasheet recommends that PLL6 output should be fixed to
599 CLKDEV_DEVICE_LOCK(dev);
600 CLKDEV_READ_4(dev, reg, &val);
601 val &= ~(A31_PLL6_FACTOR_N | A31_PLL6_FACTOR_K | A31_PLL6_BYPASS_EN);
602 val |= (A31_PLL6_DEFAULT_N << A31_PLL6_FACTOR_N_SHIFT);
603 val |= (A31_PLL6_DEFAULT_K << A31_PLL6_FACTOR_K_SHIFT);
604 CLKDEV_WRITE_4(dev, reg, val);
606 /* Wait for PLL to become stable */
607 for (retry = A31_PLL6_TIMEOUT; retry > 0; retry--) {
608 CLKDEV_READ_4(dev, reg, &val);
609 if ((val & A31_PLL6_LOCK) == A31_PLL6_LOCK)
614 CLKDEV_DEVICE_UNLOCK(dev);
623 a31_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
631 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
632 n = ((val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT) + 1;
636 *freq = (*freq * n * k) / 2;
638 case CLKID_A31_PLL6_X2:
639 *freq = *freq * n * k;
649 a80_pll4_recalc(struct aw_pll_sc *sc, uint64_t *freq)
651 uint32_t val, n, div1, div2;
657 n = (val & A80_PLL4_FACTOR_N) >> A80_PLL4_FACTOR_N_SHIFT;
658 div1 = (val & A80_PLL4_PLL_DIV1) == 0 ? 1 : 2;
659 div2 = (val & A80_PLL4_PLL_DIV2) == 0 ? 1 : 2;
661 *freq = (*freq * n) / div1 / div2;
666 #define PLL(_type, _recalc, _set_freq, _init) \
668 .recalc = (_recalc), \
669 .set_freq = (_set_freq), \
673 static struct aw_pll_funcs aw_pll_func[] = {
674 PLL(AWPLL_A10_PLL1, a10_pll1_recalc, NULL, NULL),
675 PLL(AWPLL_A10_PLL2, a10_pll2_recalc, a10_pll2_set_freq, NULL),
676 PLL(AWPLL_A10_PLL3, a10_pll3_recalc, a10_pll3_set_freq, a10_pll3_init),
677 PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL),
678 PLL(AWPLL_A10_PLL6, a10_pll6_recalc, a10_pll6_set_freq, a10_pll6_init),
679 PLL(AWPLL_A13_PLL2, a13_pll2_recalc, a13_pll2_set_freq, NULL),
680 PLL(AWPLL_A23_PLL1, a23_pll1_recalc, NULL, NULL),
681 PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL),
682 PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init),
683 PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),
686 static struct ofw_compat_data compat_data[] = {
687 { "allwinner,sun4i-a10-pll1-clk", AWPLL_A10_PLL1 },
688 { "allwinner,sun4i-a10-pll2-clk", AWPLL_A10_PLL2 },
689 { "allwinner,sun4i-a10-pll3-clk", AWPLL_A10_PLL3 },
690 { "allwinner,sun4i-a10-pll5-clk", AWPLL_A10_PLL5 },
691 { "allwinner,sun4i-a10-pll6-clk", AWPLL_A10_PLL6 },
692 { "allwinner,sun5i-a13-pll2-clk", AWPLL_A13_PLL2 },
693 { "allwinner,sun6i-a31-pll1-clk", AWPLL_A31_PLL1 },
694 { "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 },
695 { "allwinner,sun8i-a23-pll1-clk", AWPLL_A23_PLL1 },
696 { "allwinner,sun9i-a80-pll4-clk", AWPLL_A80_PLL4 },
701 aw_pll_init(struct clknode *clk, device_t dev)
703 clknode_init_parent_idx(clk, 0);
708 aw_pll_set_gate(struct clknode *clk, bool enable)
710 struct aw_pll_sc *sc;
713 sc = clknode_get_softc(clk);
718 val |= AW_PLL_ENABLE;
720 val &= ~AW_PLL_ENABLE;
728 aw_pll_recalc(struct clknode *clk, uint64_t *freq)
730 struct aw_pll_sc *sc;
732 sc = clknode_get_softc(clk);
734 if (aw_pll_func[sc->type].recalc == NULL)
737 return (aw_pll_func[sc->type].recalc(sc, freq));
741 aw_pll_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
742 int flags, int *stop)
744 struct aw_pll_sc *sc;
746 sc = clknode_get_softc(clk);
750 if (aw_pll_func[sc->type].set_freq == NULL)
753 return (aw_pll_func[sc->type].set_freq(sc, fin, fout, flags));
756 static clknode_method_t aw_pll_clknode_methods[] = {
757 /* Device interface */
758 CLKNODEMETHOD(clknode_init, aw_pll_init),
759 CLKNODEMETHOD(clknode_set_gate, aw_pll_set_gate),
760 CLKNODEMETHOD(clknode_recalc_freq, aw_pll_recalc),
761 CLKNODEMETHOD(clknode_set_freq, aw_pll_set_freq),
765 DEFINE_CLASS_1(aw_pll_clknode, aw_pll_clknode_class, aw_pll_clknode_methods,
766 sizeof(struct aw_pll_sc), clknode_class);
769 aw_pll_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
770 const char *pclkname, const char *clkname, int index)
772 enum aw_pll_type type;
773 struct clknode_init_def clkdef;
774 struct aw_pll_sc *sc;
778 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
780 memset(&clkdef, 0, sizeof(clkdef));
782 clkdef.name = clkname;
783 if (pclkname != NULL) {
784 clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP,
786 clkdef.parent_names[0] = pclkname;
787 clkdef.parent_cnt = 1;
789 clkdef.parent_cnt = 0;
791 if (aw_pll_func[type].init != NULL) {
792 error = aw_pll_func[type].init(device_get_parent(dev),
795 device_printf(dev, "clock %s init failed\n", clkname);
800 clk = clknode_create(clkdom, &aw_pll_clknode_class, &clkdef);
802 device_printf(dev, "cannot create clock node\n");
805 sc = clknode_get_softc(clk);
806 sc->clkdev = device_get_parent(dev);
811 clknode_register(clkdom, clk);
813 OF_prop_free(__DECONST(char *, clkdef.parent_names));
819 aw_pll_probe(device_t dev)
821 if (!ofw_bus_status_okay(dev))
824 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
827 device_set_desc(dev, "Allwinner PLL Clock");
828 return (BUS_PROBE_DEFAULT);
832 aw_pll_attach(device_t dev)
834 struct clkdom *clkdom;
836 int index, nout, error;
843 node = ofw_bus_get_node(dev);
845 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
846 device_printf(dev, "couldn't parse 'reg' property\n");
850 clkdom = clkdom_create(dev);
852 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
854 device_printf(dev, "no clock outputs found\n");
859 if (clk_get_by_ofw_index(dev, 0, &clk_parent) != 0)
862 for (index = 0; index < nout; index++) {
863 error = aw_pll_create(dev, paddr, clkdom,
864 clk_parent ? clk_get_name(clk_parent) : NULL,
865 names[index], nout == 1 ? 1 : index);
870 if (clkdom_finit(clkdom) != 0) {
871 device_printf(dev, "cannot finalize clkdom initialization\n");
885 static device_method_t aw_pll_methods[] = {
886 /* Device interface */
887 DEVMETHOD(device_probe, aw_pll_probe),
888 DEVMETHOD(device_attach, aw_pll_attach),
893 static driver_t aw_pll_driver = {
899 static devclass_t aw_pll_devclass;
901 EARLY_DRIVER_MODULE(aw_pll, simplebus, aw_pll_driver,
902 aw_pll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);