2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk.h>
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
52 #include <arm/allwinner/aw_machdep.h>
54 #include "clkdev_if.h"
56 #define AW_PLL_ENABLE (1 << 31)
58 #define A10_PLL1_OUT_EXT_DIVP (0x3 << 16)
59 #define A10_PLL1_OUT_EXT_DIVP_SHIFT 16
60 #define A10_PLL1_FACTOR_N (0x1f << 8)
61 #define A10_PLL1_FACTOR_N_SHIFT 8
62 #define A10_PLL1_FACTOR_K (0x3 << 4)
63 #define A10_PLL1_FACTOR_K_SHIFT 4
64 #define A10_PLL1_FACTOR_M (0x3 << 0)
65 #define A10_PLL1_FACTOR_M_SHIFT 0
67 #define A10_PLL2_POST_DIV (0xf << 26)
68 #define A10_PLL2_POST_DIV_SHIFT 26
69 #define A10_PLL2_FACTOR_N (0x7f << 8)
70 #define A10_PLL2_FACTOR_N_SHIFT 8
71 #define A10_PLL2_PRE_DIV (0x1f << 0)
72 #define A10_PLL2_PRE_DIV_SHIFT 0
74 #define A10_PLL3_MODE_SEL (0x1 << 15)
75 #define A10_PLL3_MODE_SEL_FRACT (0 << 15)
76 #define A10_PLL3_MODE_SEL_INT (1 << 15)
77 #define A10_PLL3_FUNC_SET (0x1 << 14)
78 #define A10_PLL3_FUNC_SET_270MHZ (0 << 14)
79 #define A10_PLL3_FUNC_SET_297MHZ (1 << 14)
80 #define A10_PLL3_FACTOR_M (0x7f << 0)
81 #define A10_PLL3_FACTOR_M_SHIFT 0
82 #define A10_PLL3_REF_FREQ 3000000
84 #define A10_PLL5_OUT_EXT_DIVP (0x3 << 16)
85 #define A10_PLL5_OUT_EXT_DIVP_SHIFT 16
86 #define A10_PLL5_FACTOR_N (0x1f << 8)
87 #define A10_PLL5_FACTOR_N_SHIFT 8
88 #define A10_PLL5_FACTOR_K (0x3 << 4)
89 #define A10_PLL5_FACTOR_K_SHIFT 4
90 #define A10_PLL5_FACTOR_M1 (0x3 << 2)
91 #define A10_PLL5_FACTOR_M1_SHIFT 2
92 #define A10_PLL5_FACTOR_M (0x3 << 0)
93 #define A10_PLL5_FACTOR_M_SHIFT 0
95 #define A10_PLL6_BYPASS_EN (1 << 30)
96 #define A10_PLL6_SATA_CLK_EN (1 << 14)
97 #define A10_PLL6_FACTOR_N (0x1f << 8)
98 #define A10_PLL6_FACTOR_N_SHIFT 8
99 #define A10_PLL6_FACTOR_K (0x3 << 4)
100 #define A10_PLL6_FACTOR_K_SHIFT 4
101 #define A10_PLL6_FACTOR_M (0x3 << 0)
102 #define A10_PLL6_FACTOR_M_SHIFT 0
104 #define A10_PLL2_POST_DIV (0xf << 26)
106 #define A13_PLL2_POST_DIV (0xf << 26)
107 #define A13_PLL2_POST_DIV_SHIFT 26
108 #define A13_PLL2_FACTOR_N (0x7f << 8)
109 #define A13_PLL2_FACTOR_N_SHIFT 8
110 #define A13_PLL2_PRE_DIV (0x1f << 0)
111 #define A13_PLL2_PRE_DIV_SHIFT 0
113 #define A23_PLL1_FACTOR_P (0x3 << 16)
114 #define A23_PLL1_FACTOR_P_SHIFT 16
115 #define A23_PLL1_FACTOR_N (0x1f << 8)
116 #define A23_PLL1_FACTOR_N_SHIFT 8
117 #define A23_PLL1_FACTOR_K (0x3 << 4)
118 #define A23_PLL1_FACTOR_K_SHIFT 4
119 #define A23_PLL1_FACTOR_M (0x3 << 0)
120 #define A23_PLL1_FACTOR_M_SHIFT 0
122 #define A31_PLL1_LOCK (1 << 28)
123 #define A31_PLL1_CPU_SIGMA_DELTA_EN (1 << 24)
124 #define A31_PLL1_FACTOR_N (0x1f << 8)
125 #define A31_PLL1_FACTOR_N_SHIFT 8
126 #define A31_PLL1_FACTOR_K (0x3 << 4)
127 #define A31_PLL1_FACTOR_K_SHIFT 4
128 #define A31_PLL1_FACTOR_M (0x3 << 0)
129 #define A31_PLL1_FACTOR_M_SHIFT 0
131 #define A31_PLL6_LOCK (1 << 28)
132 #define A31_PLL6_BYPASS_EN (1 << 25)
133 #define A31_PLL6_CLK_OUT_EN (1 << 24)
134 #define A31_PLL6_24M_OUT_EN (1 << 18)
135 #define A31_PLL6_24M_POST_DIV (0x3 << 16)
136 #define A31_PLL6_24M_POST_DIV_SHIFT 16
137 #define A31_PLL6_FACTOR_N (0x1f << 8)
138 #define A31_PLL6_FACTOR_N_SHIFT 8
139 #define A31_PLL6_FACTOR_K (0x3 << 4)
140 #define A31_PLL6_FACTOR_K_SHIFT 4
141 #define A31_PLL6_DEFAULT_N 0x18
142 #define A31_PLL6_DEFAULT_K 0x1
143 #define A31_PLL6_TIMEOUT 10
145 #define A64_PLLHSIC_LOCK (1 << 28)
146 #define A64_PLLHSIC_FRAC_CLK_OUT (1 << 25)
147 #define A64_PLLHSIC_PLL_MODE_SEL (1 << 24)
148 #define A64_PLLHSIC_PLL_SDM_EN (1 << 20)
149 #define A64_PLLHSIC_FACTOR_N (0x7f << 8)
150 #define A64_PLLHSIC_FACTOR_N_SHIFT 8
151 #define A64_PLLHSIC_PRE_DIV_M (0xf << 0)
152 #define A64_PLLHSIC_PRE_DIV_M_SHIFT 0
154 #define A80_PLL4_CLK_OUT_EN (1 << 20)
155 #define A80_PLL4_PLL_DIV2 (1 << 18)
156 #define A80_PLL4_PLL_DIV1 (1 << 16)
157 #define A80_PLL4_FACTOR_N (0xff << 8)
158 #define A80_PLL4_FACTOR_N_SHIFT 8
160 #define A83T_PLLCPUX_LOCK_TIME (0x7 << 24)
161 #define A83T_PLLCPUX_LOCK_TIME_SHIFT 24
162 #define A83T_PLLCPUX_CLOCK_OUTPUT_DIS (1 << 20)
163 #define A83T_PLLCPUX_OUT_EXT_DIVP (1 << 16)
164 #define A83T_PLLCPUX_FACTOR_N (0xff << 8)
165 #define A83T_PLLCPUX_FACTOR_N_SHIFT 8
166 #define A83T_PLLCPUX_FACTOR_N_MIN 12
167 #define A83T_PLLCPUX_FACTOR_N_MAX 125
168 #define A83T_PLLCPUX_POSTDIV_M (0x3 << 0)
169 #define A83T_PLLCPUX_POSTDIV_M_SHIFT 0
171 #define CLKID_A10_PLL3_1X 0
172 #define CLKID_A10_PLL3_2X 1
174 #define CLKID_A10_PLL5_DDR 0
175 #define CLKID_A10_PLL5_OTHER 1
177 #define CLKID_A10_PLL6_SATA 0
178 #define CLKID_A10_PLL6_OTHER 1
179 #define CLKID_A10_PLL6 2
180 #define CLKID_A10_PLL6_DIV_4 3
182 #define CLKID_A31_PLL6 0
183 #define CLKID_A31_PLL6_X2 1
185 struct aw_pll_factor {
192 #define PLLFACTOR(_n, _k, _m, _p, _freq) \
193 { .n = (_n), .k = (_k), .m = (_m), .p = (_p), .freq = (_freq) }
195 static struct aw_pll_factor aw_a23_pll1_factors[] = {
196 PLLFACTOR(16, 0, 0, 0, 408000000),
197 PLLFACTOR(26, 0, 0, 0, 648000000),
198 PLLFACTOR(16, 1, 0, 0, 816000000),
199 PLLFACTOR(20, 1, 0, 0, 1008000000),
200 PLLFACTOR(24, 1, 0, 0, 1200000000),
201 PLLFACTOR(26, 1, 0, 0, 1296000000),
221 enum aw_pll_type type;
227 struct aw_pll_funcs {
228 int (*recalc)(struct aw_pll_sc *, uint64_t *);
229 int (*set_freq)(struct aw_pll_sc *, uint64_t, uint64_t *, int);
230 int (*init)(device_t, bus_addr_t, struct clknode_init_def *);
233 #define PLL_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
234 #define PLL_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
235 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
236 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
239 a10_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
241 uint32_t val, m, n, k, p;
247 p = 1 << ((val & A10_PLL1_OUT_EXT_DIVP) >> A10_PLL1_OUT_EXT_DIVP_SHIFT);
248 m = ((val & A10_PLL1_FACTOR_M) >> A10_PLL1_FACTOR_M_SHIFT) + 1;
249 k = ((val & A10_PLL1_FACTOR_K) >> A10_PLL1_FACTOR_K_SHIFT) + 1;
250 n = (val & A10_PLL1_FACTOR_N) >> A10_PLL1_FACTOR_N_SHIFT;
254 *freq = (*freq * n * k) / (m * p);
260 a10_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
262 uint32_t val, post_div, n, pre_div;
268 post_div = (val & A10_PLL2_POST_DIV) >> A10_PLL2_POST_DIV_SHIFT;
271 n = (val & A10_PLL2_FACTOR_N) >> A10_PLL2_FACTOR_N_SHIFT;
274 pre_div = (val & A10_PLL2_PRE_DIV) >> A10_PLL2_PRE_DIV_SHIFT;
279 case SUN4I_A10_PLL2_1X:
280 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
282 case SUN4I_A10_PLL2_2X:
283 *freq = (*freq * 2 * n) / pre_div / 4;
285 case SUN4I_A10_PLL2_4X:
286 *freq = (*freq * 2 * n) / pre_div / 2;
288 case SUN4I_A10_PLL2_8X:
289 *freq = (*freq * 2 * n) / pre_div;
299 a10_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
302 uint32_t val, post_div, n, pre_div;
304 if (sc->id != SUN4I_A10_PLL2_1X)
308 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
310 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
311 * To get as close as possible to the desired rate, we use a
312 * pre-divider of 21 and a post-divider of 4. With these values,
313 * a multiplier of 86 or 79 gets us close to the target rates.
315 if (*fout != 24576000 && *fout != 22579200)
320 n = (*fout * pre_div * post_div * 2) / (2 * fin);
324 val &= ~(A10_PLL2_POST_DIV | A10_PLL2_FACTOR_N | A10_PLL2_PRE_DIV);
325 val |= (post_div << A10_PLL2_POST_DIV_SHIFT);
326 val |= (n << A10_PLL2_FACTOR_N_SHIFT);
327 val |= (pre_div << A10_PLL2_PRE_DIV_SHIFT);
335 a10_pll3_recalc(struct aw_pll_sc *sc, uint64_t *freq)
343 if ((val & A10_PLL3_MODE_SEL) == A10_PLL3_MODE_SEL_INT) {
344 /* In integer mode, output is 3MHz * m */
345 m = (val & A10_PLL3_FACTOR_M) >> A10_PLL3_FACTOR_M_SHIFT;
346 *freq = A10_PLL3_REF_FREQ * m;
348 /* In fractional mode, output is either 270MHz or 297MHz */
349 if ((val & A10_PLL3_FUNC_SET) == A10_PLL3_FUNC_SET_270MHZ)
355 if (sc->id == CLKID_A10_PLL3_2X)
362 a10_pll3_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
365 uint32_t val, m, mode, func;
367 m = *fout / A10_PLL3_REF_FREQ;
368 if (sc->id == CLKID_A10_PLL3_2X)
371 mode = A10_PLL3_MODE_SEL_INT;
373 *fout = m * A10_PLL3_REF_FREQ;
374 if (sc->id == CLKID_A10_PLL3_2X)
379 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
382 val |= (m << A10_PLL3_FACTOR_M_SHIFT);
390 a10_pll3_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
394 /* Allow changing PLL frequency while enabled */
395 def->flags = CLK_NODE_GLITCH_FREE;
397 /* Set PLL to 297MHz */
398 CLKDEV_DEVICE_LOCK(dev);
399 CLKDEV_READ_4(dev, reg, &val);
400 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
401 val |= A10_PLL3_MODE_SEL_FRACT;
402 val |= A10_PLL3_FUNC_SET_297MHZ;
403 CLKDEV_WRITE_4(dev, reg, val);
404 CLKDEV_DEVICE_UNLOCK(dev);
410 a10_pll5_recalc(struct aw_pll_sc *sc, uint64_t *freq)
412 uint32_t val, m, n, k, p;
418 p = 1 << ((val & A10_PLL5_OUT_EXT_DIVP) >> A10_PLL5_OUT_EXT_DIVP_SHIFT);
419 m = ((val & A10_PLL5_FACTOR_M) >> A10_PLL5_FACTOR_M_SHIFT) + 1;
420 k = ((val & A10_PLL5_FACTOR_K) >> A10_PLL5_FACTOR_K_SHIFT) + 1;
421 n = (val & A10_PLL5_FACTOR_N) >> A10_PLL5_FACTOR_N_SHIFT;
426 case CLKID_A10_PLL5_DDR:
427 *freq = (*freq * n * k) / m;
429 case CLKID_A10_PLL5_OTHER:
430 *freq = (*freq * n * k) / p;
440 a10_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
442 uint32_t val, m, n, k;
445 * SATA needs PLL6 to be a 100MHz clock.
447 * The SATA output frequency is (24MHz * n * k) / m / 6.
448 * To get to 100MHz, k & m must be equal and n must be 25.
453 CLKDEV_DEVICE_LOCK(dev);
454 CLKDEV_READ_4(dev, reg, &val);
455 val &= ~(A10_PLL6_FACTOR_N | A10_PLL6_FACTOR_K | A10_PLL6_FACTOR_M);
456 val &= ~A10_PLL6_BYPASS_EN;
457 val |= A10_PLL6_SATA_CLK_EN;
458 val |= (n << A10_PLL6_FACTOR_N_SHIFT);
459 val |= (k << A10_PLL6_FACTOR_K_SHIFT);
460 val |= (m << A10_PLL6_FACTOR_M_SHIFT);
461 CLKDEV_WRITE_4(dev, reg, val);
462 CLKDEV_DEVICE_UNLOCK(dev);
468 a10_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
470 uint32_t val, m, k, n;
476 m = ((val & A10_PLL6_FACTOR_M) >> A10_PLL6_FACTOR_M_SHIFT) + 1;
477 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
478 n = (val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT;
483 case CLKID_A10_PLL6_SATA:
484 *freq = (*freq * n * k) / m / 6;
486 case CLKID_A10_PLL6_OTHER:
487 *freq = (*freq * n * k) / 2;
490 *freq = (*freq * n * k);
492 case CLKID_A10_PLL6_DIV_4:
493 *freq = (*freq * n * k) / 4;
503 a10_pll6_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
506 if (sc->id != CLKID_A10_PLL6_SATA)
509 /* PLL6 SATA output has been set to 100MHz in a10_pll6_init */
510 if (*fout != 100000000)
517 a13_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
519 uint32_t val, post_div, n, pre_div;
525 post_div = ((val & A13_PLL2_POST_DIV) >> A13_PLL2_POST_DIV_SHIFT) + 1;
528 n = (val & A13_PLL2_FACTOR_N) >> A13_PLL2_FACTOR_N_SHIFT;
531 pre_div = ((val & A13_PLL2_PRE_DIV) >> A13_PLL2_PRE_DIV_SHIFT) + 1;
536 case SUN4I_A10_PLL2_1X:
537 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
539 case SUN4I_A10_PLL2_2X:
540 *freq = (*freq * 2 * n) / pre_div / 4;
542 case SUN4I_A10_PLL2_4X:
543 *freq = (*freq * 2 * n) / pre_div / 2;
545 case SUN4I_A10_PLL2_8X:
546 *freq = (*freq * 2 * n) / pre_div;
556 a13_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
559 uint32_t val, post_div, n, pre_div;
561 if (sc->id != SUN4I_A10_PLL2_1X)
565 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
567 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
568 * To get as close as possible to the desired rate, we use a
569 * pre-divider of 21 and a post-divider of 4. With these values,
570 * a multiplier of 86 or 79 gets us close to the target rates.
572 if (*fout != 24576000 && *fout != 22579200)
577 n = (*fout * pre_div * post_div * 2) / (2 * fin);
581 val &= ~(A13_PLL2_POST_DIV | A13_PLL2_FACTOR_N | A13_PLL2_PRE_DIV);
582 val |= ((post_div - 1) << A13_PLL2_POST_DIV_SHIFT);
583 val |= (n << A13_PLL2_FACTOR_N_SHIFT);
584 val |= ((pre_div - 1) << A13_PLL2_PRE_DIV_SHIFT);
592 a23_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
595 struct aw_pll_factor *f;
600 for (n = 0; n < nitems(aw_a23_pll1_factors); n++) {
601 if (aw_a23_pll1_factors[n].freq == *fout) {
602 f = &aw_a23_pll1_factors[n];
611 val &= ~(A23_PLL1_FACTOR_N|A23_PLL1_FACTOR_K|A23_PLL1_FACTOR_M|
613 val |= (f->n << A23_PLL1_FACTOR_N_SHIFT);
614 val |= (f->k << A23_PLL1_FACTOR_K_SHIFT);
615 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
616 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
625 a23_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
627 uint32_t val, m, n, k, p;
633 m = ((val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT) + 1;
634 k = ((val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT) + 1;
635 n = ((val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT) + 1;
636 p = ((val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT) + 1;
638 *freq = (*freq * n * k) / (m * p);
644 h3_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
647 struct aw_pll_factor *f;
648 uint32_t val, n, k, m, p;
652 for (i = 0; i < nitems(aw_a23_pll1_factors); i++) {
653 if (aw_a23_pll1_factors[i].freq == *fout) {
654 f = &aw_a23_pll1_factors[i];
664 n = (val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT;
665 k = (val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT;
666 m = (val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT;
667 p = (val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT;
670 val &= ~A23_PLL1_FACTOR_P;
671 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
677 val &= ~A23_PLL1_FACTOR_M;
678 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
683 val &= ~(A23_PLL1_FACTOR_N|A23_PLL1_FACTOR_K);
684 val |= (f->n << A23_PLL1_FACTOR_N_SHIFT);
685 val |= (f->k << A23_PLL1_FACTOR_K_SHIFT);
690 val &= ~A23_PLL1_FACTOR_M;
691 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
697 val &= ~A23_PLL1_FACTOR_P;
698 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
710 a31_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
712 uint32_t val, m, n, k;
718 m = ((val & A31_PLL1_FACTOR_M) >> A31_PLL1_FACTOR_M_SHIFT) + 1;
719 k = ((val & A31_PLL1_FACTOR_K) >> A31_PLL1_FACTOR_K_SHIFT) + 1;
720 n = ((val & A31_PLL1_FACTOR_N) >> A31_PLL1_FACTOR_N_SHIFT) + 1;
722 *freq = (*freq * n * k) / m;
728 a31_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
733 if (def->id != CLKID_A31_PLL6)
737 * The datasheet recommends that PLL6 output should be fixed to
740 CLKDEV_DEVICE_LOCK(dev);
741 CLKDEV_READ_4(dev, reg, &val);
742 val &= ~(A31_PLL6_FACTOR_N | A31_PLL6_FACTOR_K | A31_PLL6_BYPASS_EN);
743 val |= (A31_PLL6_DEFAULT_N << A31_PLL6_FACTOR_N_SHIFT);
744 val |= (A31_PLL6_DEFAULT_K << A31_PLL6_FACTOR_K_SHIFT);
745 val |= AW_PLL_ENABLE;
746 CLKDEV_WRITE_4(dev, reg, val);
748 /* Wait for PLL to become stable */
749 for (retry = A31_PLL6_TIMEOUT; retry > 0; retry--) {
750 CLKDEV_READ_4(dev, reg, &val);
751 if ((val & A31_PLL6_LOCK) == A31_PLL6_LOCK)
756 CLKDEV_DEVICE_UNLOCK(dev);
762 a31_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
770 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
771 n = ((val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT) + 1;
775 *freq = (*freq * n * k) / 2;
777 case CLKID_A31_PLL6_X2:
778 *freq = *freq * n * k;
788 a80_pll4_recalc(struct aw_pll_sc *sc, uint64_t *freq)
790 uint32_t val, n, div1, div2;
796 n = (val & A80_PLL4_FACTOR_N) >> A80_PLL4_FACTOR_N_SHIFT;
797 div1 = (val & A80_PLL4_PLL_DIV1) == 0 ? 1 : 2;
798 div2 = (val & A80_PLL4_PLL_DIV2) == 0 ? 1 : 2;
800 *freq = (*freq * n) / div1 / div2;
806 a64_pllhsic_recalc(struct aw_pll_sc *sc, uint64_t *freq)
814 n = ((val & A64_PLLHSIC_FACTOR_N) >> A64_PLLHSIC_FACTOR_N_SHIFT) + 1;
815 m = ((val & A64_PLLHSIC_PRE_DIV_M) >> A64_PLLHSIC_PRE_DIV_M_SHIFT) + 1;
817 *freq = (*freq * n) / m;
823 a64_pllhsic_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
828 * PLL_HSIC default is 480MHz, just enable it.
830 CLKDEV_DEVICE_LOCK(dev);
831 CLKDEV_READ_4(dev, reg, &val);
832 val |= AW_PLL_ENABLE;
833 CLKDEV_WRITE_4(dev, reg, val);
834 CLKDEV_DEVICE_UNLOCK(dev);
840 a83t_pllcpux_recalc(struct aw_pll_sc *sc, uint64_t *freq)
848 n = (val & A83T_PLLCPUX_FACTOR_N) >> A83T_PLLCPUX_FACTOR_N_SHIFT;
849 p = (val & A83T_PLLCPUX_OUT_EXT_DIVP) ? 4 : 1;
851 *freq = (*freq * n) / p;
857 a83t_pllcpux_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
865 if (n < A83T_PLLCPUX_FACTOR_N_MIN || n > A83T_PLLCPUX_FACTOR_N_MAX)
870 val &= ~A83T_PLLCPUX_FACTOR_N;
871 val |= (n << A83T_PLLCPUX_FACTOR_N_SHIFT);
872 val &= ~A83T_PLLCPUX_CLOCK_OUTPUT_DIS;
879 #define PLL(_type, _recalc, _set_freq, _init) \
881 .recalc = (_recalc), \
882 .set_freq = (_set_freq), \
886 static struct aw_pll_funcs aw_pll_func[] = {
887 PLL(AWPLL_A10_PLL1, a10_pll1_recalc, NULL, NULL),
888 PLL(AWPLL_A10_PLL2, a10_pll2_recalc, a10_pll2_set_freq, NULL),
889 PLL(AWPLL_A10_PLL3, a10_pll3_recalc, a10_pll3_set_freq, a10_pll3_init),
890 PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL),
891 PLL(AWPLL_A10_PLL6, a10_pll6_recalc, a10_pll6_set_freq, a10_pll6_init),
892 PLL(AWPLL_A13_PLL2, a13_pll2_recalc, a13_pll2_set_freq, NULL),
893 PLL(AWPLL_A23_PLL1, a23_pll1_recalc, a23_pll1_set_freq, NULL),
894 PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL),
895 PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init),
896 PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),
897 PLL(AWPLL_A83T_PLLCPUX, a83t_pllcpux_recalc, a83t_pllcpux_set_freq, NULL),
898 PLL(AWPLL_A64_PLLHSIC, a64_pllhsic_recalc, NULL, a64_pllhsic_init),
899 PLL(AWPLL_H3_PLL1, a23_pll1_recalc, h3_pll1_set_freq, NULL),
902 static struct ofw_compat_data compat_data[] = {
903 { "allwinner,sun4i-a10-pll1-clk", AWPLL_A10_PLL1 },
904 { "allwinner,sun4i-a10-pll2-clk", AWPLL_A10_PLL2 },
905 { "allwinner,sun4i-a10-pll3-clk", AWPLL_A10_PLL3 },
906 { "allwinner,sun4i-a10-pll5-clk", AWPLL_A10_PLL5 },
907 { "allwinner,sun4i-a10-pll6-clk", AWPLL_A10_PLL6 },
908 { "allwinner,sun5i-a13-pll2-clk", AWPLL_A13_PLL2 },
909 { "allwinner,sun6i-a31-pll1-clk", AWPLL_A31_PLL1 },
910 { "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 },
911 { "allwinner,sun8i-a23-pll1-clk", AWPLL_A23_PLL1 },
912 { "allwinner,sun8i-a83t-pllcpux-clk", AWPLL_A83T_PLLCPUX },
913 { "allwinner,sun8i-h3-pll1-clk", AWPLL_H3_PLL1 },
914 { "allwinner,sun9i-a80-pll4-clk", AWPLL_A80_PLL4 },
915 { "allwinner,sun50i-a64-pllhsic-clk", AWPLL_A64_PLLHSIC },
920 aw_pll_init(struct clknode *clk, device_t dev)
922 clknode_init_parent_idx(clk, 0);
927 aw_pll_set_gate(struct clknode *clk, bool enable)
929 struct aw_pll_sc *sc;
932 sc = clknode_get_softc(clk);
937 val |= AW_PLL_ENABLE;
939 val &= ~AW_PLL_ENABLE;
947 aw_pll_recalc(struct clknode *clk, uint64_t *freq)
949 struct aw_pll_sc *sc;
951 sc = clknode_get_softc(clk);
953 if (aw_pll_func[sc->type].recalc == NULL)
956 return (aw_pll_func[sc->type].recalc(sc, freq));
960 aw_pll_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
961 int flags, int *stop)
963 struct aw_pll_sc *sc;
965 sc = clknode_get_softc(clk);
969 if (aw_pll_func[sc->type].set_freq == NULL)
972 return (aw_pll_func[sc->type].set_freq(sc, fin, fout, flags));
975 static clknode_method_t aw_pll_clknode_methods[] = {
976 /* Device interface */
977 CLKNODEMETHOD(clknode_init, aw_pll_init),
978 CLKNODEMETHOD(clknode_set_gate, aw_pll_set_gate),
979 CLKNODEMETHOD(clknode_recalc_freq, aw_pll_recalc),
980 CLKNODEMETHOD(clknode_set_freq, aw_pll_set_freq),
984 DEFINE_CLASS_1(aw_pll_clknode, aw_pll_clknode_class, aw_pll_clknode_methods,
985 sizeof(struct aw_pll_sc), clknode_class);
988 aw_pll_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
989 const char *pclkname, const char *clkname, int index)
991 enum aw_pll_type type;
992 struct clknode_init_def clkdef;
993 struct aw_pll_sc *sc;
997 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
999 memset(&clkdef, 0, sizeof(clkdef));
1001 clkdef.name = clkname;
1002 if (pclkname != NULL) {
1003 clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP,
1005 clkdef.parent_names[0] = pclkname;
1006 clkdef.parent_cnt = 1;
1008 clkdef.parent_cnt = 0;
1010 if (aw_pll_func[type].init != NULL) {
1011 error = aw_pll_func[type].init(device_get_parent(dev),
1014 device_printf(dev, "clock %s init failed\n", clkname);
1019 clk = clknode_create(clkdom, &aw_pll_clknode_class, &clkdef);
1021 device_printf(dev, "cannot create clock node\n");
1024 sc = clknode_get_softc(clk);
1025 sc->clkdev = device_get_parent(dev);
1030 clknode_register(clkdom, clk);
1032 OF_prop_free(__DECONST(char *, clkdef.parent_names));
1038 aw_pll_probe(device_t dev)
1040 if (!ofw_bus_status_okay(dev))
1043 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1046 device_set_desc(dev, "Allwinner PLL Clock");
1047 return (BUS_PROBE_DEFAULT);
1051 aw_pll_attach(device_t dev)
1053 struct clkdom *clkdom;
1055 int index, nout, error;
1062 node = ofw_bus_get_node(dev);
1064 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
1065 device_printf(dev, "couldn't parse 'reg' property\n");
1069 clkdom = clkdom_create(dev);
1071 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
1073 device_printf(dev, "no clock outputs found\n");
1078 if (clk_get_by_ofw_index(dev, 0, 0, &clk_parent) != 0)
1081 for (index = 0; index < nout; index++) {
1082 error = aw_pll_create(dev, paddr, clkdom,
1083 clk_parent ? clk_get_name(clk_parent) : NULL,
1084 names[index], nout == 1 ? 1 : index);
1089 if (clkdom_finit(clkdom) != 0) {
1090 device_printf(dev, "cannot finalize clkdom initialization\n");
1096 clkdom_dump(clkdom);
1104 static device_method_t aw_pll_methods[] = {
1105 /* Device interface */
1106 DEVMETHOD(device_probe, aw_pll_probe),
1107 DEVMETHOD(device_attach, aw_pll_attach),
1112 static driver_t aw_pll_driver = {
1118 static devclass_t aw_pll_devclass;
1120 EARLY_DRIVER_MODULE(aw_pll, simplebus, aw_pll_driver,
1121 aw_pll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);