2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk.h>
50 #include <arm/allwinner/aw_machdep.h>
52 #include "clkdev_if.h"
54 #define SUN4I_A10_PLL2_1X 0
55 #define SUN4I_A10_PLL2_2X 1
56 #define SUN4I_A10_PLL2_4X 2
57 #define SUN4I_A10_PLL2_8X 3
59 #define AW_PLL_ENABLE (1 << 31)
61 #define A10_PLL1_OUT_EXT_DIVP (0x3 << 16)
62 #define A10_PLL1_OUT_EXT_DIVP_SHIFT 16
63 #define A10_PLL1_FACTOR_N (0x1f << 8)
64 #define A10_PLL1_FACTOR_N_SHIFT 8
65 #define A10_PLL1_FACTOR_K (0x3 << 4)
66 #define A10_PLL1_FACTOR_K_SHIFT 4
67 #define A10_PLL1_FACTOR_M (0x3 << 0)
68 #define A10_PLL1_FACTOR_M_SHIFT 0
70 #define A10_PLL2_POST_DIV (0xf << 26)
71 #define A10_PLL2_POST_DIV_SHIFT 26
72 #define A10_PLL2_FACTOR_N (0x7f << 8)
73 #define A10_PLL2_FACTOR_N_SHIFT 8
74 #define A10_PLL2_PRE_DIV (0x1f << 0)
75 #define A10_PLL2_PRE_DIV_SHIFT 0
77 #define A10_PLL3_MODE_SEL (0x1 << 15)
78 #define A10_PLL3_MODE_SEL_FRACT (0 << 15)
79 #define A10_PLL3_MODE_SEL_INT (1 << 15)
80 #define A10_PLL3_FUNC_SET (0x1 << 14)
81 #define A10_PLL3_FUNC_SET_270MHZ (0 << 14)
82 #define A10_PLL3_FUNC_SET_297MHZ (1 << 14)
83 #define A10_PLL3_FACTOR_M (0x7f << 0)
84 #define A10_PLL3_FACTOR_M_SHIFT 0
85 #define A10_PLL3_REF_FREQ 3000000
87 #define A10_PLL5_OUT_EXT_DIVP (0x3 << 16)
88 #define A10_PLL5_OUT_EXT_DIVP_SHIFT 16
89 #define A10_PLL5_FACTOR_N (0x1f << 8)
90 #define A10_PLL5_FACTOR_N_SHIFT 8
91 #define A10_PLL5_FACTOR_K (0x3 << 4)
92 #define A10_PLL5_FACTOR_K_SHIFT 4
93 #define A10_PLL5_FACTOR_M1 (0x3 << 2)
94 #define A10_PLL5_FACTOR_M1_SHIFT 2
95 #define A10_PLL5_FACTOR_M (0x3 << 0)
96 #define A10_PLL5_FACTOR_M_SHIFT 0
98 #define A10_PLL6_BYPASS_EN (1 << 30)
99 #define A10_PLL6_SATA_CLK_EN (1 << 14)
100 #define A10_PLL6_FACTOR_N (0x1f << 8)
101 #define A10_PLL6_FACTOR_N_SHIFT 8
102 #define A10_PLL6_FACTOR_K (0x3 << 4)
103 #define A10_PLL6_FACTOR_K_SHIFT 4
104 #define A10_PLL6_FACTOR_M (0x3 << 0)
105 #define A10_PLL6_FACTOR_M_SHIFT 0
107 #define A10_PLL2_POST_DIV (0xf << 26)
109 #define A13_PLL2_POST_DIV (0xf << 26)
110 #define A13_PLL2_POST_DIV_SHIFT 26
111 #define A13_PLL2_FACTOR_N (0x7f << 8)
112 #define A13_PLL2_FACTOR_N_SHIFT 8
113 #define A13_PLL2_PRE_DIV (0x1f << 0)
114 #define A13_PLL2_PRE_DIV_SHIFT 0
116 #define A23_PLL1_FACTOR_P (0x3 << 16)
117 #define A23_PLL1_FACTOR_P_SHIFT 16
118 #define A23_PLL1_FACTOR_N (0x1f << 8)
119 #define A23_PLL1_FACTOR_N_SHIFT 8
120 #define A23_PLL1_FACTOR_K (0x3 << 4)
121 #define A23_PLL1_FACTOR_K_SHIFT 4
122 #define A23_PLL1_FACTOR_M (0x3 << 0)
123 #define A23_PLL1_FACTOR_M_SHIFT 0
125 #define A31_PLL1_LOCK (1 << 28)
126 #define A31_PLL1_CPU_SIGMA_DELTA_EN (1 << 24)
127 #define A31_PLL1_FACTOR_N (0x1f << 8)
128 #define A31_PLL1_FACTOR_N_SHIFT 8
129 #define A31_PLL1_FACTOR_K (0x3 << 4)
130 #define A31_PLL1_FACTOR_K_SHIFT 4
131 #define A31_PLL1_FACTOR_M (0x3 << 0)
132 #define A31_PLL1_FACTOR_M_SHIFT 0
134 #define A31_PLL6_LOCK (1 << 28)
135 #define A31_PLL6_BYPASS_EN (1 << 25)
136 #define A31_PLL6_CLK_OUT_EN (1 << 24)
137 #define A31_PLL6_24M_OUT_EN (1 << 18)
138 #define A31_PLL6_24M_POST_DIV (0x3 << 16)
139 #define A31_PLL6_24M_POST_DIV_SHIFT 16
140 #define A31_PLL6_FACTOR_N (0x1f << 8)
141 #define A31_PLL6_FACTOR_N_SHIFT 8
142 #define A31_PLL6_FACTOR_K (0x3 << 4)
143 #define A31_PLL6_FACTOR_K_SHIFT 4
144 #define A31_PLL6_DEFAULT_N 0x18
145 #define A31_PLL6_DEFAULT_K 0x1
146 #define A31_PLL6_TIMEOUT 10
148 #define A64_PLLHSIC_LOCK (1 << 28)
149 #define A64_PLLHSIC_FRAC_CLK_OUT (1 << 25)
150 #define A64_PLLHSIC_PLL_MODE_SEL (1 << 24)
151 #define A64_PLLHSIC_PLL_SDM_EN (1 << 20)
152 #define A64_PLLHSIC_FACTOR_N (0x7f << 8)
153 #define A64_PLLHSIC_FACTOR_N_SHIFT 8
154 #define A64_PLLHSIC_PRE_DIV_M (0xf << 0)
155 #define A64_PLLHSIC_PRE_DIV_M_SHIFT 0
157 #define A80_PLL4_CLK_OUT_EN (1 << 20)
158 #define A80_PLL4_PLL_DIV2 (1 << 18)
159 #define A80_PLL4_PLL_DIV1 (1 << 16)
160 #define A80_PLL4_FACTOR_N (0xff << 8)
161 #define A80_PLL4_FACTOR_N_SHIFT 8
163 #define A83T_PLLCPUX_LOCK_TIME (0x7 << 24)
164 #define A83T_PLLCPUX_LOCK_TIME_SHIFT 24
165 #define A83T_PLLCPUX_CLOCK_OUTPUT_DIS (1 << 20)
166 #define A83T_PLLCPUX_OUT_EXT_DIVP (1 << 16)
167 #define A83T_PLLCPUX_FACTOR_N (0xff << 8)
168 #define A83T_PLLCPUX_FACTOR_N_SHIFT 8
169 #define A83T_PLLCPUX_FACTOR_N_MIN 12
170 #define A83T_PLLCPUX_FACTOR_N_MAX 125
171 #define A83T_PLLCPUX_POSTDIV_M (0x3 << 0)
172 #define A83T_PLLCPUX_POSTDIV_M_SHIFT 0
174 #define H3_PLL2_LOCK (1 << 28)
175 #define H3_PLL2_SDM_EN (1 << 24)
176 #define H3_PLL2_POST_DIV (0xf << 16)
177 #define H3_PLL2_POST_DIV_SHIFT 16
178 #define H3_PLL2_FACTOR_N (0x7f << 8)
179 #define H3_PLL2_FACTOR_N_SHIFT 8
180 #define H3_PLL2_PRE_DIV (0x1f << 0)
181 #define H3_PLL2_PRE_DIV_SHIFT 0
183 #define CLKID_A10_PLL5_DDR 0
184 #define CLKID_A10_PLL5_OTHER 1
186 #define CLKID_A10_PLL6_SATA 0
187 #define CLKID_A10_PLL6_OTHER 1
188 #define CLKID_A10_PLL6 2
189 #define CLKID_A10_PLL6_DIV_4 3
191 #define CLKID_A31_PLL6 0
192 #define CLKID_A31_PLL6_X2 1
194 struct aw_pll_factor {
201 #define PLLFACTOR(_n, _k, _m, _p, _freq) \
202 { .n = (_n), .k = (_k), .m = (_m), .p = (_p), .freq = (_freq) }
204 static struct aw_pll_factor aw_a10_pll1_factors[] = {
205 PLLFACTOR(6, 0, 0, 0, 144000000),
206 PLLFACTOR(12, 0, 0, 0, 312000000),
207 PLLFACTOR(21, 0, 0, 0, 528000000),
208 PLLFACTOR(29, 0, 0, 0, 720000000),
209 PLLFACTOR(18, 1, 0, 0, 864000000),
210 PLLFACTOR(19, 1, 0, 0, 912000000),
211 PLLFACTOR(20, 1, 0, 0, 960000000),
214 static struct aw_pll_factor aw_a23_pll1_factors[] = {
215 PLLFACTOR(9, 0, 0, 2, 60000000),
216 PLLFACTOR(10, 0, 0, 2, 66000000),
217 PLLFACTOR(11, 0, 0, 2, 72000000),
218 PLLFACTOR(12, 0, 0, 2, 78000000),
219 PLLFACTOR(13, 0, 0, 2, 84000000),
220 PLLFACTOR(14, 0, 0, 2, 90000000),
221 PLLFACTOR(15, 0, 0, 2, 96000000),
222 PLLFACTOR(16, 0, 0, 2, 102000000),
223 PLLFACTOR(17, 0, 0, 2, 108000000),
224 PLLFACTOR(18, 0, 0, 2, 114000000),
225 PLLFACTOR(9, 0, 0, 1, 120000000),
226 PLLFACTOR(10, 0, 0, 1, 132000000),
227 PLLFACTOR(11, 0, 0, 1, 144000000),
228 PLLFACTOR(12, 0, 0, 1, 156000000),
229 PLLFACTOR(13, 0, 0, 1, 168000000),
230 PLLFACTOR(14, 0, 0, 1, 180000000),
231 PLLFACTOR(15, 0, 0, 1, 192000000),
232 PLLFACTOR(16, 0, 0, 1, 204000000),
233 PLLFACTOR(17, 0, 0, 1, 216000000),
234 PLLFACTOR(18, 0, 0, 1, 228000000),
235 PLLFACTOR(9, 0, 0, 0, 240000000),
236 PLLFACTOR(10, 0, 0, 0, 264000000),
237 PLLFACTOR(11, 0, 0, 0, 288000000),
238 PLLFACTOR(12, 0, 0, 0, 312000000),
239 PLLFACTOR(13, 0, 0, 0, 336000000),
240 PLLFACTOR(14, 0, 0, 0, 360000000),
241 PLLFACTOR(15, 0, 0, 0, 384000000),
242 PLLFACTOR(16, 0, 0, 0, 408000000),
243 PLLFACTOR(17, 0, 0, 0, 432000000),
244 PLLFACTOR(18, 0, 0, 0, 456000000),
245 PLLFACTOR(19, 0, 0, 0, 480000000),
246 PLLFACTOR(20, 0, 0, 0, 504000000),
247 PLLFACTOR(21, 0, 0, 0, 528000000),
248 PLLFACTOR(22, 0, 0, 0, 552000000),
249 PLLFACTOR(23, 0, 0, 0, 576000000),
250 PLLFACTOR(24, 0, 0, 0, 600000000),
251 PLLFACTOR(25, 0, 0, 0, 624000000),
252 PLLFACTOR(26, 0, 0, 0, 648000000),
253 PLLFACTOR(27, 0, 0, 0, 672000000),
254 PLLFACTOR(28, 0, 0, 0, 696000000),
255 PLLFACTOR(29, 0, 0, 0, 720000000),
256 PLLFACTOR(15, 1, 0, 0, 768000000),
257 PLLFACTOR(10, 2, 0, 0, 792000000),
258 PLLFACTOR(16, 1, 0, 0, 816000000),
259 PLLFACTOR(17, 1, 0, 0, 864000000),
260 PLLFACTOR(18, 1, 0, 0, 912000000),
261 PLLFACTOR(12, 2, 0, 0, 936000000),
262 PLLFACTOR(19, 1, 0, 0, 960000000),
263 PLLFACTOR(20, 1, 0, 0, 1008000000),
264 PLLFACTOR(21, 1, 0, 0, 1056000000),
265 PLLFACTOR(14, 2, 0, 0, 1080000000),
266 PLLFACTOR(22, 1, 0, 0, 1104000000),
267 PLLFACTOR(23, 1, 0, 0, 1152000000),
268 PLLFACTOR(24, 1, 0, 0, 1200000000),
269 PLLFACTOR(16, 2, 0, 0, 1224000000),
270 PLLFACTOR(25, 1, 0, 0, 1248000000),
271 PLLFACTOR(26, 1, 0, 0, 1296000000),
272 PLLFACTOR(27, 1, 0, 0, 1344000000),
273 PLLFACTOR(18, 2, 0, 0, 1368000000),
274 PLLFACTOR(28, 1, 0, 0, 1392000000),
275 PLLFACTOR(29, 1, 0, 0, 1440000000),
276 PLLFACTOR(20, 2, 0, 0, 1512000000),
277 PLLFACTOR(15, 3, 0, 0, 1536000000),
278 PLLFACTOR(21, 2, 0, 0, 1584000000),
279 PLLFACTOR(16, 3, 0, 0, 1632000000),
280 PLLFACTOR(22, 2, 0, 0, 1656000000),
281 PLLFACTOR(23, 2, 0, 0, 1728000000),
282 PLLFACTOR(24, 2, 0, 0, 1800000000),
283 PLLFACTOR(18, 3, 0, 0, 1824000000),
284 PLLFACTOR(25, 2, 0, 0, 1872000000),
287 static struct aw_pll_factor aw_h3_pll2_factors[] = {
288 PLLFACTOR(13, 0, 0, 13, 24576000),
289 PLLFACTOR(6, 0, 0, 7, 22579200),
310 enum aw_pll_type type;
316 struct aw_pll_funcs {
317 int (*recalc)(struct aw_pll_sc *, uint64_t *);
318 int (*set_freq)(struct aw_pll_sc *, uint64_t, uint64_t *, int);
319 int (*init)(device_t, bus_addr_t, struct clknode_init_def *);
322 #define PLL_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
323 #define PLL_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
324 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
325 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
328 a10_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
331 struct aw_pll_factor *f;
336 for (n = 0; n < nitems(aw_a10_pll1_factors); n++) {
337 if (aw_a10_pll1_factors[n].freq == *fout) {
338 f = &aw_a10_pll1_factors[n];
347 val &= ~(A10_PLL1_FACTOR_N|A10_PLL1_FACTOR_K|A10_PLL1_FACTOR_M|
348 A10_PLL1_OUT_EXT_DIVP);
349 val |= (f->p << A10_PLL1_OUT_EXT_DIVP_SHIFT);
350 val |= (f->n << A10_PLL1_FACTOR_N_SHIFT);
351 val |= (f->k << A10_PLL1_FACTOR_K_SHIFT);
352 val |= (f->m << A10_PLL1_FACTOR_M_SHIFT);
360 a10_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
362 uint32_t val, m, n, k, p;
368 p = 1 << ((val & A10_PLL1_OUT_EXT_DIVP) >> A10_PLL1_OUT_EXT_DIVP_SHIFT);
369 m = ((val & A10_PLL1_FACTOR_M) >> A10_PLL1_FACTOR_M_SHIFT) + 1;
370 k = ((val & A10_PLL1_FACTOR_K) >> A10_PLL1_FACTOR_K_SHIFT) + 1;
371 n = (val & A10_PLL1_FACTOR_N) >> A10_PLL1_FACTOR_N_SHIFT;
375 *freq = (*freq * n * k) / (m * p);
381 a10_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
383 uint32_t val, post_div, n, pre_div;
389 post_div = (val & A10_PLL2_POST_DIV) >> A10_PLL2_POST_DIV_SHIFT;
392 n = (val & A10_PLL2_FACTOR_N) >> A10_PLL2_FACTOR_N_SHIFT;
395 pre_div = (val & A10_PLL2_PRE_DIV) >> A10_PLL2_PRE_DIV_SHIFT;
400 case SUN4I_A10_PLL2_1X:
401 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
403 case SUN4I_A10_PLL2_2X:
404 *freq = (*freq * 2 * n) / pre_div / 4;
406 case SUN4I_A10_PLL2_4X:
407 *freq = (*freq * 2 * n) / pre_div / 2;
409 case SUN4I_A10_PLL2_8X:
410 *freq = (*freq * 2 * n) / pre_div;
420 a10_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
423 uint32_t val, post_div, n, pre_div;
425 if (sc->id != SUN4I_A10_PLL2_1X)
429 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
431 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
432 * To get as close as possible to the desired rate, we use a
433 * pre-divider of 21 and a post-divider of 4. With these values,
434 * a multiplier of 86 or 79 gets us close to the target rates.
436 if (*fout != 24576000 && *fout != 22579200)
441 n = (*fout * pre_div * post_div * 2) / (2 * fin);
445 val &= ~(A10_PLL2_POST_DIV | A10_PLL2_FACTOR_N | A10_PLL2_PRE_DIV);
446 val |= (post_div << A10_PLL2_POST_DIV_SHIFT);
447 val |= (n << A10_PLL2_FACTOR_N_SHIFT);
448 val |= (pre_div << A10_PLL2_PRE_DIV_SHIFT);
456 a10_pll3_recalc(struct aw_pll_sc *sc, uint64_t *freq)
464 if ((val & A10_PLL3_MODE_SEL) == A10_PLL3_MODE_SEL_INT) {
465 /* In integer mode, output is 3MHz * m */
466 m = (val & A10_PLL3_FACTOR_M) >> A10_PLL3_FACTOR_M_SHIFT;
467 *freq = A10_PLL3_REF_FREQ * m;
469 /* In fractional mode, output is either 270MHz or 297MHz */
470 if ((val & A10_PLL3_FUNC_SET) == A10_PLL3_FUNC_SET_270MHZ)
480 a10_pll3_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
483 uint32_t val, m, mode, func;
485 if (*fout == 297000000) {
486 func = A10_PLL3_FUNC_SET_297MHZ;
487 mode = A10_PLL3_MODE_SEL_FRACT;
489 } else if (*fout == 270000000) {
490 func = A10_PLL3_FUNC_SET_270MHZ;
491 mode = A10_PLL3_MODE_SEL_FRACT;
494 mode = A10_PLL3_MODE_SEL_INT;
496 m = *fout / A10_PLL3_REF_FREQ;
497 *fout = m * A10_PLL3_REF_FREQ;
502 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
505 val |= (m << A10_PLL3_FACTOR_M_SHIFT);
513 a10_pll3_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
517 /* Allow changing PLL frequency while enabled */
518 def->flags = CLK_NODE_GLITCH_FREE;
520 /* Set PLL to 297MHz */
521 CLKDEV_DEVICE_LOCK(dev);
522 CLKDEV_READ_4(dev, reg, &val);
523 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
524 val |= A10_PLL3_MODE_SEL_FRACT;
525 val |= A10_PLL3_FUNC_SET_297MHZ;
526 CLKDEV_WRITE_4(dev, reg, val);
527 CLKDEV_DEVICE_UNLOCK(dev);
533 a10_pll5_recalc(struct aw_pll_sc *sc, uint64_t *freq)
535 uint32_t val, m, n, k, p;
541 p = 1 << ((val & A10_PLL5_OUT_EXT_DIVP) >> A10_PLL5_OUT_EXT_DIVP_SHIFT);
542 m = ((val & A10_PLL5_FACTOR_M) >> A10_PLL5_FACTOR_M_SHIFT) + 1;
543 k = ((val & A10_PLL5_FACTOR_K) >> A10_PLL5_FACTOR_K_SHIFT) + 1;
544 n = (val & A10_PLL5_FACTOR_N) >> A10_PLL5_FACTOR_N_SHIFT;
549 case CLKID_A10_PLL5_DDR:
550 *freq = (*freq * n * k) / m;
552 case CLKID_A10_PLL5_OTHER:
553 *freq = (*freq * n * k) / p;
563 a10_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
565 uint32_t val, m, n, k;
568 * SATA needs PLL6 to be a 100MHz clock.
570 * The SATA output frequency is (24MHz * n * k) / m / 6.
571 * To get to 100MHz, k & m must be equal and n must be 25.
576 CLKDEV_DEVICE_LOCK(dev);
577 CLKDEV_READ_4(dev, reg, &val);
578 val &= ~(A10_PLL6_FACTOR_N | A10_PLL6_FACTOR_K | A10_PLL6_FACTOR_M);
579 val &= ~A10_PLL6_BYPASS_EN;
580 val |= A10_PLL6_SATA_CLK_EN;
581 val |= (n << A10_PLL6_FACTOR_N_SHIFT);
582 val |= (k << A10_PLL6_FACTOR_K_SHIFT);
583 val |= (m << A10_PLL6_FACTOR_M_SHIFT);
584 CLKDEV_WRITE_4(dev, reg, val);
585 CLKDEV_DEVICE_UNLOCK(dev);
591 a10_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
593 uint32_t val, m, k, n;
599 m = ((val & A10_PLL6_FACTOR_M) >> A10_PLL6_FACTOR_M_SHIFT) + 1;
600 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
601 n = (val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT;
606 case CLKID_A10_PLL6_SATA:
607 *freq = (*freq * n * k) / m / 6;
609 case CLKID_A10_PLL6_OTHER:
610 *freq = (*freq * n * k) / 2;
613 *freq = (*freq * n * k);
615 case CLKID_A10_PLL6_DIV_4:
616 *freq = (*freq * n * k) / 4;
626 a10_pll6_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
629 if (sc->id != CLKID_A10_PLL6_SATA)
632 /* PLL6 SATA output has been set to 100MHz in a10_pll6_init */
633 if (*fout != 100000000)
640 a13_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
642 uint32_t val, post_div, n, pre_div;
648 post_div = ((val & A13_PLL2_POST_DIV) >> A13_PLL2_POST_DIV_SHIFT) + 1;
651 n = (val & A13_PLL2_FACTOR_N) >> A13_PLL2_FACTOR_N_SHIFT;
654 pre_div = ((val & A13_PLL2_PRE_DIV) >> A13_PLL2_PRE_DIV_SHIFT) + 1;
659 case SUN4I_A10_PLL2_1X:
660 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
662 case SUN4I_A10_PLL2_2X:
663 *freq = (*freq * 2 * n) / pre_div / 4;
665 case SUN4I_A10_PLL2_4X:
666 *freq = (*freq * 2 * n) / pre_div / 2;
668 case SUN4I_A10_PLL2_8X:
669 *freq = (*freq * 2 * n) / pre_div;
679 a13_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
682 uint32_t val, post_div, n, pre_div;
684 if (sc->id != SUN4I_A10_PLL2_1X)
688 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
690 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
691 * To get as close as possible to the desired rate, we use a
692 * pre-divider of 21 and a post-divider of 4. With these values,
693 * a multiplier of 86 or 79 gets us close to the target rates.
695 if (*fout != 24576000 && *fout != 22579200)
700 n = (*fout * pre_div * post_div * 2) / (2 * fin);
704 val &= ~(A13_PLL2_POST_DIV | A13_PLL2_FACTOR_N | A13_PLL2_PRE_DIV);
705 val |= ((post_div - 1) << A13_PLL2_POST_DIV_SHIFT);
706 val |= (n << A13_PLL2_FACTOR_N_SHIFT);
707 val |= ((pre_div - 1) << A13_PLL2_PRE_DIV_SHIFT);
715 h3_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
717 uint32_t val, p, n, m;
723 p = ((val & H3_PLL2_POST_DIV) >> H3_PLL2_POST_DIV_SHIFT) + 1;
724 n = ((val & H3_PLL2_FACTOR_N) >> H3_PLL2_FACTOR_N_SHIFT) + 1;
725 m = ((val & H3_PLL2_PRE_DIV) >> H3_PLL2_PRE_DIV_SHIFT) + 1;
728 case SUN4I_A10_PLL2_1X:
729 *freq = (*freq * n) / (m * p);
731 case SUN4I_A10_PLL2_2X:
732 *freq = (*freq * 2 * n) / m / 4;
734 case SUN4I_A10_PLL2_4X:
735 *freq = (*freq * 2 * n) / m / 2;
737 case SUN4I_A10_PLL2_8X:
738 *freq = (*freq * 2 * n) / m;
748 h3_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
751 struct aw_pll_factor *f;
755 if (sc->id != SUN4I_A10_PLL2_1X)
759 for (n = 0; n < nitems(aw_h3_pll2_factors); n++) {
760 if (aw_h3_pll2_factors[n].freq == *fout) {
761 f = &aw_h3_pll2_factors[n];
770 val &= ~(H3_PLL2_POST_DIV|H3_PLL2_FACTOR_N|H3_PLL2_PRE_DIV);
771 val |= (f->p << H3_PLL2_POST_DIV_SHIFT);
772 val |= (f->n << H3_PLL2_FACTOR_N_SHIFT);
773 val |= (f->m << H3_PLL2_PRE_DIV_SHIFT);
774 val |= AW_PLL_ENABLE;
779 for (retry = 0; retry < 1000; retry++) {
781 if ((val & H3_PLL2_LOCK) != 0)
794 a23_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
797 struct aw_pll_factor *f;
802 for (n = 0; n < nitems(aw_a23_pll1_factors); n++) {
803 if (aw_a23_pll1_factors[n].freq == *fout) {
804 f = &aw_a23_pll1_factors[n];
813 val &= ~(A23_PLL1_FACTOR_N|A23_PLL1_FACTOR_K|A23_PLL1_FACTOR_M|
815 val |= (f->n << A23_PLL1_FACTOR_N_SHIFT);
816 val |= (f->k << A23_PLL1_FACTOR_K_SHIFT);
817 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
818 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
827 a23_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
829 uint32_t val, m, n, k, p;
835 m = ((val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT) + 1;
836 k = ((val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT) + 1;
837 n = ((val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT) + 1;
838 p = ((val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT) + 1;
840 *freq = (*freq * n * k) / (m * p);
846 h3_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
849 struct aw_pll_factor *f;
850 uint32_t val, n, k, m, p;
854 for (i = 0; i < nitems(aw_a23_pll1_factors); i++) {
855 if (aw_a23_pll1_factors[i].freq == *fout) {
856 f = &aw_a23_pll1_factors[i];
866 n = (val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT;
867 k = (val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT;
868 m = (val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT;
869 p = (val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT;
872 val &= ~A23_PLL1_FACTOR_P;
873 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
879 val &= ~A23_PLL1_FACTOR_M;
880 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
885 val &= ~(A23_PLL1_FACTOR_N|A23_PLL1_FACTOR_K);
886 val |= (f->n << A23_PLL1_FACTOR_N_SHIFT);
887 val |= (f->k << A23_PLL1_FACTOR_K_SHIFT);
892 val &= ~A23_PLL1_FACTOR_M;
893 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
899 val &= ~A23_PLL1_FACTOR_P;
900 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
912 a31_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
914 uint32_t val, m, n, k;
920 m = ((val & A31_PLL1_FACTOR_M) >> A31_PLL1_FACTOR_M_SHIFT) + 1;
921 k = ((val & A31_PLL1_FACTOR_K) >> A31_PLL1_FACTOR_K_SHIFT) + 1;
922 n = ((val & A31_PLL1_FACTOR_N) >> A31_PLL1_FACTOR_N_SHIFT) + 1;
924 *freq = (*freq * n * k) / m;
930 a31_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
935 if (def->id != CLKID_A31_PLL6)
939 * The datasheet recommends that PLL6 output should be fixed to
942 CLKDEV_DEVICE_LOCK(dev);
943 CLKDEV_READ_4(dev, reg, &val);
944 val &= ~(A31_PLL6_FACTOR_N | A31_PLL6_FACTOR_K | A31_PLL6_BYPASS_EN);
945 val |= (A31_PLL6_DEFAULT_N << A31_PLL6_FACTOR_N_SHIFT);
946 val |= (A31_PLL6_DEFAULT_K << A31_PLL6_FACTOR_K_SHIFT);
947 val |= AW_PLL_ENABLE;
948 CLKDEV_WRITE_4(dev, reg, val);
950 /* Wait for PLL to become stable */
951 for (retry = A31_PLL6_TIMEOUT; retry > 0; retry--) {
952 CLKDEV_READ_4(dev, reg, &val);
953 if ((val & A31_PLL6_LOCK) == A31_PLL6_LOCK)
958 CLKDEV_DEVICE_UNLOCK(dev);
964 a31_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
972 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
973 n = ((val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT) + 1;
977 *freq = (*freq * n * k) / 2;
979 case CLKID_A31_PLL6_X2:
980 *freq = *freq * n * k;
990 a80_pll4_recalc(struct aw_pll_sc *sc, uint64_t *freq)
992 uint32_t val, n, div1, div2;
998 n = (val & A80_PLL4_FACTOR_N) >> A80_PLL4_FACTOR_N_SHIFT;
999 div1 = (val & A80_PLL4_PLL_DIV1) == 0 ? 1 : 2;
1000 div2 = (val & A80_PLL4_PLL_DIV2) == 0 ? 1 : 2;
1002 *freq = (*freq * n) / div1 / div2;
1008 a64_pllhsic_recalc(struct aw_pll_sc *sc, uint64_t *freq)
1016 n = ((val & A64_PLLHSIC_FACTOR_N) >> A64_PLLHSIC_FACTOR_N_SHIFT) + 1;
1017 m = ((val & A64_PLLHSIC_PRE_DIV_M) >> A64_PLLHSIC_PRE_DIV_M_SHIFT) + 1;
1019 *freq = (*freq * n) / m;
1025 a64_pllhsic_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
1030 * PLL_HSIC default is 480MHz, just enable it.
1032 CLKDEV_DEVICE_LOCK(dev);
1033 CLKDEV_READ_4(dev, reg, &val);
1034 val |= AW_PLL_ENABLE;
1035 CLKDEV_WRITE_4(dev, reg, val);
1036 CLKDEV_DEVICE_UNLOCK(dev);
1042 a83t_pllcpux_recalc(struct aw_pll_sc *sc, uint64_t *freq)
1050 n = (val & A83T_PLLCPUX_FACTOR_N) >> A83T_PLLCPUX_FACTOR_N_SHIFT;
1051 p = (val & A83T_PLLCPUX_OUT_EXT_DIVP) ? 4 : 1;
1053 *freq = (*freq * n) / p;
1059 a83t_pllcpux_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
1067 if (n < A83T_PLLCPUX_FACTOR_N_MIN || n > A83T_PLLCPUX_FACTOR_N_MAX)
1072 val &= ~A83T_PLLCPUX_FACTOR_N;
1073 val |= (n << A83T_PLLCPUX_FACTOR_N_SHIFT);
1074 val &= ~A83T_PLLCPUX_CLOCK_OUTPUT_DIS;
1081 #define PLL(_type, _recalc, _set_freq, _init) \
1083 .recalc = (_recalc), \
1084 .set_freq = (_set_freq), \
1088 static struct aw_pll_funcs aw_pll_func[] = {
1089 PLL(AWPLL_A10_PLL1, a10_pll1_recalc, a10_pll1_set_freq, NULL),
1090 PLL(AWPLL_A10_PLL2, a10_pll2_recalc, a10_pll2_set_freq, NULL),
1091 PLL(AWPLL_A10_PLL3, a10_pll3_recalc, a10_pll3_set_freq, a10_pll3_init),
1092 PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL),
1093 PLL(AWPLL_A10_PLL6, a10_pll6_recalc, a10_pll6_set_freq, a10_pll6_init),
1094 PLL(AWPLL_A13_PLL2, a13_pll2_recalc, a13_pll2_set_freq, NULL),
1095 PLL(AWPLL_A23_PLL1, a23_pll1_recalc, a23_pll1_set_freq, NULL),
1096 PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL),
1097 PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init),
1098 PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),
1099 PLL(AWPLL_A83T_PLLCPUX, a83t_pllcpux_recalc, a83t_pllcpux_set_freq, NULL),
1100 PLL(AWPLL_A64_PLLHSIC, a64_pllhsic_recalc, NULL, a64_pllhsic_init),
1101 PLL(AWPLL_H3_PLL1, a23_pll1_recalc, h3_pll1_set_freq, NULL),
1102 PLL(AWPLL_H3_PLL2, h3_pll2_recalc, h3_pll2_set_freq, NULL),
1105 static struct ofw_compat_data compat_data[] = {
1106 { "allwinner,sun4i-a10-pll1-clk", AWPLL_A10_PLL1 },
1107 { "allwinner,sun4i-a10-pll2-clk", AWPLL_A10_PLL2 },
1108 { "allwinner,sun4i-a10-pll3-clk", AWPLL_A10_PLL3 },
1109 { "allwinner,sun4i-a10-pll5-clk", AWPLL_A10_PLL5 },
1110 { "allwinner,sun4i-a10-pll6-clk", AWPLL_A10_PLL6 },
1111 { "allwinner,sun5i-a13-pll2-clk", AWPLL_A13_PLL2 },
1112 { "allwinner,sun6i-a31-pll1-clk", AWPLL_A31_PLL1 },
1113 { "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 },
1114 { "allwinner,sun8i-a23-pll1-clk", AWPLL_A23_PLL1 },
1115 { "allwinner,sun8i-a83t-pllcpux-clk", AWPLL_A83T_PLLCPUX },
1116 { "allwinner,sun8i-h3-pll1-clk", AWPLL_H3_PLL1 },
1117 { "allwinner,sun8i-h3-pll2-clk", AWPLL_H3_PLL2 },
1118 { "allwinner,sun9i-a80-pll4-clk", AWPLL_A80_PLL4 },
1119 { "allwinner,sun50i-a64-pllhsic-clk", AWPLL_A64_PLLHSIC },
1124 aw_pll_init(struct clknode *clk, device_t dev)
1126 clknode_init_parent_idx(clk, 0);
1131 aw_pll_set_gate(struct clknode *clk, bool enable)
1133 struct aw_pll_sc *sc;
1136 sc = clknode_get_softc(clk);
1141 val |= AW_PLL_ENABLE;
1143 val &= ~AW_PLL_ENABLE;
1151 aw_pll_recalc(struct clknode *clk, uint64_t *freq)
1153 struct aw_pll_sc *sc;
1155 sc = clknode_get_softc(clk);
1157 if (aw_pll_func[sc->type].recalc == NULL)
1160 return (aw_pll_func[sc->type].recalc(sc, freq));
1164 aw_pll_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
1165 int flags, int *stop)
1167 struct aw_pll_sc *sc;
1169 sc = clknode_get_softc(clk);
1173 if (aw_pll_func[sc->type].set_freq == NULL)
1176 return (aw_pll_func[sc->type].set_freq(sc, fin, fout, flags));
1179 static clknode_method_t aw_pll_clknode_methods[] = {
1180 /* Device interface */
1181 CLKNODEMETHOD(clknode_init, aw_pll_init),
1182 CLKNODEMETHOD(clknode_set_gate, aw_pll_set_gate),
1183 CLKNODEMETHOD(clknode_recalc_freq, aw_pll_recalc),
1184 CLKNODEMETHOD(clknode_set_freq, aw_pll_set_freq),
1188 DEFINE_CLASS_1(aw_pll_clknode, aw_pll_clknode_class, aw_pll_clknode_methods,
1189 sizeof(struct aw_pll_sc), clknode_class);
1192 aw_pll_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
1193 const char *pclkname, const char *clkname, int index)
1195 enum aw_pll_type type;
1196 struct clknode_init_def clkdef;
1197 struct aw_pll_sc *sc;
1198 struct clknode *clk;
1201 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1203 memset(&clkdef, 0, sizeof(clkdef));
1205 clkdef.name = clkname;
1206 if (pclkname != NULL) {
1207 clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP,
1209 clkdef.parent_names[0] = pclkname;
1210 clkdef.parent_cnt = 1;
1212 clkdef.parent_cnt = 0;
1214 if (aw_pll_func[type].init != NULL) {
1215 error = aw_pll_func[type].init(device_get_parent(dev),
1218 device_printf(dev, "clock %s init failed\n", clkname);
1223 clk = clknode_create(clkdom, &aw_pll_clknode_class, &clkdef);
1225 device_printf(dev, "cannot create clock node\n");
1228 sc = clknode_get_softc(clk);
1229 sc->clkdev = device_get_parent(dev);
1234 clknode_register(clkdom, clk);
1236 OF_prop_free(__DECONST(char *, clkdef.parent_names));
1242 aw_pll_probe(device_t dev)
1244 if (!ofw_bus_status_okay(dev))
1247 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1250 device_set_desc(dev, "Allwinner PLL Clock");
1251 return (BUS_PROBE_DEFAULT);
1255 aw_pll_attach(device_t dev)
1257 struct clkdom *clkdom;
1259 int index, nout, error;
1266 node = ofw_bus_get_node(dev);
1268 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
1269 device_printf(dev, "couldn't parse 'reg' property\n");
1273 clkdom = clkdom_create(dev);
1275 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
1277 device_printf(dev, "no clock outputs found\n");
1282 if (clk_get_by_ofw_index(dev, 0, 0, &clk_parent) != 0)
1285 for (index = 0; index < nout; index++) {
1286 error = aw_pll_create(dev, paddr, clkdom,
1287 clk_parent ? clk_get_name(clk_parent) : NULL,
1288 names[index], nout == 1 ? 1 : index);
1293 if (clkdom_finit(clkdom) != 0) {
1294 device_printf(dev, "cannot finalize clkdom initialization\n");
1300 clkdom_dump(clkdom);
1308 static device_method_t aw_pll_methods[] = {
1309 /* Device interface */
1310 DEVMETHOD(device_probe, aw_pll_probe),
1311 DEVMETHOD(device_attach, aw_pll_attach),
1316 static driver_t aw_pll_driver = {
1322 static devclass_t aw_pll_devclass;
1324 EARLY_DRIVER_MODULE(aw_pll, simplebus, aw_pll_driver,
1325 aw_pll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);