2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk.h>
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
52 #include <arm/allwinner/aw_machdep.h>
54 #include "clkdev_if.h"
56 #define AW_PLL_ENABLE (1 << 31)
58 #define A10_PLL1_OUT_EXT_DIVP (0x3 << 16)
59 #define A10_PLL1_OUT_EXT_DIVP_SHIFT 16
60 #define A10_PLL1_FACTOR_N (0x1f << 8)
61 #define A10_PLL1_FACTOR_N_SHIFT 8
62 #define A10_PLL1_FACTOR_K (0x3 << 4)
63 #define A10_PLL1_FACTOR_K_SHIFT 4
64 #define A10_PLL1_FACTOR_M (0x3 << 0)
65 #define A10_PLL1_FACTOR_M_SHIFT 0
67 #define A10_PLL2_POST_DIV (0xf << 26)
68 #define A10_PLL2_POST_DIV_SHIFT 26
69 #define A10_PLL2_FACTOR_N (0x7f << 8)
70 #define A10_PLL2_FACTOR_N_SHIFT 8
71 #define A10_PLL2_PRE_DIV (0x1f << 0)
72 #define A10_PLL2_PRE_DIV_SHIFT 0
74 #define A10_PLL3_MODE_SEL (0x1 << 15)
75 #define A10_PLL3_MODE_SEL_FRACT (0 << 15)
76 #define A10_PLL3_MODE_SEL_INT (1 << 15)
77 #define A10_PLL3_FUNC_SET (0x1 << 14)
78 #define A10_PLL3_FUNC_SET_270MHZ (0 << 14)
79 #define A10_PLL3_FUNC_SET_297MHZ (1 << 14)
80 #define A10_PLL3_FACTOR_M (0x7f << 0)
81 #define A10_PLL3_FACTOR_M_SHIFT 0
82 #define A10_PLL3_REF_FREQ 3000000
84 #define A10_PLL5_OUT_EXT_DIVP (0x3 << 16)
85 #define A10_PLL5_OUT_EXT_DIVP_SHIFT 16
86 #define A10_PLL5_FACTOR_N (0x1f << 8)
87 #define A10_PLL5_FACTOR_N_SHIFT 8
88 #define A10_PLL5_FACTOR_K (0x3 << 4)
89 #define A10_PLL5_FACTOR_K_SHIFT 4
90 #define A10_PLL5_FACTOR_M1 (0x3 << 2)
91 #define A10_PLL5_FACTOR_M1_SHIFT 2
92 #define A10_PLL5_FACTOR_M (0x3 << 0)
93 #define A10_PLL5_FACTOR_M_SHIFT 0
95 #define A10_PLL6_BYPASS_EN (1 << 30)
96 #define A10_PLL6_SATA_CLK_EN (1 << 14)
97 #define A10_PLL6_FACTOR_N (0x1f << 8)
98 #define A10_PLL6_FACTOR_N_SHIFT 8
99 #define A10_PLL6_FACTOR_K (0x3 << 4)
100 #define A10_PLL6_FACTOR_K_SHIFT 4
101 #define A10_PLL6_FACTOR_M (0x3 << 0)
102 #define A10_PLL6_FACTOR_M_SHIFT 0
104 #define A10_PLL2_POST_DIV (0xf << 26)
106 #define A13_PLL2_POST_DIV (0xf << 26)
107 #define A13_PLL2_POST_DIV_SHIFT 26
108 #define A13_PLL2_FACTOR_N (0x7f << 8)
109 #define A13_PLL2_FACTOR_N_SHIFT 8
110 #define A13_PLL2_PRE_DIV (0x1f << 0)
111 #define A13_PLL2_PRE_DIV_SHIFT 0
113 #define A23_PLL1_FACTOR_N (0x1f << 8)
114 #define A23_PLL1_FACTOR_N_SHIFT 8
115 #define A23_PLL1_FACTOR_K (0x3 << 4)
116 #define A23_PLL1_FACTOR_K_SHIFT 4
117 #define A23_PLL1_FACTOR_M (0x3 << 0)
118 #define A23_PLL1_FACTOR_M_SHIFT 0
119 #define A23_PLL1_FACTOR_P (0x3 << 16)
120 #define A23_PLL1_FACTOR_P_SHIFT 16
122 #define A31_PLL1_LOCK (1 << 28)
123 #define A31_PLL1_CPU_SIGMA_DELTA_EN (1 << 24)
124 #define A31_PLL1_FACTOR_N (0x1f << 8)
125 #define A31_PLL1_FACTOR_N_SHIFT 8
126 #define A31_PLL1_FACTOR_K (0x3 << 4)
127 #define A31_PLL1_FACTOR_K_SHIFT 4
128 #define A31_PLL1_FACTOR_M (0x3 << 0)
129 #define A31_PLL1_FACTOR_M_SHIFT 0
131 #define A31_PLL6_LOCK (1 << 28)
132 #define A31_PLL6_BYPASS_EN (1 << 25)
133 #define A31_PLL6_CLK_OUT_EN (1 << 24)
134 #define A31_PLL6_24M_OUT_EN (1 << 18)
135 #define A31_PLL6_24M_POST_DIV (0x3 << 16)
136 #define A31_PLL6_24M_POST_DIV_SHIFT 16
137 #define A31_PLL6_FACTOR_N (0x1f << 8)
138 #define A31_PLL6_FACTOR_N_SHIFT 8
139 #define A31_PLL6_FACTOR_K (0x3 << 4)
140 #define A31_PLL6_FACTOR_K_SHIFT 4
141 #define A31_PLL6_DEFAULT_N 0x18
142 #define A31_PLL6_DEFAULT_K 0x1
143 #define A31_PLL6_TIMEOUT 10
145 #define A64_PLLHSIC_LOCK (1 << 28)
146 #define A64_PLLHSIC_FRAC_CLK_OUT (1 << 25)
147 #define A64_PLLHSIC_PLL_MODE_SEL (1 << 24)
148 #define A64_PLLHSIC_PLL_SDM_EN (1 << 20)
149 #define A64_PLLHSIC_FACTOR_N (0x7f << 8)
150 #define A64_PLLHSIC_FACTOR_N_SHIFT 8
151 #define A64_PLLHSIC_PRE_DIV_M (0xf << 0)
152 #define A64_PLLHSIC_PRE_DIV_M_SHIFT 0
154 #define A80_PLL4_CLK_OUT_EN (1 << 20)
155 #define A80_PLL4_PLL_DIV2 (1 << 18)
156 #define A80_PLL4_PLL_DIV1 (1 << 16)
157 #define A80_PLL4_FACTOR_N (0xff << 8)
158 #define A80_PLL4_FACTOR_N_SHIFT 8
160 #define CLKID_A10_PLL3_1X 0
161 #define CLKID_A10_PLL3_2X 1
163 #define CLKID_A10_PLL5_DDR 0
164 #define CLKID_A10_PLL5_OTHER 1
166 #define CLKID_A10_PLL6_SATA 0
167 #define CLKID_A10_PLL6_OTHER 1
168 #define CLKID_A10_PLL6 2
169 #define CLKID_A10_PLL6_DIV_4 3
171 #define CLKID_A31_PLL6 0
172 #define CLKID_A31_PLL6_X2 1
189 enum aw_pll_type type;
195 struct aw_pll_funcs {
196 int (*recalc)(struct aw_pll_sc *, uint64_t *);
197 int (*set_freq)(struct aw_pll_sc *, uint64_t, uint64_t *, int);
198 int (*init)(device_t, bus_addr_t, struct clknode_init_def *);
201 #define PLL_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
202 #define PLL_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
203 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
204 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
207 a10_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
209 uint32_t val, m, n, k, p;
215 p = 1 << ((val & A10_PLL1_OUT_EXT_DIVP) >> A10_PLL1_OUT_EXT_DIVP_SHIFT);
216 m = ((val & A10_PLL1_FACTOR_M) >> A10_PLL1_FACTOR_M_SHIFT) + 1;
217 k = ((val & A10_PLL1_FACTOR_K) >> A10_PLL1_FACTOR_K_SHIFT) + 1;
218 n = (val & A10_PLL1_FACTOR_N) >> A10_PLL1_FACTOR_N_SHIFT;
222 *freq = (*freq * n * k) / (m * p);
228 a10_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
230 uint32_t val, post_div, n, pre_div;
236 post_div = (val & A10_PLL2_POST_DIV) >> A10_PLL2_POST_DIV_SHIFT;
239 n = (val & A10_PLL2_FACTOR_N) >> A10_PLL2_FACTOR_N_SHIFT;
242 pre_div = (val & A10_PLL2_PRE_DIV) >> A10_PLL2_PRE_DIV_SHIFT;
247 case SUN4I_A10_PLL2_1X:
248 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
250 case SUN4I_A10_PLL2_2X:
251 *freq = (*freq * 2 * n) / pre_div / 4;
253 case SUN4I_A10_PLL2_4X:
254 *freq = (*freq * 2 * n) / pre_div / 2;
256 case SUN4I_A10_PLL2_8X:
257 *freq = (*freq * 2 * n) / pre_div;
267 a10_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
270 uint32_t val, post_div, n, pre_div;
272 if (sc->id != SUN4I_A10_PLL2_1X)
276 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
278 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
279 * To get as close as possible to the desired rate, we use a
280 * pre-divider of 21 and a post-divider of 4. With these values,
281 * a multiplier of 86 or 79 gets us close to the target rates.
283 if (*fout != 24576000 && *fout != 22579200)
288 n = (*fout * pre_div * post_div * 2) / (2 * fin);
292 val &= ~(A10_PLL2_POST_DIV | A10_PLL2_FACTOR_N | A10_PLL2_PRE_DIV);
293 val |= (post_div << A10_PLL2_POST_DIV_SHIFT);
294 val |= (n << A10_PLL2_FACTOR_N_SHIFT);
295 val |= (pre_div << A10_PLL2_PRE_DIV_SHIFT);
303 a10_pll3_recalc(struct aw_pll_sc *sc, uint64_t *freq)
311 if ((val & A10_PLL3_MODE_SEL) == A10_PLL3_MODE_SEL_INT) {
312 /* In integer mode, output is 3MHz * m */
313 m = (val & A10_PLL3_FACTOR_M) >> A10_PLL3_FACTOR_M_SHIFT;
314 *freq = A10_PLL3_REF_FREQ * m;
316 /* In fractional mode, output is either 270MHz or 297MHz */
317 if ((val & A10_PLL3_FUNC_SET) == A10_PLL3_FUNC_SET_270MHZ)
323 if (sc->id == CLKID_A10_PLL3_2X)
330 a10_pll3_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
333 uint32_t val, m, mode, func;
335 m = *fout / A10_PLL3_REF_FREQ;
336 if (sc->id == CLKID_A10_PLL3_2X)
339 mode = A10_PLL3_MODE_SEL_INT;
341 *fout = m * A10_PLL3_REF_FREQ;
342 if (sc->id == CLKID_A10_PLL3_2X)
347 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
350 val |= (m << A10_PLL3_FACTOR_M_SHIFT);
358 a10_pll3_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
362 /* Allow changing PLL frequency while enabled */
363 def->flags = CLK_NODE_GLITCH_FREE;
365 /* Set PLL to 297MHz */
366 CLKDEV_DEVICE_LOCK(dev);
367 CLKDEV_READ_4(dev, reg, &val);
368 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
369 val |= A10_PLL3_MODE_SEL_FRACT;
370 val |= A10_PLL3_FUNC_SET_297MHZ;
371 CLKDEV_WRITE_4(dev, reg, val);
372 CLKDEV_DEVICE_UNLOCK(dev);
378 a10_pll5_recalc(struct aw_pll_sc *sc, uint64_t *freq)
380 uint32_t val, m, n, k, p;
386 p = 1 << ((val & A10_PLL5_OUT_EXT_DIVP) >> A10_PLL5_OUT_EXT_DIVP_SHIFT);
387 m = ((val & A10_PLL5_FACTOR_M) >> A10_PLL5_FACTOR_M_SHIFT) + 1;
388 k = ((val & A10_PLL5_FACTOR_K) >> A10_PLL5_FACTOR_K_SHIFT) + 1;
389 n = (val & A10_PLL5_FACTOR_N) >> A10_PLL5_FACTOR_N_SHIFT;
394 case CLKID_A10_PLL5_DDR:
395 *freq = (*freq * n * k) / m;
397 case CLKID_A10_PLL5_OTHER:
398 *freq = (*freq * n * k) / p;
408 a10_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
410 uint32_t val, m, n, k;
413 * SATA needs PLL6 to be a 100MHz clock.
415 * The SATA output frequency is (24MHz * n * k) / m / 6.
416 * To get to 100MHz, k & m must be equal and n must be 25.
421 CLKDEV_DEVICE_LOCK(dev);
422 CLKDEV_READ_4(dev, reg, &val);
423 val &= ~(A10_PLL6_FACTOR_N | A10_PLL6_FACTOR_K | A10_PLL6_FACTOR_M);
424 val &= ~A10_PLL6_BYPASS_EN;
425 val |= A10_PLL6_SATA_CLK_EN;
426 val |= (n << A10_PLL6_FACTOR_N_SHIFT);
427 val |= (k << A10_PLL6_FACTOR_K_SHIFT);
428 val |= (m << A10_PLL6_FACTOR_M_SHIFT);
429 CLKDEV_WRITE_4(dev, reg, val);
430 CLKDEV_DEVICE_UNLOCK(dev);
436 a10_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
438 uint32_t val, m, k, n;
444 m = ((val & A10_PLL6_FACTOR_M) >> A10_PLL6_FACTOR_M_SHIFT) + 1;
445 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
446 n = (val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT;
451 case CLKID_A10_PLL6_SATA:
452 *freq = (*freq * n * k) / m / 6;
454 case CLKID_A10_PLL6_OTHER:
455 *freq = (*freq * n * k) / 2;
458 *freq = (*freq * n * k);
460 case CLKID_A10_PLL6_DIV_4:
461 *freq = (*freq * n * k) / 4;
471 a10_pll6_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
474 if (sc->id != CLKID_A10_PLL6_SATA)
477 /* PLL6 SATA output has been set to 100MHz in a10_pll6_init */
478 if (*fout != 100000000)
485 a13_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
487 uint32_t val, post_div, n, pre_div;
493 post_div = ((val & A13_PLL2_POST_DIV) >> A13_PLL2_POST_DIV_SHIFT) + 1;
496 n = (val & A13_PLL2_FACTOR_N) >> A13_PLL2_FACTOR_N_SHIFT;
499 pre_div = ((val & A13_PLL2_PRE_DIV) >> A13_PLL2_PRE_DIV_SHIFT) + 1;
504 case SUN4I_A10_PLL2_1X:
505 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
507 case SUN4I_A10_PLL2_2X:
508 *freq = (*freq * 2 * n) / pre_div / 4;
510 case SUN4I_A10_PLL2_4X:
511 *freq = (*freq * 2 * n) / pre_div / 2;
513 case SUN4I_A10_PLL2_8X:
514 *freq = (*freq * 2 * n) / pre_div;
524 a13_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
527 uint32_t val, post_div, n, pre_div;
529 if (sc->id != SUN4I_A10_PLL2_1X)
533 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
535 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
536 * To get as close as possible to the desired rate, we use a
537 * pre-divider of 21 and a post-divider of 4. With these values,
538 * a multiplier of 86 or 79 gets us close to the target rates.
540 if (*fout != 24576000 && *fout != 22579200)
545 n = (*fout * pre_div * post_div * 2) / (2 * fin);
549 val &= ~(A13_PLL2_POST_DIV | A13_PLL2_FACTOR_N | A13_PLL2_PRE_DIV);
550 val |= ((post_div - 1) << A13_PLL2_POST_DIV_SHIFT);
551 val |= (n << A13_PLL2_FACTOR_N_SHIFT);
552 val |= ((pre_div - 1) << A13_PLL2_PRE_DIV_SHIFT);
560 a23_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
562 uint32_t val, m, n, k, p;
568 m = ((val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT) + 1;
569 k = ((val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT) + 1;
570 n = ((val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT) + 1;
571 p = ((val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT) + 1;
573 *freq = (*freq * n * k) / (m * p);
579 a31_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
581 uint32_t val, m, n, k;
587 m = ((val & A31_PLL1_FACTOR_M) >> A31_PLL1_FACTOR_M_SHIFT) + 1;
588 k = ((val & A31_PLL1_FACTOR_K) >> A31_PLL1_FACTOR_K_SHIFT) + 1;
589 n = ((val & A31_PLL1_FACTOR_N) >> A31_PLL1_FACTOR_N_SHIFT) + 1;
591 *freq = (*freq * n * k) / m;
597 a31_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
602 if (def->id != CLKID_A31_PLL6)
606 * The datasheet recommends that PLL6 output should be fixed to
609 CLKDEV_DEVICE_LOCK(dev);
610 CLKDEV_READ_4(dev, reg, &val);
611 val &= ~(A31_PLL6_FACTOR_N | A31_PLL6_FACTOR_K | A31_PLL6_BYPASS_EN);
612 val |= (A31_PLL6_DEFAULT_N << A31_PLL6_FACTOR_N_SHIFT);
613 val |= (A31_PLL6_DEFAULT_K << A31_PLL6_FACTOR_K_SHIFT);
614 val |= AW_PLL_ENABLE;
615 CLKDEV_WRITE_4(dev, reg, val);
617 /* Wait for PLL to become stable */
618 for (retry = A31_PLL6_TIMEOUT; retry > 0; retry--) {
619 CLKDEV_READ_4(dev, reg, &val);
620 if ((val & A31_PLL6_LOCK) == A31_PLL6_LOCK)
625 CLKDEV_DEVICE_UNLOCK(dev);
631 a31_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
639 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
640 n = ((val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT) + 1;
644 *freq = (*freq * n * k) / 2;
646 case CLKID_A31_PLL6_X2:
647 *freq = *freq * n * k;
657 a80_pll4_recalc(struct aw_pll_sc *sc, uint64_t *freq)
659 uint32_t val, n, div1, div2;
665 n = (val & A80_PLL4_FACTOR_N) >> A80_PLL4_FACTOR_N_SHIFT;
666 div1 = (val & A80_PLL4_PLL_DIV1) == 0 ? 1 : 2;
667 div2 = (val & A80_PLL4_PLL_DIV2) == 0 ? 1 : 2;
669 *freq = (*freq * n) / div1 / div2;
675 a64_pllhsic_recalc(struct aw_pll_sc *sc, uint64_t *freq)
683 n = ((val & A64_PLLHSIC_FACTOR_N) >> A64_PLLHSIC_FACTOR_N_SHIFT) + 1;
684 m = ((val & A64_PLLHSIC_PRE_DIV_M) >> A64_PLLHSIC_PRE_DIV_M_SHIFT) + 1;
686 *freq = (*freq * n) / m;
692 a64_pllhsic_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
697 * PLL_HSIC default is 480MHz, just enable it.
699 CLKDEV_DEVICE_LOCK(dev);
700 CLKDEV_READ_4(dev, reg, &val);
701 val |= AW_PLL_ENABLE;
702 CLKDEV_WRITE_4(dev, reg, val);
703 CLKDEV_DEVICE_UNLOCK(dev);
708 #define PLL(_type, _recalc, _set_freq, _init) \
710 .recalc = (_recalc), \
711 .set_freq = (_set_freq), \
715 static struct aw_pll_funcs aw_pll_func[] = {
716 PLL(AWPLL_A10_PLL1, a10_pll1_recalc, NULL, NULL),
717 PLL(AWPLL_A10_PLL2, a10_pll2_recalc, a10_pll2_set_freq, NULL),
718 PLL(AWPLL_A10_PLL3, a10_pll3_recalc, a10_pll3_set_freq, a10_pll3_init),
719 PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL),
720 PLL(AWPLL_A10_PLL6, a10_pll6_recalc, a10_pll6_set_freq, a10_pll6_init),
721 PLL(AWPLL_A13_PLL2, a13_pll2_recalc, a13_pll2_set_freq, NULL),
722 PLL(AWPLL_A23_PLL1, a23_pll1_recalc, NULL, NULL),
723 PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL),
724 PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init),
725 PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),
726 PLL(AWPLL_A64_PLLHSIC, a64_pllhsic_recalc, NULL, a64_pllhsic_init),
729 static struct ofw_compat_data compat_data[] = {
730 { "allwinner,sun4i-a10-pll1-clk", AWPLL_A10_PLL1 },
731 { "allwinner,sun4i-a10-pll2-clk", AWPLL_A10_PLL2 },
732 { "allwinner,sun4i-a10-pll3-clk", AWPLL_A10_PLL3 },
733 { "allwinner,sun4i-a10-pll5-clk", AWPLL_A10_PLL5 },
734 { "allwinner,sun4i-a10-pll6-clk", AWPLL_A10_PLL6 },
735 { "allwinner,sun5i-a13-pll2-clk", AWPLL_A13_PLL2 },
736 { "allwinner,sun6i-a31-pll1-clk", AWPLL_A31_PLL1 },
737 { "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 },
738 { "allwinner,sun8i-a23-pll1-clk", AWPLL_A23_PLL1 },
739 { "allwinner,sun9i-a80-pll4-clk", AWPLL_A80_PLL4 },
740 { "allwinner,sun50i-a64-pllhsic-clk", AWPLL_A64_PLLHSIC },
745 aw_pll_init(struct clknode *clk, device_t dev)
747 clknode_init_parent_idx(clk, 0);
752 aw_pll_set_gate(struct clknode *clk, bool enable)
754 struct aw_pll_sc *sc;
757 sc = clknode_get_softc(clk);
762 val |= AW_PLL_ENABLE;
764 val &= ~AW_PLL_ENABLE;
772 aw_pll_recalc(struct clknode *clk, uint64_t *freq)
774 struct aw_pll_sc *sc;
776 sc = clknode_get_softc(clk);
778 if (aw_pll_func[sc->type].recalc == NULL)
781 return (aw_pll_func[sc->type].recalc(sc, freq));
785 aw_pll_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
786 int flags, int *stop)
788 struct aw_pll_sc *sc;
790 sc = clknode_get_softc(clk);
794 if (aw_pll_func[sc->type].set_freq == NULL)
797 return (aw_pll_func[sc->type].set_freq(sc, fin, fout, flags));
800 static clknode_method_t aw_pll_clknode_methods[] = {
801 /* Device interface */
802 CLKNODEMETHOD(clknode_init, aw_pll_init),
803 CLKNODEMETHOD(clknode_set_gate, aw_pll_set_gate),
804 CLKNODEMETHOD(clknode_recalc_freq, aw_pll_recalc),
805 CLKNODEMETHOD(clknode_set_freq, aw_pll_set_freq),
809 DEFINE_CLASS_1(aw_pll_clknode, aw_pll_clknode_class, aw_pll_clknode_methods,
810 sizeof(struct aw_pll_sc), clknode_class);
813 aw_pll_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
814 const char *pclkname, const char *clkname, int index)
816 enum aw_pll_type type;
817 struct clknode_init_def clkdef;
818 struct aw_pll_sc *sc;
822 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
824 memset(&clkdef, 0, sizeof(clkdef));
826 clkdef.name = clkname;
827 if (pclkname != NULL) {
828 clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP,
830 clkdef.parent_names[0] = pclkname;
831 clkdef.parent_cnt = 1;
833 clkdef.parent_cnt = 0;
835 if (aw_pll_func[type].init != NULL) {
836 error = aw_pll_func[type].init(device_get_parent(dev),
839 device_printf(dev, "clock %s init failed\n", clkname);
844 clk = clknode_create(clkdom, &aw_pll_clknode_class, &clkdef);
846 device_printf(dev, "cannot create clock node\n");
849 sc = clknode_get_softc(clk);
850 sc->clkdev = device_get_parent(dev);
855 clknode_register(clkdom, clk);
857 OF_prop_free(__DECONST(char *, clkdef.parent_names));
863 aw_pll_probe(device_t dev)
865 if (!ofw_bus_status_okay(dev))
868 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
871 device_set_desc(dev, "Allwinner PLL Clock");
872 return (BUS_PROBE_DEFAULT);
876 aw_pll_attach(device_t dev)
878 struct clkdom *clkdom;
880 int index, nout, error;
887 node = ofw_bus_get_node(dev);
889 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
890 device_printf(dev, "couldn't parse 'reg' property\n");
894 clkdom = clkdom_create(dev);
896 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
898 device_printf(dev, "no clock outputs found\n");
903 if (clk_get_by_ofw_index(dev, 0, 0, &clk_parent) != 0)
906 for (index = 0; index < nout; index++) {
907 error = aw_pll_create(dev, paddr, clkdom,
908 clk_parent ? clk_get_name(clk_parent) : NULL,
909 names[index], nout == 1 ? 1 : index);
914 if (clkdom_finit(clkdom) != 0) {
915 device_printf(dev, "cannot finalize clkdom initialization\n");
929 static device_method_t aw_pll_methods[] = {
930 /* Device interface */
931 DEVMETHOD(device_probe, aw_pll_probe),
932 DEVMETHOD(device_attach, aw_pll_attach),
937 static driver_t aw_pll_driver = {
943 static devclass_t aw_pll_devclass;
945 EARLY_DRIVER_MODULE(aw_pll, simplebus, aw_pll_driver,
946 aw_pll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);