2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk.h>
50 #include <arm/allwinner/aw_machdep.h>
52 #include "clkdev_if.h"
54 #define SUN4I_A10_PLL2_1X 0
55 #define SUN4I_A10_PLL2_2X 1
56 #define SUN4I_A10_PLL2_4X 2
57 #define SUN4I_A10_PLL2_8X 3
59 #define AW_PLL_ENABLE (1 << 31)
61 #define A10_PLL1_OUT_EXT_DIVP (0x3 << 16)
62 #define A10_PLL1_OUT_EXT_DIVP_SHIFT 16
63 #define A10_PLL1_FACTOR_N (0x1f << 8)
64 #define A10_PLL1_FACTOR_N_SHIFT 8
65 #define A10_PLL1_FACTOR_K (0x3 << 4)
66 #define A10_PLL1_FACTOR_K_SHIFT 4
67 #define A10_PLL1_FACTOR_M (0x3 << 0)
68 #define A10_PLL1_FACTOR_M_SHIFT 0
70 #define A10_PLL2_POST_DIV (0xf << 26)
71 #define A10_PLL2_POST_DIV_SHIFT 26
72 #define A10_PLL2_FACTOR_N (0x7f << 8)
73 #define A10_PLL2_FACTOR_N_SHIFT 8
74 #define A10_PLL2_PRE_DIV (0x1f << 0)
75 #define A10_PLL2_PRE_DIV_SHIFT 0
77 #define A10_PLL3_MODE_SEL (0x1 << 15)
78 #define A10_PLL3_MODE_SEL_FRACT (0 << 15)
79 #define A10_PLL3_MODE_SEL_INT (1 << 15)
80 #define A10_PLL3_FUNC_SET (0x1 << 14)
81 #define A10_PLL3_FUNC_SET_270MHZ (0 << 14)
82 #define A10_PLL3_FUNC_SET_297MHZ (1 << 14)
83 #define A10_PLL3_FACTOR_M (0x7f << 0)
84 #define A10_PLL3_FACTOR_M_SHIFT 0
85 #define A10_PLL3_REF_FREQ 3000000
87 #define A10_PLL5_OUT_EXT_DIVP (0x3 << 16)
88 #define A10_PLL5_OUT_EXT_DIVP_SHIFT 16
89 #define A10_PLL5_FACTOR_N (0x1f << 8)
90 #define A10_PLL5_FACTOR_N_SHIFT 8
91 #define A10_PLL5_FACTOR_K (0x3 << 4)
92 #define A10_PLL5_FACTOR_K_SHIFT 4
93 #define A10_PLL5_FACTOR_M1 (0x3 << 2)
94 #define A10_PLL5_FACTOR_M1_SHIFT 2
95 #define A10_PLL5_FACTOR_M (0x3 << 0)
96 #define A10_PLL5_FACTOR_M_SHIFT 0
98 #define A10_PLL6_BYPASS_EN (1 << 30)
99 #define A10_PLL6_SATA_CLK_EN (1 << 14)
100 #define A10_PLL6_FACTOR_N (0x1f << 8)
101 #define A10_PLL6_FACTOR_N_SHIFT 8
102 #define A10_PLL6_FACTOR_K (0x3 << 4)
103 #define A10_PLL6_FACTOR_K_SHIFT 4
104 #define A10_PLL6_FACTOR_M (0x3 << 0)
105 #define A10_PLL6_FACTOR_M_SHIFT 0
107 #define A10_PLL2_POST_DIV (0xf << 26)
109 #define A13_PLL2_POST_DIV (0xf << 26)
110 #define A13_PLL2_POST_DIV_SHIFT 26
111 #define A13_PLL2_FACTOR_N (0x7f << 8)
112 #define A13_PLL2_FACTOR_N_SHIFT 8
113 #define A13_PLL2_PRE_DIV (0x1f << 0)
114 #define A13_PLL2_PRE_DIV_SHIFT 0
116 #define A23_PLL1_FACTOR_P (0x3 << 16)
117 #define A23_PLL1_FACTOR_P_SHIFT 16
118 #define A23_PLL1_FACTOR_N (0x1f << 8)
119 #define A23_PLL1_FACTOR_N_SHIFT 8
120 #define A23_PLL1_FACTOR_K (0x3 << 4)
121 #define A23_PLL1_FACTOR_K_SHIFT 4
122 #define A23_PLL1_FACTOR_M (0x3 << 0)
123 #define A23_PLL1_FACTOR_M_SHIFT 0
125 #define A31_PLL1_LOCK (1 << 28)
126 #define A31_PLL1_CPU_SIGMA_DELTA_EN (1 << 24)
127 #define A31_PLL1_FACTOR_N (0x1f << 8)
128 #define A31_PLL1_FACTOR_N_SHIFT 8
129 #define A31_PLL1_FACTOR_K (0x3 << 4)
130 #define A31_PLL1_FACTOR_K_SHIFT 4
131 #define A31_PLL1_FACTOR_M (0x3 << 0)
132 #define A31_PLL1_FACTOR_M_SHIFT 0
134 #define A31_PLL6_LOCK (1 << 28)
135 #define A31_PLL6_BYPASS_EN (1 << 25)
136 #define A31_PLL6_CLK_OUT_EN (1 << 24)
137 #define A31_PLL6_24M_OUT_EN (1 << 18)
138 #define A31_PLL6_24M_POST_DIV (0x3 << 16)
139 #define A31_PLL6_24M_POST_DIV_SHIFT 16
140 #define A31_PLL6_FACTOR_N (0x1f << 8)
141 #define A31_PLL6_FACTOR_N_SHIFT 8
142 #define A31_PLL6_FACTOR_K (0x3 << 4)
143 #define A31_PLL6_FACTOR_K_SHIFT 4
144 #define A31_PLL6_DEFAULT_N 0x18
145 #define A31_PLL6_DEFAULT_K 0x1
146 #define A31_PLL6_TIMEOUT 10
148 #define A64_PLLHSIC_LOCK (1 << 28)
149 #define A64_PLLHSIC_FRAC_CLK_OUT (1 << 25)
150 #define A64_PLLHSIC_PLL_MODE_SEL (1 << 24)
151 #define A64_PLLHSIC_PLL_SDM_EN (1 << 20)
152 #define A64_PLLHSIC_FACTOR_N (0x7f << 8)
153 #define A64_PLLHSIC_FACTOR_N_SHIFT 8
154 #define A64_PLLHSIC_PRE_DIV_M (0xf << 0)
155 #define A64_PLLHSIC_PRE_DIV_M_SHIFT 0
157 #define A80_PLL4_CLK_OUT_EN (1 << 20)
158 #define A80_PLL4_PLL_DIV2 (1 << 18)
159 #define A80_PLL4_PLL_DIV1 (1 << 16)
160 #define A80_PLL4_FACTOR_N (0xff << 8)
161 #define A80_PLL4_FACTOR_N_SHIFT 8
163 #define A83T_PLLCPUX_LOCK_TIME (0x7 << 24)
164 #define A83T_PLLCPUX_LOCK_TIME_SHIFT 24
165 #define A83T_PLLCPUX_CLOCK_OUTPUT_DIS (1 << 20)
166 #define A83T_PLLCPUX_OUT_EXT_DIVP (1 << 16)
167 #define A83T_PLLCPUX_FACTOR_N (0xff << 8)
168 #define A83T_PLLCPUX_FACTOR_N_SHIFT 8
169 #define A83T_PLLCPUX_FACTOR_N_MIN 12
170 #define A83T_PLLCPUX_FACTOR_N_MAX 125
171 #define A83T_PLLCPUX_POSTDIV_M (0x3 << 0)
172 #define A83T_PLLCPUX_POSTDIV_M_SHIFT 0
174 #define H3_PLL2_LOCK (1 << 28)
175 #define H3_PLL2_SDM_EN (1 << 24)
176 #define H3_PLL2_POST_DIV (0xf << 16)
177 #define H3_PLL2_POST_DIV_SHIFT 16
178 #define H3_PLL2_FACTOR_N (0x7f << 8)
179 #define H3_PLL2_FACTOR_N_SHIFT 8
180 #define H3_PLL2_PRE_DIV (0x1f << 0)
181 #define H3_PLL2_PRE_DIV_SHIFT 0
183 #define CLKID_A10_PLL5_DDR 0
184 #define CLKID_A10_PLL5_OTHER 1
186 #define CLKID_A10_PLL6_SATA 0
187 #define CLKID_A10_PLL6_OTHER 1
188 #define CLKID_A10_PLL6 2
189 #define CLKID_A10_PLL6_DIV_4 3
191 #define CLKID_A31_PLL6 0
192 #define CLKID_A31_PLL6_X2 1
194 struct aw_pll_factor {
201 #define PLLFACTOR(_n, _k, _m, _p, _freq) \
202 { .n = (_n), .k = (_k), .m = (_m), .p = (_p), .freq = (_freq) }
204 static struct aw_pll_factor aw_a10_pll1_factors[] = {
205 PLLFACTOR(6, 0, 0, 0, 144000000),
206 PLLFACTOR(12, 0, 0, 0, 312000000),
207 PLLFACTOR(21, 0, 0, 0, 528000000),
208 PLLFACTOR(29, 0, 0, 0, 720000000),
209 PLLFACTOR(18, 1, 0, 0, 864000000),
210 PLLFACTOR(19, 1, 0, 0, 912000000),
211 PLLFACTOR(20, 1, 0, 0, 960000000),
214 static struct aw_pll_factor aw_a23_pll1_factors[] = {
215 PLLFACTOR(9, 0, 0, 2, 60000000),
216 PLLFACTOR(10, 0, 0, 2, 66000000),
217 PLLFACTOR(11, 0, 0, 2, 72000000),
218 PLLFACTOR(12, 0, 0, 2, 78000000),
219 PLLFACTOR(13, 0, 0, 2, 84000000),
220 PLLFACTOR(14, 0, 0, 2, 90000000),
221 PLLFACTOR(15, 0, 0, 2, 96000000),
222 PLLFACTOR(16, 0, 0, 2, 102000000),
223 PLLFACTOR(17, 0, 0, 2, 108000000),
224 PLLFACTOR(18, 0, 0, 2, 114000000),
225 PLLFACTOR(9, 0, 0, 1, 120000000),
226 PLLFACTOR(10, 0, 0, 1, 132000000),
227 PLLFACTOR(11, 0, 0, 1, 144000000),
228 PLLFACTOR(12, 0, 0, 1, 156000000),
229 PLLFACTOR(13, 0, 0, 1, 168000000),
230 PLLFACTOR(14, 0, 0, 1, 180000000),
231 PLLFACTOR(15, 0, 0, 1, 192000000),
232 PLLFACTOR(16, 0, 0, 1, 204000000),
233 PLLFACTOR(17, 0, 0, 1, 216000000),
234 PLLFACTOR(18, 0, 0, 1, 228000000),
235 PLLFACTOR(9, 0, 0, 0, 240000000),
236 PLLFACTOR(10, 0, 0, 0, 264000000),
237 PLLFACTOR(11, 0, 0, 0, 288000000),
238 PLLFACTOR(12, 0, 0, 0, 312000000),
239 PLLFACTOR(13, 0, 0, 0, 336000000),
240 PLLFACTOR(14, 0, 0, 0, 360000000),
241 PLLFACTOR(15, 0, 0, 0, 384000000),
242 PLLFACTOR(16, 0, 0, 0, 408000000),
243 PLLFACTOR(17, 0, 0, 0, 432000000),
244 PLLFACTOR(18, 0, 0, 0, 456000000),
245 PLLFACTOR(19, 0, 0, 0, 480000000),
246 PLLFACTOR(20, 0, 0, 0, 504000000),
247 PLLFACTOR(21, 0, 0, 0, 528000000),
248 PLLFACTOR(22, 0, 0, 0, 552000000),
249 PLLFACTOR(23, 0, 0, 0, 576000000),
250 PLLFACTOR(24, 0, 0, 0, 600000000),
251 PLLFACTOR(25, 0, 0, 0, 624000000),
252 PLLFACTOR(26, 0, 0, 0, 648000000),
253 PLLFACTOR(27, 0, 0, 0, 672000000),
254 PLLFACTOR(28, 0, 0, 0, 696000000),
255 PLLFACTOR(29, 0, 0, 0, 720000000),
256 PLLFACTOR(15, 1, 0, 0, 768000000),
257 PLLFACTOR(10, 2, 0, 0, 792000000),
258 PLLFACTOR(16, 1, 0, 0, 816000000),
259 PLLFACTOR(17, 1, 0, 0, 864000000),
260 PLLFACTOR(18, 1, 0, 0, 912000000),
261 PLLFACTOR(12, 2, 0, 0, 936000000),
262 PLLFACTOR(19, 1, 0, 0, 960000000),
263 PLLFACTOR(20, 1, 0, 0, 1008000000),
264 PLLFACTOR(21, 1, 0, 0, 1056000000),
265 PLLFACTOR(14, 2, 0, 0, 1080000000),
266 PLLFACTOR(22, 1, 0, 0, 1104000000),
267 PLLFACTOR(23, 1, 0, 0, 1152000000),
268 PLLFACTOR(24, 1, 0, 0, 1200000000),
269 PLLFACTOR(16, 2, 0, 0, 1224000000),
270 PLLFACTOR(25, 1, 0, 0, 1248000000),
271 PLLFACTOR(26, 1, 0, 0, 1296000000),
272 PLLFACTOR(27, 1, 0, 0, 1344000000),
273 PLLFACTOR(18, 2, 0, 0, 1368000000),
274 PLLFACTOR(28, 1, 0, 0, 1392000000),
275 PLLFACTOR(29, 1, 0, 0, 1440000000),
276 PLLFACTOR(20, 2, 0, 0, 1512000000),
277 PLLFACTOR(15, 3, 0, 0, 1536000000),
278 PLLFACTOR(21, 2, 0, 0, 1584000000),
279 PLLFACTOR(16, 3, 0, 0, 1632000000),
280 PLLFACTOR(22, 2, 0, 0, 1656000000),
281 PLLFACTOR(23, 2, 0, 0, 1728000000),
282 PLLFACTOR(24, 2, 0, 0, 1800000000),
283 PLLFACTOR(18, 3, 0, 0, 1824000000),
284 PLLFACTOR(25, 2, 0, 0, 1872000000),
287 static struct aw_pll_factor aw_h3_pll2_factors[] = {
288 PLLFACTOR(13, 0, 0, 13, 24576000),
289 PLLFACTOR(6, 0, 0, 7, 22579200),
310 enum aw_pll_type type;
316 struct aw_pll_funcs {
317 int (*recalc)(struct aw_pll_sc *, uint64_t *);
318 int (*set_freq)(struct aw_pll_sc *, uint64_t, uint64_t *, int);
319 int (*init)(device_t, bus_addr_t, struct clknode_init_def *);
322 #define PLL_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
323 #define PLL_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
324 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
325 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
328 a10_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
331 struct aw_pll_factor *f;
336 for (n = 0; n < nitems(aw_a10_pll1_factors); n++) {
337 if (aw_a10_pll1_factors[n].freq == *fout) {
338 f = &aw_a10_pll1_factors[n];
345 if ((flags & CLK_SET_DRYRUN) != 0)
350 val &= ~(A10_PLL1_FACTOR_N|A10_PLL1_FACTOR_K|A10_PLL1_FACTOR_M|
351 A10_PLL1_OUT_EXT_DIVP);
352 val |= (f->p << A10_PLL1_OUT_EXT_DIVP_SHIFT);
353 val |= (f->n << A10_PLL1_FACTOR_N_SHIFT);
354 val |= (f->k << A10_PLL1_FACTOR_K_SHIFT);
355 val |= (f->m << A10_PLL1_FACTOR_M_SHIFT);
363 a10_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
365 uint32_t val, m, n, k, p;
371 p = 1 << ((val & A10_PLL1_OUT_EXT_DIVP) >> A10_PLL1_OUT_EXT_DIVP_SHIFT);
372 m = ((val & A10_PLL1_FACTOR_M) >> A10_PLL1_FACTOR_M_SHIFT) + 1;
373 k = ((val & A10_PLL1_FACTOR_K) >> A10_PLL1_FACTOR_K_SHIFT) + 1;
374 n = (val & A10_PLL1_FACTOR_N) >> A10_PLL1_FACTOR_N_SHIFT;
378 *freq = (*freq * n * k) / (m * p);
384 a10_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
386 uint32_t val, post_div, n, pre_div;
392 post_div = (val & A10_PLL2_POST_DIV) >> A10_PLL2_POST_DIV_SHIFT;
395 n = (val & A10_PLL2_FACTOR_N) >> A10_PLL2_FACTOR_N_SHIFT;
398 pre_div = (val & A10_PLL2_PRE_DIV) >> A10_PLL2_PRE_DIV_SHIFT;
403 case SUN4I_A10_PLL2_1X:
404 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
406 case SUN4I_A10_PLL2_2X:
407 *freq = (*freq * 2 * n) / pre_div / 4;
409 case SUN4I_A10_PLL2_4X:
410 *freq = (*freq * 2 * n) / pre_div / 2;
412 case SUN4I_A10_PLL2_8X:
413 *freq = (*freq * 2 * n) / pre_div;
423 a10_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
426 uint32_t val, post_div, n, pre_div;
428 if (sc->id != SUN4I_A10_PLL2_1X)
432 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
434 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
435 * To get as close as possible to the desired rate, we use a
436 * pre-divider of 21 and a post-divider of 4. With these values,
437 * a multiplier of 86 or 79 gets us close to the target rates.
439 if (*fout != 24576000 && *fout != 22579200)
444 n = (*fout * pre_div * post_div * 2) / (2 * fin);
446 if ((flags & CLK_SET_DRYRUN) != 0)
451 val &= ~(A10_PLL2_POST_DIV | A10_PLL2_FACTOR_N | A10_PLL2_PRE_DIV);
452 val |= (post_div << A10_PLL2_POST_DIV_SHIFT);
453 val |= (n << A10_PLL2_FACTOR_N_SHIFT);
454 val |= (pre_div << A10_PLL2_PRE_DIV_SHIFT);
462 a10_pll3_recalc(struct aw_pll_sc *sc, uint64_t *freq)
470 if ((val & A10_PLL3_MODE_SEL) == A10_PLL3_MODE_SEL_INT) {
471 /* In integer mode, output is 3MHz * m */
472 m = (val & A10_PLL3_FACTOR_M) >> A10_PLL3_FACTOR_M_SHIFT;
473 *freq = A10_PLL3_REF_FREQ * m;
475 /* In fractional mode, output is either 270MHz or 297MHz */
476 if ((val & A10_PLL3_FUNC_SET) == A10_PLL3_FUNC_SET_270MHZ)
486 a10_pll3_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
489 uint32_t val, m, mode, func;
491 if (*fout == 297000000) {
492 func = A10_PLL3_FUNC_SET_297MHZ;
493 mode = A10_PLL3_MODE_SEL_FRACT;
495 } else if (*fout == 270000000) {
496 func = A10_PLL3_FUNC_SET_270MHZ;
497 mode = A10_PLL3_MODE_SEL_FRACT;
500 mode = A10_PLL3_MODE_SEL_INT;
502 m = *fout / A10_PLL3_REF_FREQ;
503 *fout = m * A10_PLL3_REF_FREQ;
506 if ((flags & CLK_SET_DRYRUN) != 0)
511 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
514 val |= (m << A10_PLL3_FACTOR_M_SHIFT);
522 a10_pll3_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
526 /* Allow changing PLL frequency while enabled */
527 def->flags = CLK_NODE_GLITCH_FREE;
529 /* Set PLL to 297MHz */
530 CLKDEV_DEVICE_LOCK(dev);
531 CLKDEV_READ_4(dev, reg, &val);
532 val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M);
533 val |= A10_PLL3_MODE_SEL_FRACT;
534 val |= A10_PLL3_FUNC_SET_297MHZ;
535 CLKDEV_WRITE_4(dev, reg, val);
536 CLKDEV_DEVICE_UNLOCK(dev);
542 a10_pll5_recalc(struct aw_pll_sc *sc, uint64_t *freq)
544 uint32_t val, m, n, k, p;
550 p = 1 << ((val & A10_PLL5_OUT_EXT_DIVP) >> A10_PLL5_OUT_EXT_DIVP_SHIFT);
551 m = ((val & A10_PLL5_FACTOR_M) >> A10_PLL5_FACTOR_M_SHIFT) + 1;
552 k = ((val & A10_PLL5_FACTOR_K) >> A10_PLL5_FACTOR_K_SHIFT) + 1;
553 n = (val & A10_PLL5_FACTOR_N) >> A10_PLL5_FACTOR_N_SHIFT;
558 case CLKID_A10_PLL5_DDR:
559 *freq = (*freq * n * k) / m;
561 case CLKID_A10_PLL5_OTHER:
562 *freq = (*freq * n * k) / p;
572 a10_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
574 uint32_t val, m, n, k;
577 * SATA needs PLL6 to be a 100MHz clock.
579 * The SATA output frequency is (24MHz * n * k) / m / 6.
580 * To get to 100MHz, k & m must be equal and n must be 25.
585 CLKDEV_DEVICE_LOCK(dev);
586 CLKDEV_READ_4(dev, reg, &val);
587 val &= ~(A10_PLL6_FACTOR_N | A10_PLL6_FACTOR_K | A10_PLL6_FACTOR_M);
588 val &= ~A10_PLL6_BYPASS_EN;
589 val |= A10_PLL6_SATA_CLK_EN;
590 val |= (n << A10_PLL6_FACTOR_N_SHIFT);
591 val |= (k << A10_PLL6_FACTOR_K_SHIFT);
592 val |= (m << A10_PLL6_FACTOR_M_SHIFT);
593 CLKDEV_WRITE_4(dev, reg, val);
594 CLKDEV_DEVICE_UNLOCK(dev);
600 a10_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
602 uint32_t val, m, k, n;
608 m = ((val & A10_PLL6_FACTOR_M) >> A10_PLL6_FACTOR_M_SHIFT) + 1;
609 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
610 n = (val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT;
615 case CLKID_A10_PLL6_SATA:
616 *freq = (*freq * n * k) / m / 6;
618 case CLKID_A10_PLL6_OTHER:
619 *freq = (*freq * n * k) / 2;
622 *freq = (*freq * n * k);
624 case CLKID_A10_PLL6_DIV_4:
625 *freq = (*freq * n * k) / 4;
635 a10_pll6_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
638 if (sc->id != CLKID_A10_PLL6_SATA)
641 /* PLL6 SATA output has been set to 100MHz in a10_pll6_init */
642 if (*fout != 100000000)
649 a13_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
651 uint32_t val, post_div, n, pre_div;
657 post_div = ((val & A13_PLL2_POST_DIV) >> A13_PLL2_POST_DIV_SHIFT) + 1;
660 n = (val & A13_PLL2_FACTOR_N) >> A13_PLL2_FACTOR_N_SHIFT;
663 pre_div = ((val & A13_PLL2_PRE_DIV) >> A13_PLL2_PRE_DIV_SHIFT) + 1;
668 case SUN4I_A10_PLL2_1X:
669 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
671 case SUN4I_A10_PLL2_2X:
672 *freq = (*freq * 2 * n) / pre_div / 4;
674 case SUN4I_A10_PLL2_4X:
675 *freq = (*freq * 2 * n) / pre_div / 2;
677 case SUN4I_A10_PLL2_8X:
678 *freq = (*freq * 2 * n) / pre_div;
688 a13_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
691 uint32_t val, post_div, n, pre_div;
693 if (sc->id != SUN4I_A10_PLL2_1X)
697 * Audio Codec needs PLL2-1X to be either 24576000 or 22579200.
699 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
700 * To get as close as possible to the desired rate, we use a
701 * pre-divider of 21 and a post-divider of 4. With these values,
702 * a multiplier of 86 or 79 gets us close to the target rates.
704 if (*fout != 24576000 && *fout != 22579200)
709 n = (*fout * pre_div * post_div * 2) / (2 * fin);
711 if ((flags & CLK_SET_DRYRUN) != 0)
716 val &= ~(A13_PLL2_POST_DIV | A13_PLL2_FACTOR_N | A13_PLL2_PRE_DIV);
717 val |= ((post_div - 1) << A13_PLL2_POST_DIV_SHIFT);
718 val |= (n << A13_PLL2_FACTOR_N_SHIFT);
719 val |= ((pre_div - 1) << A13_PLL2_PRE_DIV_SHIFT);
727 h3_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq)
729 uint32_t val, p, n, m;
735 p = ((val & H3_PLL2_POST_DIV) >> H3_PLL2_POST_DIV_SHIFT) + 1;
736 n = ((val & H3_PLL2_FACTOR_N) >> H3_PLL2_FACTOR_N_SHIFT) + 1;
737 m = ((val & H3_PLL2_PRE_DIV) >> H3_PLL2_PRE_DIV_SHIFT) + 1;
740 case SUN4I_A10_PLL2_1X:
741 *freq = (*freq * n) / (m * p);
743 case SUN4I_A10_PLL2_2X:
744 *freq = (*freq * 2 * n) / m / 4;
746 case SUN4I_A10_PLL2_4X:
747 *freq = (*freq * 2 * n) / m / 2;
749 case SUN4I_A10_PLL2_8X:
750 *freq = (*freq * 2 * n) / m;
760 h3_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
763 struct aw_pll_factor *f;
767 if (sc->id != SUN4I_A10_PLL2_1X)
771 for (n = 0; n < nitems(aw_h3_pll2_factors); n++) {
772 if (aw_h3_pll2_factors[n].freq == *fout) {
773 f = &aw_h3_pll2_factors[n];
780 if ((flags & CLK_SET_DRYRUN) != 0)
785 val &= ~(H3_PLL2_POST_DIV|H3_PLL2_FACTOR_N|H3_PLL2_PRE_DIV);
786 val |= (f->p << H3_PLL2_POST_DIV_SHIFT);
787 val |= (f->n << H3_PLL2_FACTOR_N_SHIFT);
788 val |= (f->m << H3_PLL2_PRE_DIV_SHIFT);
789 val |= AW_PLL_ENABLE;
794 for (retry = 0; retry < 1000; retry++) {
796 if ((val & H3_PLL2_LOCK) != 0)
809 a23_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
812 struct aw_pll_factor *f;
817 for (n = 0; n < nitems(aw_a23_pll1_factors); n++) {
818 if (aw_a23_pll1_factors[n].freq == *fout) {
819 f = &aw_a23_pll1_factors[n];
826 if ((flags & CLK_SET_DRYRUN) != 0)
831 val &= ~(A23_PLL1_FACTOR_N|A23_PLL1_FACTOR_K|A23_PLL1_FACTOR_M|
833 val |= (f->n << A23_PLL1_FACTOR_N_SHIFT);
834 val |= (f->k << A23_PLL1_FACTOR_K_SHIFT);
835 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
836 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
845 a23_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
847 uint32_t val, m, n, k, p;
853 m = ((val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT) + 1;
854 k = ((val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT) + 1;
855 n = ((val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT) + 1;
856 p = ((val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT) + 1;
858 *freq = (*freq * n * k) / (m * p);
864 h3_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
867 struct aw_pll_factor *f;
868 uint32_t val, n, k, m, p;
872 for (i = 0; i < nitems(aw_a23_pll1_factors); i++) {
873 if (aw_a23_pll1_factors[i].freq == *fout) {
874 f = &aw_a23_pll1_factors[i];
881 if ((flags & CLK_SET_DRYRUN) != 0)
887 n = (val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT;
888 k = (val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT;
889 m = (val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT;
890 p = (val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT;
893 val &= ~A23_PLL1_FACTOR_P;
894 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
900 val &= ~A23_PLL1_FACTOR_M;
901 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
906 val &= ~(A23_PLL1_FACTOR_N|A23_PLL1_FACTOR_K);
907 val |= (f->n << A23_PLL1_FACTOR_N_SHIFT);
908 val |= (f->k << A23_PLL1_FACTOR_K_SHIFT);
913 val &= ~A23_PLL1_FACTOR_M;
914 val |= (f->m << A23_PLL1_FACTOR_M_SHIFT);
920 val &= ~A23_PLL1_FACTOR_P;
921 val |= (f->p << A23_PLL1_FACTOR_P_SHIFT);
933 a31_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq)
935 uint32_t val, m, n, k;
941 m = ((val & A31_PLL1_FACTOR_M) >> A31_PLL1_FACTOR_M_SHIFT) + 1;
942 k = ((val & A31_PLL1_FACTOR_K) >> A31_PLL1_FACTOR_K_SHIFT) + 1;
943 n = ((val & A31_PLL1_FACTOR_N) >> A31_PLL1_FACTOR_N_SHIFT) + 1;
945 *freq = (*freq * n * k) / m;
951 a31_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
956 if (def->id != CLKID_A31_PLL6)
960 * The datasheet recommends that PLL6 output should be fixed to
963 CLKDEV_DEVICE_LOCK(dev);
964 CLKDEV_READ_4(dev, reg, &val);
965 val &= ~(A31_PLL6_FACTOR_N | A31_PLL6_FACTOR_K | A31_PLL6_BYPASS_EN);
966 val |= (A31_PLL6_DEFAULT_N << A31_PLL6_FACTOR_N_SHIFT);
967 val |= (A31_PLL6_DEFAULT_K << A31_PLL6_FACTOR_K_SHIFT);
968 val |= AW_PLL_ENABLE;
969 CLKDEV_WRITE_4(dev, reg, val);
971 /* Wait for PLL to become stable */
972 for (retry = A31_PLL6_TIMEOUT; retry > 0; retry--) {
973 CLKDEV_READ_4(dev, reg, &val);
974 if ((val & A31_PLL6_LOCK) == A31_PLL6_LOCK)
979 CLKDEV_DEVICE_UNLOCK(dev);
985 a31_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq)
993 k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1;
994 n = ((val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT) + 1;
998 *freq = (*freq * n * k) / 2;
1000 case CLKID_A31_PLL6_X2:
1001 *freq = *freq * n * k;
1011 a80_pll4_recalc(struct aw_pll_sc *sc, uint64_t *freq)
1013 uint32_t val, n, div1, div2;
1019 n = (val & A80_PLL4_FACTOR_N) >> A80_PLL4_FACTOR_N_SHIFT;
1020 div1 = (val & A80_PLL4_PLL_DIV1) == 0 ? 1 : 2;
1021 div2 = (val & A80_PLL4_PLL_DIV2) == 0 ? 1 : 2;
1023 *freq = (*freq * n) / div1 / div2;
1029 a64_pllhsic_recalc(struct aw_pll_sc *sc, uint64_t *freq)
1037 n = ((val & A64_PLLHSIC_FACTOR_N) >> A64_PLLHSIC_FACTOR_N_SHIFT) + 1;
1038 m = ((val & A64_PLLHSIC_PRE_DIV_M) >> A64_PLLHSIC_PRE_DIV_M_SHIFT) + 1;
1040 *freq = (*freq * n) / m;
1046 a64_pllhsic_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
1051 * PLL_HSIC default is 480MHz, just enable it.
1053 CLKDEV_DEVICE_LOCK(dev);
1054 CLKDEV_READ_4(dev, reg, &val);
1055 val |= AW_PLL_ENABLE;
1056 CLKDEV_WRITE_4(dev, reg, val);
1057 CLKDEV_DEVICE_UNLOCK(dev);
1063 a83t_pllcpux_recalc(struct aw_pll_sc *sc, uint64_t *freq)
1071 n = (val & A83T_PLLCPUX_FACTOR_N) >> A83T_PLLCPUX_FACTOR_N_SHIFT;
1072 p = (val & A83T_PLLCPUX_OUT_EXT_DIVP) ? 4 : 1;
1074 *freq = (*freq * n) / p;
1080 a83t_pllcpux_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
1088 if (n < A83T_PLLCPUX_FACTOR_N_MIN || n > A83T_PLLCPUX_FACTOR_N_MAX)
1091 if ((flags & CLK_SET_DRYRUN) != 0)
1096 val &= ~A83T_PLLCPUX_FACTOR_N;
1097 val |= (n << A83T_PLLCPUX_FACTOR_N_SHIFT);
1098 val &= ~A83T_PLLCPUX_CLOCK_OUTPUT_DIS;
1105 #define PLL(_type, _recalc, _set_freq, _init) \
1107 .recalc = (_recalc), \
1108 .set_freq = (_set_freq), \
1112 static struct aw_pll_funcs aw_pll_func[] = {
1113 PLL(AWPLL_A10_PLL1, a10_pll1_recalc, a10_pll1_set_freq, NULL),
1114 PLL(AWPLL_A10_PLL2, a10_pll2_recalc, a10_pll2_set_freq, NULL),
1115 PLL(AWPLL_A10_PLL3, a10_pll3_recalc, a10_pll3_set_freq, a10_pll3_init),
1116 PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL),
1117 PLL(AWPLL_A10_PLL6, a10_pll6_recalc, a10_pll6_set_freq, a10_pll6_init),
1118 PLL(AWPLL_A13_PLL2, a13_pll2_recalc, a13_pll2_set_freq, NULL),
1119 PLL(AWPLL_A23_PLL1, a23_pll1_recalc, a23_pll1_set_freq, NULL),
1120 PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL),
1121 PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init),
1122 PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),
1123 PLL(AWPLL_A83T_PLLCPUX, a83t_pllcpux_recalc, a83t_pllcpux_set_freq, NULL),
1124 PLL(AWPLL_A64_PLLHSIC, a64_pllhsic_recalc, NULL, a64_pllhsic_init),
1125 PLL(AWPLL_H3_PLL1, a23_pll1_recalc, h3_pll1_set_freq, NULL),
1126 PLL(AWPLL_H3_PLL2, h3_pll2_recalc, h3_pll2_set_freq, NULL),
1129 static struct ofw_compat_data compat_data[] = {
1130 { "allwinner,sun4i-a10-pll1-clk", AWPLL_A10_PLL1 },
1131 { "allwinner,sun4i-a10-pll2-clk", AWPLL_A10_PLL2 },
1132 { "allwinner,sun4i-a10-pll3-clk", AWPLL_A10_PLL3 },
1133 { "allwinner,sun4i-a10-pll5-clk", AWPLL_A10_PLL5 },
1134 { "allwinner,sun4i-a10-pll6-clk", AWPLL_A10_PLL6 },
1135 { "allwinner,sun5i-a13-pll2-clk", AWPLL_A13_PLL2 },
1136 { "allwinner,sun6i-a31-pll1-clk", AWPLL_A31_PLL1 },
1137 { "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 },
1138 { "allwinner,sun8i-a23-pll1-clk", AWPLL_A23_PLL1 },
1139 { "allwinner,sun8i-a83t-pllcpux-clk", AWPLL_A83T_PLLCPUX },
1140 { "allwinner,sun8i-h3-pll1-clk", AWPLL_H3_PLL1 },
1141 { "allwinner,sun8i-h3-pll2-clk", AWPLL_H3_PLL2 },
1142 { "allwinner,sun9i-a80-pll4-clk", AWPLL_A80_PLL4 },
1143 { "allwinner,sun50i-a64-pllhsic-clk", AWPLL_A64_PLLHSIC },
1148 aw_pll_init(struct clknode *clk, device_t dev)
1150 clknode_init_parent_idx(clk, 0);
1155 aw_pll_set_gate(struct clknode *clk, bool enable)
1157 struct aw_pll_sc *sc;
1160 sc = clknode_get_softc(clk);
1165 val |= AW_PLL_ENABLE;
1167 val &= ~AW_PLL_ENABLE;
1175 aw_pll_recalc(struct clknode *clk, uint64_t *freq)
1177 struct aw_pll_sc *sc;
1179 sc = clknode_get_softc(clk);
1181 if (aw_pll_func[sc->type].recalc == NULL)
1184 return (aw_pll_func[sc->type].recalc(sc, freq));
1188 aw_pll_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
1189 int flags, int *stop)
1191 struct aw_pll_sc *sc;
1193 sc = clknode_get_softc(clk);
1197 if (aw_pll_func[sc->type].set_freq == NULL)
1200 return (aw_pll_func[sc->type].set_freq(sc, fin, fout, flags));
1203 static clknode_method_t aw_pll_clknode_methods[] = {
1204 /* Device interface */
1205 CLKNODEMETHOD(clknode_init, aw_pll_init),
1206 CLKNODEMETHOD(clknode_set_gate, aw_pll_set_gate),
1207 CLKNODEMETHOD(clknode_recalc_freq, aw_pll_recalc),
1208 CLKNODEMETHOD(clknode_set_freq, aw_pll_set_freq),
1212 DEFINE_CLASS_1(aw_pll_clknode, aw_pll_clknode_class, aw_pll_clknode_methods,
1213 sizeof(struct aw_pll_sc), clknode_class);
1216 aw_pll_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
1217 const char *pclkname, const char *clkname, int index)
1219 enum aw_pll_type type;
1220 struct clknode_init_def clkdef;
1221 struct aw_pll_sc *sc;
1222 struct clknode *clk;
1225 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1227 memset(&clkdef, 0, sizeof(clkdef));
1229 clkdef.name = clkname;
1230 if (pclkname != NULL) {
1231 clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP,
1233 clkdef.parent_names[0] = pclkname;
1234 clkdef.parent_cnt = 1;
1236 clkdef.parent_cnt = 0;
1238 if (aw_pll_func[type].init != NULL) {
1239 error = aw_pll_func[type].init(device_get_parent(dev),
1242 device_printf(dev, "clock %s init failed\n", clkname);
1247 clk = clknode_create(clkdom, &aw_pll_clknode_class, &clkdef);
1249 device_printf(dev, "cannot create clock node\n");
1252 sc = clknode_get_softc(clk);
1253 sc->clkdev = device_get_parent(dev);
1258 clknode_register(clkdom, clk);
1260 OF_prop_free(__DECONST(char *, clkdef.parent_names));
1266 aw_pll_probe(device_t dev)
1268 if (!ofw_bus_status_okay(dev))
1271 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1274 device_set_desc(dev, "Allwinner PLL Clock");
1275 return (BUS_PROBE_DEFAULT);
1279 aw_pll_attach(device_t dev)
1281 struct clkdom *clkdom;
1283 int index, nout, error;
1290 node = ofw_bus_get_node(dev);
1292 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
1293 device_printf(dev, "couldn't parse 'reg' property\n");
1297 clkdom = clkdom_create(dev);
1299 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
1301 device_printf(dev, "no clock outputs found\n");
1306 if (clk_get_by_ofw_index(dev, 0, 0, &clk_parent) != 0)
1309 for (index = 0; index < nout; index++) {
1310 error = aw_pll_create(dev, paddr, clkdom,
1311 clk_parent ? clk_get_name(clk_parent) : NULL,
1312 names[index], nout == 1 ? 1 : index);
1317 if (clkdom_finit(clkdom) != 0) {
1318 device_printf(dev, "cannot finalize clkdom initialization\n");
1324 clkdom_dump(clkdom);
1332 static device_method_t aw_pll_methods[] = {
1333 /* Device interface */
1334 DEVMETHOD(device_probe, aw_pll_probe),
1335 DEVMETHOD(device_attach, aw_pll_attach),
1340 static driver_t aw_pll_driver = {
1346 static devclass_t aw_pll_devclass;
1348 EARLY_DRIVER_MODULE(aw_pll, simplebus, aw_pll_driver,
1349 aw_pll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);