2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner USB clocks
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
48 #include <dev/extres/clk/clk_gate.h>
49 #include <dev/extres/hwreset/hwreset.h>
51 #include "clkdev_if.h"
52 #include "hwreset_if.h"
54 #define A10_SCLK_GATING_USBPHY (1 << 8)
55 #define A10_SCLK_GATING_OHCI1 (1 << 7)
56 #define A10_SCLK_GATING_OHCI0 (1 << 6)
58 #define USBPHY2_RST (1 << 2)
59 #define USBPHY1_RST (1 << 1)
60 #define USBPHY0_RST (1 << 0)
70 static struct ofw_compat_data compat_data[] = {
71 { "allwinner,sun4i-a10-usb-clk", AW_A10_USBCLK },
72 { "allwinner,sun5i-a13-usb-clk", AW_A13_USBCLK },
73 { "allwinner,sun6i-a31-usb-clk", AW_A31_USBCLK },
74 { "allwinner,sun8i-a83t-usb-clk", AW_A83T_USBCLK },
75 { "allwinner,sun8i-h3-usb-clk", AW_H3_USBCLK },
79 /* Clock indices for A10, as there is no clock-indices property in the DT */
80 static uint32_t aw_usbclk_indices_a10[] = { 6, 7, 8 };
81 /* Clock indices for H3, as there is no clock-indices property in the DT */
82 static uint32_t aw_usbclk_indices_h3[] = { 8, 9, 10, 11, 16, 17, 18, 19 };
84 struct aw_usbclk_softc {
89 aw_usbclk_hwreset_assert(device_t dev, intptr_t id, bool value)
91 struct aw_usbclk_softc *sc;
96 sc = device_get_softc(dev);
97 pdev = device_get_parent(dev);
99 mask = USBPHY0_RST << id;
101 CLKDEV_DEVICE_LOCK(pdev);
102 error = CLKDEV_MODIFY_4(pdev, sc->reg, mask, value ? 0 : mask);
103 CLKDEV_DEVICE_UNLOCK(pdev);
109 aw_usbclk_hwreset_is_asserted(device_t dev, intptr_t id, bool *value)
111 struct aw_usbclk_softc *sc;
116 sc = device_get_softc(dev);
117 pdev = device_get_parent(dev);
119 mask = USBPHY0_RST << id;
121 CLKDEV_DEVICE_LOCK(pdev);
122 error = CLKDEV_READ_4(pdev, sc->reg, &val);
123 CLKDEV_DEVICE_UNLOCK(pdev);
128 *value = (val & mask) != 0 ? false : true;
134 aw_usbclk_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
135 const char *pclkname, const char *clkname, int index)
137 const char *parent_names[1] = { pclkname };
138 struct clk_gate_def def;
140 memset(&def, 0, sizeof(def));
141 def.clkdef.id = index;
142 def.clkdef.name = clkname;
143 def.clkdef.parent_names = parent_names;
144 def.clkdef.parent_cnt = 1;
151 return (clknode_gate_register(clkdom, &def));
155 aw_usbclk_probe(device_t dev)
157 if (!ofw_bus_status_okay(dev))
160 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
163 device_set_desc(dev, "Allwinner USB Clocks");
164 return (BUS_PROBE_DEFAULT);
168 aw_usbclk_attach(device_t dev)
170 struct aw_usbclk_softc *sc;
171 struct clkdom *clkdom;
174 int index, nout, error;
175 enum aw_usbclk_type type;
177 clk_t clk_parent, clk_parent_pll;
181 sc = device_get_softc(dev);
182 node = ofw_bus_get_node(dev);
184 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
186 if (ofw_reg_to_paddr(node, 0, &sc->reg, &psize, NULL) != 0) {
187 device_printf(dev, "cannot parse 'reg' property\n");
191 clkdom = clkdom_create(dev);
193 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
195 device_printf(dev, "no clock outputs found\n");
200 if (indices == NULL && type == AW_A10_USBCLK)
201 indices = aw_usbclk_indices_a10;
202 else if (indices == NULL && type == AW_H3_USBCLK)
203 indices = aw_usbclk_indices_h3;
205 error = clk_get_by_ofw_index(dev, 0, 0, &clk_parent);
207 device_printf(dev, "cannot parse clock parent\n");
210 if (type == AW_A83T_USBCLK) {
211 error = clk_get_by_ofw_index(dev, 0, 1, &clk_parent_pll);
213 device_printf(dev, "cannot parse pll clock parent\n");
218 for (index = 0; index < nout; index++) {
219 if (strcmp(names[index], "usb_hsic_pll") == 0)
220 pname = clk_get_name(clk_parent_pll);
222 pname = clk_get_name(clk_parent);
223 error = aw_usbclk_create(dev, sc->reg, clkdom, pname,
224 names[index], indices != NULL ? indices[index] : index);
229 if (clkdom_finit(clkdom) != 0) {
230 device_printf(dev, "cannot finalize clkdom initialization\n");
238 hwreset_register_ofw_provider(dev);
246 static device_method_t aw_usbclk_methods[] = {
247 /* Device interface */
248 DEVMETHOD(device_probe, aw_usbclk_probe),
249 DEVMETHOD(device_attach, aw_usbclk_attach),
251 /* Reset interface */
252 DEVMETHOD(hwreset_assert, aw_usbclk_hwreset_assert),
253 DEVMETHOD(hwreset_is_asserted, aw_usbclk_hwreset_is_asserted),
258 static driver_t aw_usbclk_driver = {
261 sizeof(struct aw_usbclk_softc)
264 static devclass_t aw_usbclk_devclass;
266 EARLY_DRIVER_MODULE(aw_usbclk, simplebus, aw_usbclk_driver,
267 aw_usbclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);