sys/arm/allwinner/clkng/aw_ccung.c

   1 /*-
   2  * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  19  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  21  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  22  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 /*
  30  * Allwinner Clock Control Unit
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/bus.h>
  39 #include <sys/rman.h>
  40 #include <sys/kernel.h>
  41 #include <sys/module.h>
  42 #include <machine/bus.h>
  43
  44 #include <dev/fdt/simplebus.h>
  45
  46 #include <dev/ofw/ofw_bus.h>
  47 #include <dev/ofw/ofw_bus_subr.h>
  48
  49 #include <dev/extres/clk/clk.h>
  50 #include <dev/extres/clk/clk_gate.h>
  51
  52 #include <dev/extres/hwreset/hwreset.h>
  53
  54 #include <arm/allwinner/clkng/aw_ccung.h>
  55 #include <arm/allwinner/clkng/aw_clk.h>
  56
  57 #ifdef __aarch64__
  58 #include "opt_soc.h"
  59 #endif
  60
  61 #if defined(SOC_ALLWINNER_A13)
  62 #include <arm/allwinner/clkng/ccu_a13.h>
  63 #endif
  64
  65 #if defined(SOC_ALLWINNER_A31)
  66 #include <arm/allwinner/clkng/ccu_a31.h>
  67 #endif
  68
  69 #if defined(SOC_ALLWINNER_A64)
  70 #include <arm/allwinner/clkng/ccu_a64.h>
  71 #include <arm/allwinner/clkng/ccu_sun8i_r.h>
  72 #endif
  73
  74 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
  75 #include <arm/allwinner/clkng/ccu_h3.h>
  76 #include <arm/allwinner/clkng/ccu_sun8i_r.h>
  77 #endif
  78
  79 #if defined(SOC_ALLWINNER_A83T)
  80 #include <arm/allwinner/clkng/ccu_a83t.h>
  81 #include <arm/allwinner/clkng/ccu_sun8i_r.h>
  82 #endif
  83
  84 #include "clkdev_if.h"
  85 #include "hwreset_if.h"
  86
  87 static struct resource_spec aw_ccung_spec[] = {
  88         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  89         { -1, 0 }
  90 };
  91
  92 static struct ofw_compat_data compat_data[] = {
  93 #if defined(SOC_ALLWINNER_A31)
  94         { "allwinner,sun5i-a13-ccu", A13_CCU},
  95 #endif
  96 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
  97         { "allwinner,sun8i-h3-ccu", H3_CCU },
  98         { "allwinner,sun50i-h5-ccu", H3_CCU },
  99         { "allwinner,sun8i-h3-r-ccu", H3_R_CCU },
 100 #endif
 101 #if defined(SOC_ALLWINNER_A31)
 102         { "allwinner,sun6i-a31-ccu", A31_CCU },
 103 #endif
 104 #if defined(SOC_ALLWINNER_A64)
 105         { "allwinner,sun50i-a64-ccu", A64_CCU },
 106         { "allwinner,sun50i-a64-r-ccu", A64_R_CCU },
 107 #endif
 108 #if defined(SOC_ALLWINNER_A83T)
 109         { "allwinner,sun8i-a83t-ccu", A83T_CCU },
 110         { "allwinner,sun8i-a83t-r-ccu", A83T_R_CCU },
 111 #endif
 112         {NULL, 0 }
 113 };
 114
 115 #define CCU_READ4(sc, reg)              bus_read_4((sc)->res, (reg))
 116 #define CCU_WRITE4(sc, reg, val)        bus_write_4((sc)->res, (reg), (val))
 117
 118 static int
 119 aw_ccung_write_4(device_t dev, bus_addr_t addr, uint32_t val)
 120 {
 121         struct aw_ccung_softc *sc;
 122
 123         sc = device_get_softc(dev);
 124         CCU_WRITE4(sc, addr, val);
 125         return (0);
 126 }
 127
 128 static int
 129 aw_ccung_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
 130 {
 131         struct aw_ccung_softc *sc;
 132
 133         sc = device_get_softc(dev);
 134
 135         *val = CCU_READ4(sc, addr);
 136         return (0);
 137 }
 138
 139 static int
 140 aw_ccung_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
 141 {
 142         struct aw_ccung_softc *sc;
 143         uint32_t reg;
 144
 145         sc = device_get_softc(dev);
 146
 147         reg = CCU_READ4(sc, addr);
 148         reg &= ~clr;
 149         reg |= set;
 150         CCU_WRITE4(sc, addr, reg);
 151
 152         return (0);
 153 }
 154
 155 static int
 156 aw_ccung_reset_assert(device_t dev, intptr_t id, bool reset)
 157 {
 158         struct aw_ccung_softc *sc;
 159         uint32_t val;
 160
 161         sc = device_get_softc(dev);
 162
 163         if (id >= sc->nresets || sc->resets[id].offset == 0)
 164                 return (0);
 165
 166         mtx_lock(&sc->mtx);
 167         val = CCU_READ4(sc, sc->resets[id].offset);
 168         if (reset)
 169                 val &= ~(1 << sc->resets[id].shift);
 170         else
 171                 val |= 1 << sc->resets[id].shift;
 172         CCU_WRITE4(sc, sc->resets[id].offset, val);
 173         mtx_unlock(&sc->mtx);
 174
 175         return (0);
 176 }
 177
 178 static int
 179 aw_ccung_reset_is_asserted(device_t dev, intptr_t id, bool *reset)
 180 {
 181         struct aw_ccung_softc *sc;
 182         uint32_t val;
 183
 184         sc = device_get_softc(dev);
 185
 186         if (id >= sc->nresets || sc->resets[id].offset == 0)
 187                 return (0);
 188
 189         mtx_lock(&sc->mtx);
 190         val = CCU_READ4(sc, sc->resets[id].offset);
 191         *reset = (val & (1 << sc->resets[id].shift)) != 0 ? false : true;
 192         mtx_unlock(&sc->mtx);
 193
 194         return (0);
 195 }
 196
 197 static void
 198 aw_ccung_device_lock(device_t dev)
 199 {
 200         struct aw_ccung_softc *sc;
 201
 202         sc = device_get_softc(dev);
 203         mtx_lock(&sc->mtx);
 204 }
 205
 206 static void
 207 aw_ccung_device_unlock(device_t dev)
 208 {
 209         struct aw_ccung_softc *sc;
 210
 211         sc = device_get_softc(dev);
 212         mtx_unlock(&sc->mtx);
 213 }
 214
 215 static int
 216 aw_ccung_probe(device_t dev)
 217 {
 218
 219         if (!ofw_bus_status_okay(dev))
 220                 return (ENXIO);
 221
 222         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 223                 return (ENXIO);
 224
 225         device_set_desc(dev, "Allwinner Clock Control Unit NG");
 226         return (BUS_PROBE_DEFAULT);
 227 }
 228
 229 static int
 230 aw_ccung_register_gates(struct aw_ccung_softc *sc)
 231 {
 232         struct clk_gate_def def;
 233         int i;
 234
 235         for (i = 0; i < sc->ngates; i++) {
 236                 if (sc->gates[i].name == NULL)
 237                         continue;
 238                 memset(&def, 0, sizeof(def));
 239                 def.clkdef.id = i;
 240                 def.clkdef.name = sc->gates[i].name;
 241                 def.clkdef.parent_names = &sc->gates[i].parent_name;
 242                 def.clkdef.parent_cnt = 1;
 243                 def.offset = sc->gates[i].offset;
 244                 def.shift = sc->gates[i].shift;
 245                 def.mask = 1;
 246                 def.on_value = 1;
 247                 def.off_value = 0;
 248                 clknode_gate_register(sc->clkdom, &def);
 249         }
 250
 251         return (0);
 252 }
 253
 254 static void
 255 aw_ccung_init_clocks(struct aw_ccung_softc *sc)
 256 {
 257         struct clknode *clknode;
 258         int i, error;
 259
 260         for (i = 0; i < sc->n_clk_init; i++) {
 261                 clknode = clknode_find_by_name(sc->clk_init[i].name);
 262                 if (clknode == NULL) {
 263                         device_printf(sc->dev, "Cannot find clock %s\n",
 264                             sc->clk_init[i].name);
 265                         continue;
 266                 }
 267
 268                 if (sc->clk_init[i].parent_name != NULL) {
 269                         if (bootverbose)
 270                                 device_printf(sc->dev, "Setting %s as parent for %s\n",
 271                                     sc->clk_init[i].parent_name,
 272                                     sc->clk_init[i].name);
 273                         error = clknode_set_parent_by_name(clknode,
 274                             sc->clk_init[i].parent_name);
 275                         if (error != 0) {
 276                                 device_printf(sc->dev,
 277                                     "Cannot set parent to %s for %s\n",
 278                                     sc->clk_init[i].parent_name,
 279                                     sc->clk_init[i].name);
 280                                 continue;
 281                         }
 282                 }
 283                 if (sc->clk_init[i].default_freq != 0) {
 284                         error = clknode_set_freq(clknode,
 285                             sc->clk_init[i].default_freq, 0 , 0);
 286                         if (error != 0) {
 287                                 device_printf(sc->dev,
 288                                     "Cannot set frequency for %s to %ju\n",
 289                                     sc->clk_init[i].name,
 290                                     sc->clk_init[i].default_freq);
 291                                 continue;
 292                         }
 293                 }
 294                 if (sc->clk_init[i].enable) {
 295                         error = clknode_enable(clknode);
 296                         if (error != 0) {
 297                                 device_printf(sc->dev,
 298                                     "Cannot enable %s\n",
 299                                     sc->clk_init[i].name);
 300                                 continue;
 301                         }
 302                 }
 303         }
 304 }
 305
 306 static int
 307 aw_ccung_attach(device_t dev)
 308 {
 309         struct aw_ccung_softc *sc;
 310
 311         sc = device_get_softc(dev);
 312         sc->dev = dev;
 313
 314         if (bus_alloc_resources(dev, aw_ccung_spec, &sc->res) != 0) {
 315                 device_printf(dev, "cannot allocate resources for device\n");
 316                 return (ENXIO);
 317         }
 318
 319         mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 320
 321         sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
 322
 323         sc->clkdom = clkdom_create(dev);
 324         if (sc->clkdom == NULL)
 325                 panic("Cannot create clkdom\n");
 326
 327         switch (sc->type) {
 328 #if defined(SOC_ALLWINNER_A13)
 329         case A13_CCU:
 330                 ccu_a13_register_clocks(sc);
 331                 break;
 332 #endif
 333 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
 334         case H3_CCU:
 335                 ccu_h3_register_clocks(sc);
 336                 break;
 337         case H3_R_CCU:
 338                 ccu_sun8i_r_register_clocks(sc);
 339                 break;
 340 #endif
 341 #if defined(SOC_ALLWINNER_A31)
 342         case A31_CCU:
 343                 ccu_a31_register_clocks(sc);
 344                 break;
 345 #endif
 346 #if defined(SOC_ALLWINNER_A64)
 347         case A64_CCU:
 348                 ccu_a64_register_clocks(sc);
 349                 break;
 350         case A64_R_CCU:
 351                 ccu_sun8i_r_register_clocks(sc);
 352                 break;
 353 #endif
 354 #if defined(SOC_ALLWINNER_A83T)
 355         case A83T_CCU:
 356                 ccu_a83t_register_clocks(sc);
 357                 break;
 358         case A83T_R_CCU:
 359                 ccu_sun8i_r_register_clocks(sc);
 360                 break;
 361 #endif
 362         }
 363
 364         if (sc->gates)
 365                 aw_ccung_register_gates(sc);
 366         if (clkdom_finit(sc->clkdom) != 0)
 367                 panic("cannot finalize clkdom initialization\n");
 368
 369         clkdom_xlock(sc->clkdom);
 370         aw_ccung_init_clocks(sc);
 371         clkdom_unlock(sc->clkdom);
 372
 373         if (bootverbose)
 374                 clkdom_dump(sc->clkdom);
 375
 376         /* If we have resets, register our self as a reset provider */
 377         if (sc->resets)
 378                 hwreset_register_ofw_provider(dev);
 379
 380         return (0);
 381 }
 382
 383 static device_method_t aw_ccung_methods[] = {
 384         /* Device interface */
 385         DEVMETHOD(device_probe,         aw_ccung_probe),
 386         DEVMETHOD(device_attach,        aw_ccung_attach),
 387
 388         /* clkdev interface */
 389         DEVMETHOD(clkdev_write_4,       aw_ccung_write_4),
 390         DEVMETHOD(clkdev_read_4,        aw_ccung_read_4),
 391         DEVMETHOD(clkdev_modify_4,      aw_ccung_modify_4),
 392         DEVMETHOD(clkdev_device_lock,   aw_ccung_device_lock),
 393         DEVMETHOD(clkdev_device_unlock, aw_ccung_device_unlock),
 394
 395         /* Reset interface */
 396         DEVMETHOD(hwreset_assert,       aw_ccung_reset_assert),
 397         DEVMETHOD(hwreset_is_asserted,  aw_ccung_reset_is_asserted),
 398
 399         DEVMETHOD_END
 400 };
 401
 402 static driver_t aw_ccung_driver = {
 403         "aw_ccung",
 404         aw_ccung_methods,
 405         sizeof(struct aw_ccung_softc),
 406 };
 407
 408 static devclass_t aw_ccung_devclass;
 409
 410 EARLY_DRIVER_MODULE(aw_ccung, simplebus, aw_ccung_driver, aw_ccung_devclass,
 411     0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
 412 MODULE_VERSION(aw_ccung, 1);