2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Allwinner Clock Control Unit
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <machine/bus.h>
45 #include <dev/fdt/simplebus.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/extres/clk/clk.h>
51 #include <dev/extres/clk/clk_gate.h>
53 #include <dev/extres/hwreset/hwreset.h>
55 #include <arm/allwinner/clkng/aw_ccung.h>
56 #include <arm/allwinner/clkng/aw_clk.h>
62 #include "clkdev_if.h"
63 #include "hwreset_if.h"
65 static struct resource_spec aw_ccung_spec[] = {
66 { SYS_RES_MEMORY, 0, RF_ACTIVE },
70 #define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))
71 #define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
74 aw_ccung_write_4(device_t dev, bus_addr_t addr, uint32_t val)
76 struct aw_ccung_softc *sc;
78 sc = device_get_softc(dev);
79 CCU_WRITE4(sc, addr, val);
84 aw_ccung_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
86 struct aw_ccung_softc *sc;
88 sc = device_get_softc(dev);
90 *val = CCU_READ4(sc, addr);
95 aw_ccung_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
97 struct aw_ccung_softc *sc;
100 sc = device_get_softc(dev);
102 reg = CCU_READ4(sc, addr);
105 CCU_WRITE4(sc, addr, reg);
111 aw_ccung_reset_assert(device_t dev, intptr_t id, bool reset)
113 struct aw_ccung_softc *sc;
116 sc = device_get_softc(dev);
118 if (id >= sc->nresets || sc->resets[id].offset == 0)
122 val = CCU_READ4(sc, sc->resets[id].offset);
124 val &= ~(1 << sc->resets[id].shift);
126 val |= 1 << sc->resets[id].shift;
127 CCU_WRITE4(sc, sc->resets[id].offset, val);
128 mtx_unlock(&sc->mtx);
134 aw_ccung_reset_is_asserted(device_t dev, intptr_t id, bool *reset)
136 struct aw_ccung_softc *sc;
139 sc = device_get_softc(dev);
141 if (id >= sc->nresets || sc->resets[id].offset == 0)
145 val = CCU_READ4(sc, sc->resets[id].offset);
146 *reset = (val & (1 << sc->resets[id].shift)) != 0 ? false : true;
147 mtx_unlock(&sc->mtx);
153 aw_ccung_device_lock(device_t dev)
155 struct aw_ccung_softc *sc;
157 sc = device_get_softc(dev);
162 aw_ccung_device_unlock(device_t dev)
164 struct aw_ccung_softc *sc;
166 sc = device_get_softc(dev);
167 mtx_unlock(&sc->mtx);
171 aw_ccung_register_gates(struct aw_ccung_softc *sc)
173 struct clk_gate_def def;
176 for (i = 0; i < sc->ngates; i++) {
177 if (sc->gates[i].name == NULL)
179 memset(&def, 0, sizeof(def));
181 def.clkdef.name = sc->gates[i].name;
182 def.clkdef.parent_names = &sc->gates[i].parent_name;
183 def.clkdef.parent_cnt = 1;
184 def.offset = sc->gates[i].offset;
185 def.shift = sc->gates[i].shift;
189 clknode_gate_register(sc->clkdom, &def);
196 aw_ccung_init_clocks(struct aw_ccung_softc *sc)
198 struct clknode *clknode;
201 for (i = 0; i < sc->n_clk_init; i++) {
202 clknode = clknode_find_by_name(sc->clk_init[i].name);
203 if (clknode == NULL) {
204 device_printf(sc->dev, "Cannot find clock %s\n",
205 sc->clk_init[i].name);
209 if (sc->clk_init[i].parent_name != NULL) {
211 device_printf(sc->dev, "Setting %s as parent for %s\n",
212 sc->clk_init[i].parent_name,
213 sc->clk_init[i].name);
214 error = clknode_set_parent_by_name(clknode,
215 sc->clk_init[i].parent_name);
217 device_printf(sc->dev,
218 "Cannot set parent to %s for %s\n",
219 sc->clk_init[i].parent_name,
220 sc->clk_init[i].name);
224 if (sc->clk_init[i].default_freq != 0) {
225 error = clknode_set_freq(clknode,
226 sc->clk_init[i].default_freq, 0 , 0);
228 device_printf(sc->dev,
229 "Cannot set frequency for %s to %ju\n",
230 sc->clk_init[i].name,
231 sc->clk_init[i].default_freq);
235 if (sc->clk_init[i].enable) {
236 error = clknode_enable(clknode);
238 device_printf(sc->dev,
239 "Cannot enable %s\n",
240 sc->clk_init[i].name);
248 aw_ccung_attach(device_t dev)
250 struct aw_ccung_softc *sc;
253 sc = device_get_softc(dev);
256 if (bus_alloc_resources(dev, aw_ccung_spec, &sc->res) != 0) {
257 device_printf(dev, "cannot allocate resources for device\n");
261 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
263 sc->clkdom = clkdom_create(dev);
264 if (sc->clkdom == NULL)
265 panic("Cannot create clkdom\n");
267 for (i = 0; i < sc->nclks; i++) {
268 switch (sc->clks[i].type) {
269 case AW_CLK_UNDEFINED:
272 clknode_mux_register(sc->clkdom, sc->clks[i].clk.mux);
275 clknode_div_register(sc->clkdom, sc->clks[i].clk.div);
278 clknode_fixed_register(sc->clkdom,
279 sc->clks[i].clk.fixed);
282 aw_clk_nkmp_register(sc->clkdom, sc->clks[i].clk.nkmp);
285 aw_clk_nm_register(sc->clkdom, sc->clks[i].clk.nm);
287 case AW_CLK_PREDIV_MUX:
288 aw_clk_prediv_mux_register(sc->clkdom,
289 sc->clks[i].clk.prediv_mux);
295 aw_ccung_register_gates(sc);
296 if (clkdom_finit(sc->clkdom) != 0)
297 panic("cannot finalize clkdom initialization\n");
299 clkdom_xlock(sc->clkdom);
300 aw_ccung_init_clocks(sc);
301 clkdom_unlock(sc->clkdom);
304 clkdom_dump(sc->clkdom);
306 /* If we have resets, register our self as a reset provider */
308 hwreset_register_ofw_provider(dev);
313 static device_method_t aw_ccung_methods[] = {
314 /* clkdev interface */
315 DEVMETHOD(clkdev_write_4, aw_ccung_write_4),
316 DEVMETHOD(clkdev_read_4, aw_ccung_read_4),
317 DEVMETHOD(clkdev_modify_4, aw_ccung_modify_4),
318 DEVMETHOD(clkdev_device_lock, aw_ccung_device_lock),
319 DEVMETHOD(clkdev_device_unlock, aw_ccung_device_unlock),
321 /* Reset interface */
322 DEVMETHOD(hwreset_assert, aw_ccung_reset_assert),
323 DEVMETHOD(hwreset_is_asserted, aw_ccung_reset_is_asserted),
328 DEFINE_CLASS_0(aw_ccung, aw_ccung_driver, aw_ccung_methods,
329 sizeof(struct aw_ccung_softc));