2 * Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <dev/extres/clk/clk.h>
37 #include <arm/allwinner/clkng/aw_clk.h>
38 #include <arm/allwinner/clkng/aw_clk_mipi.h>
40 #include "clkdev_if.h"
42 /* #define dprintf(format, arg...) printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */
43 #define dprintf(format, arg...)
46 * clknode for PLL_MIPI :
48 * clk = (pll_video0 * n * k) / m when vfb_sel=0
49 * clk depend on sint_frac, sdiv2, s6p25_7p5, pll_feedback_div when vfb_sel=1
53 struct aw_clk_mipi_sc {
56 struct aw_clk_factor k;
57 struct aw_clk_factor m;
58 struct aw_clk_factor n;
65 uint32_t lock_retries;
70 #define WRITE4(_clk, off, val) \
71 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
72 #define READ4(_clk, off, val) \
73 CLKDEV_READ_4(clknode_get_device(_clk), off, val)
74 #define DEVICE_LOCK(_clk) \
75 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
76 #define DEVICE_UNLOCK(_clk) \
77 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
79 #define LDO1_EN_SHIFT 23
80 #define LDO2_EN_SHIFT 22
81 #define VFB_SEL_SHIFT 16
84 aw_clk_mipi_init(struct clknode *clk, device_t dev)
86 struct aw_clk_mipi_sc *sc;
88 sc = clknode_get_softc(clk);
90 clknode_init_parent_idx(clk, 0);
95 aw_clk_mipi_set_gate(struct clknode *clk, bool enable)
97 struct aw_clk_mipi_sc *sc;
100 sc = clknode_get_softc(clk);
102 dprintf("%sabling gate\n", enable ? "En" : "Dis");
104 READ4(clk, sc->offset, &val);
106 val |= (1 << sc->gate_shift);
107 val |= (1 << LDO1_EN_SHIFT);
108 val |= (1 << LDO2_EN_SHIFT);
110 val &= ~(1 << sc->gate_shift);
111 val &= ~(1 << LDO1_EN_SHIFT);
112 val &= ~(1 << LDO2_EN_SHIFT);
114 WRITE4(clk, sc->offset, val);
121 aw_clk_mipi_find_best(struct aw_clk_mipi_sc *sc, uint64_t fparent, uint64_t *fout,
122 uint32_t *factor_k, uint32_t *factor_m, uint32_t *factor_n)
132 for (n = aw_clk_factor_get_min(&sc->n); n <= aw_clk_factor_get_max(&sc->n); ) {
133 for (k = aw_clk_factor_get_min(&sc->k); k <= aw_clk_factor_get_max(&sc->k); ) {
134 for (m = aw_clk_factor_get_min(&sc->m); m <= aw_clk_factor_get_max(&sc->m); ) {
135 cur = (fparent * n * k) / m;
136 if ((*fout - cur) < (*fout - best)) {
155 aw_clk_mipi_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
156 int flags, int *stop)
158 struct aw_clk_mipi_sc *sc;
160 uint32_t best_k, best_m, best_n;
165 sc = clknode_get_softc(clk);
167 best = aw_clk_mipi_find_best(sc, fparent, fout, &best_k, &best_m, &best_n);
169 if (best < sc->min_freq ||
170 best > sc->max_freq) {
171 printf("%s: Cannot set %ju for %s (min=%ju max=%ju)\n",
172 __func__, best, clknode_get_name(clk),
173 sc->min_freq, sc->max_freq);
176 if ((flags & CLK_SET_DRYRUN) != 0) {
183 READ4(clk, sc->offset, &val);
184 /* Disable clock during freq changes */
185 val &= ~(1 << sc->gate_shift);
186 WRITE4(clk, sc->offset, val);
188 k = aw_clk_factor_get_value(&sc->k, best_k);
189 n = aw_clk_factor_get_value(&sc->n, best_n);
190 m = aw_clk_factor_get_value(&sc->m, best_m);
194 val |= k << sc->k.shift;
195 val |= m << sc->m.shift;
196 val |= n << sc->n.shift;
198 /* Write the clock changes */
199 WRITE4(clk, sc->offset, val);
201 /* Enable clock now that we've change it */
202 val |= 1 << sc->gate_shift;
203 WRITE4(clk, sc->offset, val);
206 for (retry = 0; retry < sc->lock_retries; retry++) {
207 READ4(clk, sc->offset, &val);
208 if ((val & (1 << sc->lock_shift)) != 0)
220 aw_clk_mipi_recalc(struct clknode *clk, uint64_t *freq)
222 struct aw_clk_mipi_sc *sc;
223 uint32_t val, m, n, k;
225 sc = clknode_get_softc(clk);
228 READ4(clk, sc->offset, &val);
231 k = aw_clk_get_factor(val, &sc->k);
232 m = aw_clk_get_factor(val, &sc->m);
233 n = aw_clk_get_factor(val, &sc->n);
235 *freq = (*freq * n * k) / m;
240 static clknode_method_t aw_mipi_clknode_methods[] = {
241 /* Device interface */
242 CLKNODEMETHOD(clknode_init, aw_clk_mipi_init),
243 CLKNODEMETHOD(clknode_set_gate, aw_clk_mipi_set_gate),
244 CLKNODEMETHOD(clknode_recalc_freq, aw_clk_mipi_recalc),
245 CLKNODEMETHOD(clknode_set_freq, aw_clk_mipi_set_freq),
249 DEFINE_CLASS_1(aw_mipi_clknode, aw_mipi_clknode_class, aw_mipi_clknode_methods,
250 sizeof(struct aw_clk_mipi_sc), clknode_class);
253 aw_clk_mipi_register(struct clkdom *clkdom, struct aw_clk_mipi_def *clkdef)
256 struct aw_clk_mipi_sc *sc;
258 clk = clknode_create(clkdom, &aw_mipi_clknode_class, &clkdef->clkdef);
262 sc = clknode_get_softc(clk);
264 sc->offset = clkdef->offset;
266 sc->k.shift = clkdef->k.shift;
267 sc->k.width = clkdef->k.width;
268 sc->k.mask = ((1 << sc->k.width) - 1) << sc->k.shift;
269 sc->k.value = clkdef->k.value;
270 sc->k.flags = clkdef->k.flags;
271 sc->k.min_value = clkdef->k.min_value;
273 sc->m.shift = clkdef->m.shift;
274 sc->m.width = clkdef->m.width;
275 sc->m.mask = ((1 << sc->m.width) - 1) << sc->m.shift;
276 sc->m.value = clkdef->m.value;
277 sc->m.flags = clkdef->m.flags;
278 sc->m.min_value = clkdef->m.min_value;
280 sc->n.shift = clkdef->n.shift;
281 sc->n.width = clkdef->n.width;
282 sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
283 sc->n.value = clkdef->n.value;
284 sc->n.flags = clkdef->n.flags;
285 sc->n.min_value = clkdef->n.min_value;
287 sc->min_freq = clkdef->min_freq;
288 sc->max_freq = clkdef->max_freq;
290 sc->gate_shift = clkdef->gate_shift;
292 sc->lock_shift = clkdef->lock_shift;
293 sc->lock_retries = clkdef->lock_retries;
295 sc->flags = clkdef->flags;
297 clknode_register(clkdom, clk);